CN106783729A - A kind of method that substrate contact is drawn under SOI - Google Patents
A kind of method that substrate contact is drawn under SOI Download PDFInfo
- Publication number
- CN106783729A CN106783729A CN201611196503.6A CN201611196503A CN106783729A CN 106783729 A CN106783729 A CN 106783729A CN 201611196503 A CN201611196503 A CN 201611196503A CN 106783729 A CN106783729 A CN 106783729A
- Authority
- CN
- China
- Prior art keywords
- contact
- soi
- substrate
- drawn
- under
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
Abstract
The method that the present invention provides substrate contact extraction under a kind of SOI, including:Step 1), the contact lead-out area of substrate is defined, using the etching technics of fairlead, the contact lead-out area of substrate under SOI is opened from the upper surface of SOI;Step 2), contact lead-out area is carried out metal filled, and realize that the electricity of substrate under SOI is drawn by metal interconnection technique;Wherein, the contact with the component on SOI of substrate lead-out area is drawn and is made a plate using same photoetching under SOI, and the etching technics and metal filling processes of substrate contact lead-out area use same processing step with the etching technics and metal filling processes of component contact hole respectively under SOI.The method of the present invention is on the one hand compatible with existing common process, does not on the other hand need extra mask plate, so as to extra cost need not be increased, realizes the electricity extraction of substrate under SOI.Present invention process step is simple, and is conducive to the reduction of cost, is with a wide range of applications in field of semiconductor manufacture.
Description
Technical field
The present invention relates to field of semiconductor manufacture, the method that substrate contact is drawn under more particularly to a kind of SOI.
Background technology
SOI wafer substrate zone passes through the natural electric isolation of oxygen buried layer with the device region on surface.But needed in many applications
Substrate zone electricity is drawn, carrys out controlling potential or eliminate chip to prepare the antenna effect (antenna effect) for occurring.
The Normal practice of prior art is, using additional etch technique, in substrate zone etching dedicated pin hole, to fill out afterwards
Metal material is filled, realizes that electricity is drawn.A kind of electricity of existing SOI wafer substrate zone is drawn and is comprised the following steps:
The first step, makes component in SOI wafer, and the component needs to carry out electricity with one or more
The region of extraction;
Second step, dielectric layer is formed on the SOI wafer surface;
3rd step, draws photoetching and makes a plate using the contact of component, etches the contact lead-out area of component;
4th step, draws photoetching and makes a plate using the contact of substrate under SOI wafer, etches the contact of substrate under SOI wafer
Lead-out area;
5th step, is carried out metal filled to the contact lead-out area of the component;
6th step, is carried out metal filled to the contact lead-out area of substrate under the SOI wafer;
7th step, realizes that the contact of substrate under SOI wafer is drawn and the component connects using metal interconnection technique
The electricity drawn is touched to draw.
It can be seen that, the electricity outbound course of traditional SOI wafer substrate zone is needed on the basis of common process, using extra
Technique, while needing the region of lead in order to define and needing the extra mask plate for preparing, it is disadvantageous in that, introduce volume
The compatibility issue brought after outer technique, and the increased problem of cost that extra technique and extra mask plate bring.
Based on the above, there is provided a kind of compatible with existing common process, it is not necessary to extra mask plate, without increasing
Extra cost, it is possible to achieve the method that the electricity of substrate is drawn under SOI is necessary.
The content of the invention
The shortcoming of prior art, draws it is an object of the invention to provide substrate contact under a kind of SOI in view of the above
Method SOI under the method drawn of substrate contact, for solving in the prior art, substrate introduces what is brought after additional technique under SOI
Compatibility issue, and the increased problem of cost that extra technique and extra mask plate bring.
In order to achieve the above objects and other related objects, the method that the present invention provides substrate contact extraction under a kind of SOI, institute
Stating method includes step:Step 1), the contact lead-out area of substrate is defined, using the etching technics of fairlead, from the upper table of SOI
Open the contact lead-out area of substrate under SOI in face;Step 2), contact lead-out area is carried out metal filled and mutual by metal
Connection technique realizes the electricity extraction of substrate under SOI;Wherein, the contact with the component on SOI of substrate lead-out area is drawn under SOI
Made a plate using same photoetching, the etching technics and metal filling processes of substrate contact lead-out area connect with component respectively under SOI
The etching technics and metal filling processes of contact hole use same processing step.
A kind of preferred scheme of the method drawn as substrate contact under SOI of the invention, substrate contact draws under the SOI
The etching technics and the etching technics of component contact hole for going out region are using same technique and while carry out, lining under the SOI
The metal filling processes of metal filling processes and the component contact hole of bottom contact lead-out area are using same technique and simultaneously
Carry out.
A kind of preferred scheme of the method drawn as substrate contact under SOI of the invention, the contact of the component is drawn
Go out the source contact extraction including metal-oxide-semiconductor, drain contact extraction, substrate zone contact is drawn and gate contact is drawn, diode
Yang Qu contacts draw and the contact of cloudy area is drawn, the collecting zone contact of triode is drawn, launch site contact is drawn and base contact
Draw, active area and gate resistance contact are drawn, the upper bottom crown contact of mos capacitance is drawn, and the contact of optics is drawn, MEMS
One or more combinations that the contact of device is drawn.
Further, by controlling the etching selection ratio of etching technics, etching technics is made to stop at connecing for component respectively
Touch and draw substrate surface under surface and SOI.
A kind of preferred scheme of the method drawn as substrate contact under SOI of the invention, step 1) include:Step 1-
1), in component is produced on SOI, the component includes that the contact of component is drawn;Step 1-2), in the SOI upper tables
Face blanket dielectric layer;Step 1-3), made a plate using same photoetching, substrate lead-out area under SOI is used and the component on SOI
Contact draw simultaneously perform etching, by controlling the etching selection ratio of etching technics, etching technics is stopped at first device respectively
Substrate surface under surface and SOI is drawn in the contact of part.
A kind of preferred scheme of the method drawn as substrate contact under SOI of the invention, step 2) include:Step 2-
1) row metal, is entered to substrate contact lead-out area under the SOI and the component contact hole simultaneously using metal filling processes
Filling;Step 2-2), the electricity of substrate contact lead-out area and the component contact hole under SOI is realized by metal interconnection technique
Learn and draw.
A kind of preferred scheme of the method drawn as substrate contact under SOI of the invention, step 1) in, the etching work
Skill includes the one kind in ICP etching technics and RIE etching technics.
A kind of preferred scheme of the method drawn as substrate contact under SOI of the invention, step 2) in, metal filled institute
The metal material of use includes one or more combination or its alloy in copper, aluminium, silver, gold, platinum, titanium, tungsten.
As described above, the method that substrate contact is drawn under SOI of the invention, has the advantages that:
The present invention improves etching selection ratio by improving the fairlead etching technics in common process, etches fairlead
Stop at the substrate surface in the case where surface and SOI are drawn in the contact of component simultaneously such that it is able at the same realize SOI components and
The electricity of lower substrate zone is drawn.The method of the present invention is on the one hand compatible with existing common process, on the other hand need not be extra
Mask plate, so as to extra cost need not be increased, the electricity for realizing substrate under SOI is drawn.Present invention process step is simple, and
Be conducive to the reduction of cost, be with a wide range of applications in field of semiconductor manufacture.
Brief description of the drawings
The step of Fig. 1 is shown as the method that substrate contact is drawn under SOI of the invention schematic flow sheet.
Fig. 2~Fig. 6 is shown as the structural representation that each step of method that substrate contact is drawn under SOI of the invention is presented
Figure, wherein, Fig. 6 is the overlooking the structure diagram of each contact extraction electrode.
Component label instructions
101 times substrates
102 oxygen buried layers
103 top layer silicons
104 source regions
105 drain regions
106 grid regions
107 dielectric layers
Substrate contact fairlead under 108 SOI
109 source contact fairleads
110 drain contact fairleads
111 gate contact fairleads
Substrate contact draws metal under 112 SOI
113 source contacts draw metal
114 drain contacts draw metal
115 gate contacts draw metal
S11~S15 steps
Specific embodiment
Embodiments of the present invention are illustrated below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages of the invention and effect easily.The present invention can also be by specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Refer to Fig. 1~Fig. 6.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, package count when only display is with relevant component in the present invention rather than according to actual implementation in illustrating then
Mesh, shape and size are drawn, and the kenel of each component, quantity and ratio can be a kind of random change during its actual implementation, and its
Assembly layout kenel is likely to increasingly complex.
Embodiment 1
As shown in Fig. 1~Fig. 6, the method that the present embodiment provides substrate contact extraction under a kind of SOI, methods described includes step
Suddenly:
Step 1), the contact lead-out area of substrate is defined, using the etching technics of fairlead, opened from the upper surface of SOI
The contact lead-out area of substrate under SOI;
Step 2), contact lead-out area is carried out metal filled, and the electricity of substrate under SOI is realized by metal interconnection technique
Learn and draw;
Wherein, substrate lead-out area contact with the component on SOI extraction is made a plate using same photoetching under SOI, under SOI
The etching technics and metal filling processes of substrate contact lead-out area are filled out with the etching technics and metal of component contact hole respectively
Technique is filled using same processing step.
As an example, under the SOI etching technics of substrate contact lead-out area and component contact hole etching technics
It is using same technique and while carries out, the metal filling processes of substrate contact lead-out area are contacted with component under the SOI
The metal filling processes in hole are using same technique and while carry out.
In the present embodiment, the contact of the component is drawn includes that the source contact extraction of metal-oxide-semiconductor, drain contact are drawn
And gate contact is drawn.
As an example, the etching selection ratio by controlling etching technics, makes etching technics stop at connecing for component respectively
Touch and draw substrate surface under surface and SOI.
In a specific implementation process, the method that substrate contact is drawn under the SOI includes step:
As shown in figure 1, carrying out step 1-1 first) S11, in component is produced on SOI, the component includes first device
The contact of part is drawn;In the present embodiment, the SOI includes lower substrate 101, silica oxygen buried layer 102 and top layer silicon
103, the component is metal-oxide-semiconductor, and it at least includes source region 104, drain region 105 and grid region 106, and the contact of the component is drawn
Go out the source contact extraction including metal-oxide-semiconductor, drain contact extraction, substrate zone contact is drawn and gate contact is drawn.
As shown in figure 1, then carrying out step 1-2) S12, in SOI upper surfaces blanket dielectric layer 107;In the present embodiment
In, the dielectric layer 107 is silicon dioxide layer;
Step 1-3) S13, made a plate using same photoetching, the lead-out area of substrate under SOI 101 is used and the first device on SOI
The contact of part is drawn and is performed etching simultaneously, by controlling the etching selection ratio of etching technics, etching technics is stopped at unit respectively
Substrate surface under surface and SOI is drawn in the contact of device;In the present embodiment, substrate contact fairlead under SOI is etched
108, the source contact fairlead 109 of metal-oxide-semiconductor, drain contact fairlead 110 and gate contact fairlead 111.
As an example, the etching technics includes the one kind in ICP etching technics and RIE etching technics.In the present embodiment
In, it is ICP etching technics that the etching technics is selected.
Step 2-1) S14, using metal filling processes simultaneously to substrate contact lead-out area under the SOI and first device
Part contact hole carries out metal filled;After metal filled, substrate contact draws metal 112, the source contact of metal-oxide-semiconductor under obtaining SOI
Draw metal 113, drain contact and draw metal 114 and gate contact extraction metal 115.
Step 2-2) S15, realizes that substrate contact lead-out area and the component are contacted under SOI by metal interconnection technique
The electricity in hole is drawn.
As an example, metal filled used metal material include copper, aluminium, silver, gold, platinum, titanium, tungsten in one kind or
Two or more combinations or its alloy.In the present embodiment, it is metal filled using such as galvanoplastic, sputtering method, vapour deposition method
Technique, the metal material is the copper with preferable filling capacity.
Embodiment 2
The method that substrate contact is drawn under a kind of SOI of the present embodiment offer, its basic step such as embodiment 1, wherein, as
Example, the contact of the component is drawn includes that the Yang Qu contacts extraction of diode and cloudy area's contact are drawn.
Embodiment 3
The method that substrate contact is drawn under a kind of SOI of the present embodiment offer, its basic step such as embodiment 1, wherein, as
Example, the contact of the component is drawn includes that the collecting zone contact extraction of triode, launch site contact are drawn and base contact
Draw.
Embodiment 4
The method that substrate contact is drawn under a kind of SOI of the present embodiment offer, its basic step such as embodiment 1, wherein, as
Example, the contact of the component is drawn includes that the contact of MEMS is drawn.
Embodiment 5
The method that substrate contact is drawn under a kind of SOI of the present embodiment offer, its basic step such as embodiment 1, wherein, as
Example, the contact of the component is drawn includes that the upper bottom crown contact of mos capacitance is drawn.
Embodiment 6
The method that substrate contact is drawn under a kind of SOI of the present embodiment offer, its basic step such as embodiment 1, wherein, as
Example, the contact of the component is drawn includes that the contact of optics is drawn.
Embodiment 7
The method that substrate contact is drawn under a kind of SOI of the present embodiment offer, its basic step such as embodiment 1, wherein, as
Example, the contact of the component is drawn includes the source contact extraction of metal-oxide-semiconductor, drain contact is drawn and gate contact draws
Go out, the Yang Qu contacts of diode are drawn and cloudy area's contact is drawn and the collecting zone contact of triode is drawn, launch site contact is drawn
Go out and base contact draw combination.
As described above, the method that substrate contact is drawn under SOI of the invention, has the advantages that:
The present invention improves etching selection ratio by improving the fairlead etching technics in common process, etches fairlead
Stop at the substrate surface in the case where surface and SOI are drawn in the contact of component simultaneously such that it is able at the same realize SOI components and
The electricity of lower substrate zone is drawn.The method of the present invention is on the one hand compatible with existing common process, on the other hand need not be extra
Mask plate, so as to extra cost need not be increased, the electricity for realizing substrate under SOI is drawn.Present invention process step is simple, and
Be conducive to the reduction of cost, be with a wide range of applications in field of semiconductor manufacture.
So, the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
The personage for knowing this technology all can carry out modifications and changes under without prejudice to spirit and scope of the invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete with institute under technological thought without departing from disclosed spirit such as
Into all equivalent modifications or change, should be covered by claim of the invention.
Claims (8)
1. a kind of method that substrate contact is drawn under SOI, it is characterised in that methods described includes step:
Step 1), the contact lead-out area of substrate is defined, using the etching technics of fairlead, opened under SOI from the upper surface of SOI
The contact lead-out area of substrate;
Step 2), contact lead-out area is carried out metal filled, and realize that the electricity of substrate under SOI is drawn by metal interconnection technique
Go out;
Wherein, substrate lead-out area contact with the component on SOI extraction is made a plate using same photoetching under SOI, substrate under SOI
Contact lead-out area etching technics and metal filling processes respectively with the etching technics and metal filled work of component contact hole
Skill uses same processing step.
2. the method that substrate contact is drawn under SOI according to claim 1, it is characterised in that:Substrate contact under the SOI
The etching technics of lead-out area and the etching technics of component contact hole are using same technique and while carry out, under the SOI
The metal filling processes of substrate contact lead-out area and the metal filling processes of component contact hole are using same technique and same
Shi Jinhang.
3. the method that substrate contact is drawn under SOI according to claim 1, it is characterised in that:The contact of the component
Extraction includes that the source contact of metal-oxide-semiconductor is drawn, drain contact is drawn, substrate zone contact is drawn and gate contact is drawn, two poles
Guan Yang areas contact extraction and cloudy area contacts and draws, and the collecting zone of triode contacts extraction, launch site contact extraction and base and connects
Touch and draw, active area and gate resistance contact are drawn, the upper bottom crown contact of mos capacitance is drawn, and the contact of optics is drawn,
One or more combinations that the contact of MEMS is drawn.
4. the method that substrate contact is drawn under SOI according to claim 3, it is characterised in that:By controlling etching technics
Etching selection ratio, the contact for making etching technics stop at component respectively draws substrate surface under surface and SOI.
5. the method that substrate contact is drawn under SOI according to claim 1, it is characterised in that:Step 1) include:
Step 1-1), in component is produced on SOI, the component includes that the contact of component is drawn;
Step 1-2), in SOI upper surfaces blanket dielectric layer;
Step 1-3), made a plate using same photoetching, substrate lead-out area under SOI is used and is drawn with the contact of the component on SOI
Go out while perform etching, by controlling the etching selection ratio of etching technics, etching technics is stopped at the contact of component respectively
Draw substrate surface under surface and SOI.
6. the method that substrate contact is drawn under SOI according to claim 1, it is characterised in that:Step 2) include:
Step 2-1), substrate contact lead-out area under the SOI and the component are contacted simultaneously using metal filling processes
Hole carries out metal filled;
Step 2-2), the electricity of substrate contact lead-out area and the component contact hole under SOI is realized by metal interconnection technique
Learn and draw.
7. the method that substrate contact is drawn under SOI according to claim 1, it is characterised in that:Step 1) in, the etching
Technique includes the one kind in ICP etching technics and RIE etching technics.
8. the method that substrate contact is drawn under SOI according to claim 1, it is characterised in that:Step 2) in, it is metal filled
The metal material for being used includes one or more combination or its alloy in copper, aluminium, silver, gold, platinum, titanium, tungsten.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201611196503.6A CN106783729B (en) | 2016-12-22 | 2016-12-22 | A kind of method that substrate contact is drawn under SOI |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201611196503.6A CN106783729B (en) | 2016-12-22 | 2016-12-22 | A kind of method that substrate contact is drawn under SOI |
Publications (2)
Publication Number | Publication Date |
---|---|
CN106783729A true CN106783729A (en) | 2017-05-31 |
CN106783729B CN106783729B (en) | 2018-08-31 |
Family
ID=58900329
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201611196503.6A Active CN106783729B (en) | 2016-12-22 | 2016-12-22 | A kind of method that substrate contact is drawn under SOI |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN106783729B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110021553A (en) * | 2018-01-09 | 2019-07-16 | 上海新微技术研发中心有限公司 | Through hole structure and method thereof |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008130829A (en) * | 2006-11-21 | 2008-06-05 | Rohm Co Ltd | Method of fabricating semiconductor device, and semiconductor device |
US20140084395A1 (en) * | 2012-09-25 | 2014-03-27 | Andrew Sparks | Mems microphone |
CN104282644A (en) * | 2013-07-02 | 2015-01-14 | 中芯国际集成电路制造(上海)有限公司 | Programmable silicon through hole structure and manufacturing method thereof |
CN104409421A (en) * | 2014-11-05 | 2015-03-11 | 武汉新芯集成电路制造有限公司 | Integration process of vertical type channel memory device and control device |
CN105552097A (en) * | 2016-02-29 | 2016-05-04 | 上海集成电路研发中心有限公司 | Global exposure pixel unit, capacitor structure and preparation method |
-
2016
- 2016-12-22 CN CN201611196503.6A patent/CN106783729B/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008130829A (en) * | 2006-11-21 | 2008-06-05 | Rohm Co Ltd | Method of fabricating semiconductor device, and semiconductor device |
US20140084395A1 (en) * | 2012-09-25 | 2014-03-27 | Andrew Sparks | Mems microphone |
CN104282644A (en) * | 2013-07-02 | 2015-01-14 | 中芯国际集成电路制造(上海)有限公司 | Programmable silicon through hole structure and manufacturing method thereof |
CN104409421A (en) * | 2014-11-05 | 2015-03-11 | 武汉新芯集成电路制造有限公司 | Integration process of vertical type channel memory device and control device |
CN105552097A (en) * | 2016-02-29 | 2016-05-04 | 上海集成电路研发中心有限公司 | Global exposure pixel unit, capacitor structure and preparation method |
Non-Patent Citations (1)
Title |
---|
SIDDHARTHA PANDA ET AL: "Etching High Aspect Ratio Silicon Trenches", 《JOURNAL OF THE ELECTROCHEMICAL SOCIETY》 * |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110021553A (en) * | 2018-01-09 | 2019-07-16 | 上海新微技术研发中心有限公司 | Through hole structure and method thereof |
Also Published As
Publication number | Publication date |
---|---|
CN106783729B (en) | 2018-08-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN103426732B (en) | The method of low-temperature wafer bonding and the structure formed by the method | |
CN105621348B (en) | A kind of MEMS inertial sensor part and its manufacture method | |
CN107316840A (en) | The 3DIC structures and method of mixing engagement semiconductor wafer | |
CN107527889B (en) | Semiconductor device packages | |
TWI267927B (en) | Method for wafer level package | |
CN105470225B (en) | Production method based on the three-dimensional capacitive coupling interconnection structure for wearing silicon capacitance | |
CN104979223B (en) | A kind of wafer bonding technique | |
CN108649036A (en) | A kind of array substrate and preparation method thereof | |
CN104915054B (en) | Array substrate and preparation method thereof and display device | |
CN107369664A (en) | The encapsulating structure and method for packing of semiconductor chip | |
CN106783729B (en) | A kind of method that substrate contact is drawn under SOI | |
CN104766806B (en) | The method of wafer three-dimensional integration | |
CN104332455A (en) | Structure of silicon through hole based semiconductor device on chip, and preparation method of the semiconductor device | |
CN104649218B (en) | A kind of wafer-level vacuum encapsulating method | |
CN105810593A (en) | Fan-out type packaging structure and packaging method therefor | |
CN103107129B (en) | Micropore metal filling structure and method | |
CN107226452B (en) | Coplanar bonding structure and preparation method thereof | |
CN102254821B (en) | Metal oxide semiconductor (MOS) capacitor based on silicon-on-insulator (SOI) material and method for making MOS capacitor | |
CN107546174A (en) | A kind of process of ic component | |
CN106338867A (en) | VCOM wiring structure, display panel and manufacturing method of VCOM wiring structure | |
CN203850291U (en) | TSV hole structure | |
CN203941899U (en) | A kind of semiconductor structure | |
CN104241201B (en) | A kind of method of integrated power device and control device | |
CN105742197A (en) | Bonding wafer structure and preparation method therefor | |
CN207165551U (en) | The encapsulating structure of semiconductor chip |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right |
Effective date of registration: 20221026 Address after: 201808 Room 930, 9/F, Building 2, No. 1399, Shengzhu Road, Juyuan New District, Jiading District, Shanghai Patentee after: Shanghai Industrial UTechnology Research Institute Address before: 201800 Room 1048, Building 1, No. 2222, Huancheng Road, Juyuan New District, Jiading District, Shanghai Patentee before: SHANGHAI INTERNATIONAL MICRO-TECH AFFILIATION CENTER |
|
TR01 | Transfer of patent right |