CN105552097A - Global exposure pixel unit, capacitor structure and preparation method - Google Patents
Global exposure pixel unit, capacitor structure and preparation method Download PDFInfo
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- CN105552097A CN105552097A CN201610109828.XA CN201610109828A CN105552097A CN 105552097 A CN105552097 A CN 105552097A CN 201610109828 A CN201610109828 A CN 201610109828A CN 105552097 A CN105552097 A CN 105552097A
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- 239000003990 capacitor Substances 0.000 title claims abstract description 63
- 238000002360 preparation method Methods 0.000 title claims abstract description 11
- 238000000605 extraction Methods 0.000 claims description 53
- 229910052751 metal Inorganic materials 0.000 claims description 48
- 239000002184 metal Substances 0.000 claims description 48
- 229910021332 silicide Inorganic materials 0.000 claims description 37
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 37
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 13
- 230000000903 blocking effect Effects 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 5
- 238000002955 isolation Methods 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
Abstract
The invention provides a global exposure pixel unit, a capacitor structure and a preparation method. Through forming a first capacitor structure, a second capacitor structure and a third capacitor structure at a longitudinal direction, and connecting the three capacitor structures together in a parallel connection manner, on the basis of not increasing the area of the capacitor structure of the global exposure pixel unit, the storage capacitance value of the capacitor structure is increased, and the readout noise is reduced; and meanwhile, the area of a photodiode photosensitive area of the whole global exposure pixel unit is not affected, and the performance of a device is improved.
Description
Technical field
The present invention relates to technical field of semiconductors, be specifically related to a kind of overall exposing pixels unit, capacitance structure and preparation method thereof.
Background technology
Imageing sensor refers to device light signal being converted to the signal of telecommunication, and extensive commercial image sensor chip comprises charge coupled device (CCD) and the large class of complementary metal oxide semiconductors (CMOS) (CMOS) image sensor chip two usually.
Cmos image sensor compares with traditional ccd sensor the low-power consumption had, low cost and with the feature such as CMOS technology is compatible, therefore obtain applying more and more widely.Present cmos image sensor not only for consumer electronics field, such as miniature digital camera (DSC), mobile phone camera, in video camera and number list anti-(DSLR), and at automotive electronics, monitoring, the field such as biotechnology and medical science have also been obtained applies widely.
The pixel cell of cmos image sensor is that imageing sensor realizes photosensitive core devices.The most frequently used pixel cell is the active pixel structure comprising a photodiode and multiple transistor, in these devices, photodiode is photosensitive unit, realize the collection to light and opto-electronic conversion, other MOS transistor is control unit, main realization choosing photodiode, reset, the control that signal amplifies and reads.
Usually two kinds of shutter control modes are had: mechanical shutter and electronic shutter in digital camera.Mechanical shutter controls the time for exposure by the folding being arranged on the mechanical parts before cmos image sensor; Electronic shutter changes the time of integration by the sequencing control of pixel cell, thus reaches the object controlling the time for exposure.Because mechanical shutter needs mechanical parts, the area of digital camera can be taken, therefore not be suitable for portable digital camera, and for video surveillance applications, owing to normally carrying out video acquisition, therefore generally adopt electronic shutter to control the time for exposure.Electronic shutter is divided into again two kinds: roller shutter type and overall exposure type.The time for exposure of roller shutter type electronic shutter often between row is inconsistent, is easily cause motion blur phenomenon at shooting high-speed object; Every a line of overall situation exposure type electronic shutter exposes at one time, then charge signal is stored in the memory node of pixel cell simultaneously, finally the signal of memory node is exported line by line, because all row expose at one time, so can not motion blur phenomenon be caused.
Along with cmos image sensor is applied more and more widely in industrial, vehicle-mounted, road monitoring and high speed camera, the demand for the imageing sensor that can catch high-speed moving object image improves further.In order to monitor high-speed object, cmos image sensor needs the pixel cell using overall situation exposure, and the reading noise of overall pixel cell in overall pixel, directly can be affected for the capacitance of the storage capacitance of stored charge signal, the reading noise of the larger then pixel cell of capacitance of storage capacitance is less, its performance is more excellent, be illustrated in figure 1 the overall exposing pixels unit of conventional mos capacitance as storage capacitance, comprise: silicon substrate 100, photodiode area 101, MOS storage capacitor construction region 102, the contact hole 103 in capacitance structure region 102, metal M 1 in interconnection layer and metal M 2, and inter-level dielectric 104, be illustrated in figure 2 the enlarged drawing of MOS storage capacitance in Fig. 1, the MOS storage capacitance in CMOS technology comprises MOS conventional capacitance and MOS transfiguration electric capacity, and mos capacitance can be divided into again N-type and P type two kinds of structures according to doping type.For MOS transfiguration electric capacity, it is a two terminal device formed in P-type silicon substrate 100, the top crown 203 of MOS storage capacitance is N-type polycrystalline, and the bottom crown 201 of MOS storage capacitance is N trap doped region, is capacitor dielectric layer 202 between upper bottom crown 203,201; Also comprise the side wall and source-drain area 204 that are positioned at top crown 203 both sides, the contact hole 103 on top crown 203, the contact hole 103 on source-drain area 204, inter-level dielectric 104, top crown electrode 205 and bottom crown electrode 206 between contact hole 103.The size of its capacitance depends on the area in the district that to overlap between polycrystalline top crown and N trap bottom crown, therefore to increase capacitance just to need to increase electric capacity area on a silicon substrate, silicon substrate is arranged in due to mos capacitance with for photosensitive photodiode, if increase storage capacitance area, need the photosensitive area reducing photodiode, the sensitivity of pixel cell will be reduced, therefore in order to ensure the photosensitive area of photodiode area in pixel cell, the area of storage capacitance is restricted.If so can increase the capacitance of storage capacitance under the condition not affecting photodiode photosensitive area, then overall pixel cell can reduce reading noise when not sacrificing sensitivity, improves performance.
Summary of the invention
In order to overcome above problem, the invention provides a kind of capacitance structure of overall exposing pixels unit, in this capacitance structure, there is multiple electric capacity in the vertical, thus do not increase overall exposing pixels unit capacitance structure area basis on, add the storage capacitance value of capacitance structure.
In order to achieve the above object, the invention provides a kind of capacitance structure of overall exposing pixels unit, comprise: silicon substrate, be positioned at the bottom crown on silicon substrate, be positioned on bottom crown and have the first capacitor dielectric and top crown successively, the bottom crown part surface of top crown both sides is provided with source-drain area, described top crown is provided with inter-level dielectric, top crown is connected with top crown extraction pole by the first contact hole, source-drain area is connected with bottom crown extraction pole by the second contact hole, also comprises:
Described top crown surface is provided with the second capacitor dielectric;
Some 3rd contact trench are respectively arranged with between described second contact hole and on described second capacitor dielectric of described first contact hole both sides; Described bottom crown extraction pole connects described second contact hole and described 3rd contact trench simultaneously; Described 3rd contact trench is all connected between described bottom crown extraction pole and described second capacitor dielectric;
Wherein, described top crown, between described first capacitor dielectric and described bottom crown, form the first capacitance structure, described first capacitance structure is connected with described top crown extraction pole by described first contact hole, is connected with described bottom crown extraction pole by described second contact hole; The bottom of described 3rd contact trench, the second capacitance structure formed between described second capacitor dielectric and the upper surface of described top crown, described second capacitance structure is connected with described top crown extraction pole by described first contact hole, is connected with described bottom crown extraction pole by described 3rd contact trench; Described 3rd contact trench sidewall, the 3rd capacitance structure formed between the described inter-level dielectric of part and the sidewall of described first contact hole, described 3rd capacitance structure is connected with described top crown extraction pole by described first contact hole, is connected with described bottom crown extraction pole by described 3rd contact trench; Further, the width of described 3rd contact trench is greater than the width of described first contact hole, and is greater than the width of described second contact hole; In described 3rd capacitance structure, the width between the sidewall of described first contact hole and the sidewall of described 3rd contact trench is less than the width between the sidewall of described second contact hole sidewall and adjacent described 3rd contact trench.
Preferably, described second contact hole is two, is arranged on described source-drain area respectively, and described 3rd contact trench is two, is separately positioned on described first contact hole both sides.
Preferably, described inter-level dielectric is for the metal interconnected inter-level dielectric in rear road, and the material of described second capacitor dielectric is identical with the material of blocking layer of metal silicide.
Preferably, described source-drain area is formed with metal silicide, the bottom of described second contact hole contacts with described metal silicide; The region of described top crown and described first contact holes contact is formed with metal silicide, contacts bottom described first contact hole with described metal silicide.
Preferably, the material of described inter-level dielectric is silica, and the material of described second capacitor dielectric is silicon nitride, silicon oxynitride.
Preferably, the doping type of described bottom crown is N-type, and the doping type of described source and drain is N-type, and the material of described top crown is polysilicon.
In order to achieve the above object, present invention also offers a kind of preparation method of capacitance structure of above-mentioned overall exposing pixels unit, it comprises:
Step 01: form described bottom crown, described first capacitor dielectric, described top crown and described source-drain area on a silicon substrate;
Step 02: form described second capacitor dielectric on described first inter-level dielectric He on described top crown;
Step 03: form described inter-level dielectric on described second capacitor dielectric;
Step 04: form described first contact hole, described second contact hole and described 3rd contact trench in described inter-level dielectric;
Step 05: fill metal in described first contact hole, described second contact hole and described 3rd contact trench;
Step 06: prepare described bottom crown extraction pole and described top crown extraction pole; Wherein, described top crown extraction pole contacts with described first contact hole top; Described bottom crown extraction pole connects described second contact hole top and described 3rd contact trench top simultaneously.
Preferably, described second capacitor dielectric is blocking layer of metal silicide; Also comprise between described step 02 and described step 03: in described blocking layer of metal silicide, etch metal silicide pattern openings; Then, the top crown part exposed at described opening and described source-drain area part form metal silicide; In described step 04, described first contact hole of formation is connected with the described metal silicide of described source-drain area part with the described metal silicide of described top crown part respectively with bottom described second contact hole.
Preferably, in described step 04, photoetching and dry etch process is adopted to form described first contact hole, described second contact hole and described 3rd contact trench.
In order to achieve the above object, present invention also offers a kind of overall exposing pixels unit, comprise photodiode photosensitive region, capacitor regions and interconnection layer, described capacitor regions has described capacitance structure.
The capacitance structure of overall exposing pixels unit of the present invention, by forming the first capacitance structure, the second capacitance structure and the 3rd capacitance structure in the vertical, mode in parallel is adopted to link together these three capacitance structures, thus do not increase overall exposing pixels unit capacitance structure area basis on, add the storage capacitance value of capacitance structure, reduce reading noise, simultaneously, do not affect the area of the photodiode photosensitive region of whole overall exposing pixels unit, improve the performance of device.
Accompanying drawing explanation
Fig. 1 is the conventional structural representation with the overall exposing pixels unit of storage capacitance
Fig. 2 is the enlarged diagram of storage capacitance in Fig. 1
Fig. 3 is the schematic diagram of the capacitance structure of the overall exposing pixels unit of a preferred embodiment of the present invention
Fig. 4 is the schematic flow sheet of the preparation method of the capacitance structure of the overall exposing pixels unit of a preferred embodiment of the present invention
Fig. 5-Figure 12 is each preparation process schematic diagram of the preparation method of the capacitance structure of the overall exposing pixels unit of embodiments of the invention one
Embodiment
For making content of the present invention clearly understandable, below in conjunction with Figure of description, content of the present invention is described further.Certain the present invention is not limited to this specific embodiment, and the general replacement known by those skilled in the art is also encompassed in protection scope of the present invention.
In the present invention, the capacitance structure of overall situation exposing pixels unit, comprise: silicon substrate, be positioned at the bottom crown on silicon substrate, be positioned on bottom crown and have the first capacitor dielectric and top crown successively, the bottom crown part surface of top crown both sides is provided with source-drain area, described top crown is provided with inter-level dielectric, top crown is connected with top crown extraction pole by the first contact hole, source-drain area is connected with bottom crown extraction pole by the second contact hole, described top crown surface is provided with the second capacitor dielectric; Some 3rd contact trench are respectively arranged with between described second contact hole and on described second capacitor dielectric of described first contact hole both sides; Described bottom crown extraction pole connects described second contact hole and described 3rd contact trench simultaneously; Described 3rd contact trench is all connected between described bottom crown extraction pole and described second capacitor dielectric;
Wherein, described top crown, between described first capacitor dielectric and described bottom crown, form the first capacitance structure, described first capacitance structure is connected with described top crown extraction pole by described first contact hole, is connected with described bottom crown extraction pole by described second contact hole; The bottom of described 3rd contact trench, the second capacitance structure formed between described second capacitor dielectric and the upper surface of described top crown, described second capacitance structure is connected with described top crown extraction pole by described first contact hole, is connected with described bottom crown extraction pole by described 3rd contact trench; Described 3rd contact trench sidewall, the 3rd capacitance structure formed between the described inter-level dielectric of part and the sidewall of described first contact hole, described 3rd capacitance structure is connected with described top crown extraction pole by described first contact hole, is connected with described bottom crown extraction pole by described 3rd contact trench.
Below in conjunction with accompanying drawing 3-Figure 12 and specific embodiment, the present invention is described in further detail.It should be noted that, accompanying drawing all adopt simplify very much form, use non-ratio accurately, and only in order to object that is convenient, that clearly reach aid illustration the present embodiment.
Refer to Fig. 3, in the present embodiment, silicon substrate 00 is formed with N-type bottom crown 01, it is gate oxide that N-type bottom crown 01 is formed the first capacitor dielectric 02, first capacitor dielectric 02; First capacitor dielectric 02 is formed with polysilicon top crown 03, and pole plate 03 both sides are formed with isolation side walls on the polysilicon; N-type bottom crown 01 surface of pole plate 03 both sides is formed with source-drain area 04 on the polysilicon; Source-drain area 04 is formed metal silicide 06; Pole plate 03 upper surface and isolation side walls sidewall are formed with the second capacitor dielectric 05 on the polysilicon; Position corresponding with the first contact hole 08 in the second capacitor dielectric 05 is formed with metal silicide 06; Source-drain area 04 is formed the second contact hole 09, the second capacitor dielectric 05 on the polysilicon on pole plate 03 is formed with the 3rd contact trench 10, metal silicide 06 on the polysilicon on pole plate 03 is formed with the first contact hole 08, be formed with inter-level dielectric 07 between first contact hole 08, second contact hole 09 and the 3rd contact trench 10, inter-level dielectric 07 for by the first contact hole 08, second contact hole 09 and the 3rd contact trench 10 isolated.Top crown extraction pole 11 is formed at the first contact hole 08 top, be formed with public bottom crown extraction pole 12 at the second contact hole 09 top and the 3rd contact trench 10 top, that is to say that bottom crown extraction pole 12 connects the second contact hole 09 and the 3rd contact trench 10 simultaneously.Here, preferably, inter-level dielectric 07 is for the metal interconnected inter-level dielectric in rear road, and the material of inter-level dielectric 07 can be silica; The material of the second capacitor dielectric 05 is identical with the material of blocking layer of metal silicide, can be that silicon nitride, silicon oxynitride etc. have the dielectric material compared with high selectivity to inter-level dielectric 07, the thickness of deposition at 50 ~ 500 dusts, masking layer when adopting the material of blocking layer of metal silicide can be formed as metal silicide in preparation technology and the second capacitor dielectric of the second capacitance structure.
Form two the first capacitance structures between polysilicon top crown 03, first capacitor dielectric 02 and bottom crown 01, the first capacitance structure is connected with top crown extraction pole 11 by the first contact hole 08, is connected with bottom crown extraction pole 12 by the second contact hole 09;
The bottom of the 3rd contact trench 10, two the second capacitance structures formed between the second capacitor dielectric 05 and the upper surface of polysilicon top crown 03, two the second capacitance structures lay respectively at bottom the 3rd contact trench 10 of the first contact hole 08 both sides; Second capacitance structure is connected with top crown extraction pole 11 by the first contact hole 08, is connected with bottom crown extraction pole 12 by the 3rd contact trench 10;
3rd contact trench 10 sidewall, two the 3rd capacitance structures formed between part inter-level dielectric 07 and the sidewall of the first contact hole 08, two the 3rd capacitance structures lay respectively at the first contact hole 08 both sides; 3rd capacitance structure is connected with top crown extraction pole 11 by the first contact hole 08, is connected with bottom crown extraction pole 12 by the 3rd contact trench 10.The width of the 3rd contact trench 10 is greater than the width of the first contact hole 08, and is greater than the width of the second contact hole 09; In 3rd capacitance structure, the width between the sidewall of the first contact hole 08 and the sidewall of the 3rd contact trench 10 is less than the width between the sidewall of the second contact hole 09 sidewall and the 3rd adjacent contact trench 10.
Refer to Fig. 4, in the present embodiment, the preparation method of the capacitance structure of above-mentioned overall exposing pixels unit comprises:
Step 01: form bottom crown, the first capacitor dielectric, top crown and source-drain area on a silicon substrate;
Concrete, refer to Fig. 5, silicon substrate 00 is formed N-type bottom crown 01, first capacitor dielectric 02, polysilicon top crown 03 and N shape source-drain area 04, and these can adopt common process to prepare, and repeat no more.
Step 02: form the second capacitor dielectric on the first inter-level dielectric He on top crown;
Concrete, refer to Fig. 6, can be, but not limited to adopt chemical vapour deposition technique to deposit the second capacitor dielectric 05.Here, the second capacitor dielectric 05 is blocking layer of metal silicide.
Also comprise between step 02 and step 03: first, refer to Fig. 7, in blocking layer of metal silicide 05, go out metal silicide pattern openings by dry method or wet etching; Then, refer to Fig. 8, top crown 03 part adopting conventional metal silicide formation process to expose at opening and source-drain area 04 part form metal silicide 06; Polysilicon top crown 03 part exposed is the middle section of polysilicon top crown 03.
Step 03: form inter-level dielectric on the second capacitor dielectric;
Concrete, refer to Fig. 9, can be, but not limited to adopt vapour deposition process to carry out interlayer dielectric 07, inter-level dielectric 07 as the isolation between the 3rd capacitance structure, and metal interconnected between isolation.
Step 04: form the first contact hole, the second contact hole and the 3rd contact trench in inter-level dielectric;
Concrete, refer to Figure 10, the first contact hole 08 ', the second contact hole 09 ' and the 3rd contact trench 10 ' can be etched through photoetching and dry etch process; In this step 04, because inter-level dielectric 07 has high etching selection ratio relative to blocking layer of metal silicide 05, final etching stopping is on blocking layer of metal silicide 05, and the first contact hole 08 ' of formation is connected with the metal silicide 06 of source-drain area 04 part with the metal silicide 06 of top crown 03 part respectively with the second contact hole 09 ' bottom.Wherein, inter-level dielectric 07 part between first contact hole 08 ' and the 3rd contact trench 10 ' is as the capacitor dielectric of the 3rd capacitance structure, the spacing of the first contact hole 08 ' and the 3rd contact trench 10 ' uses minimum design rule when layout design, make the thickness of remaining inter-level dielectric 07 part the thinnest, namely capacitance is maximum.
Step 05: fill metal in the first contact hole, the second contact hole and the 3rd contact trench;
Concrete, refer to Figure 11, the metal filled is tungsten, electroplating technology or gas-phase deposition can be adopted to fill metal, then CMP (Chemical Mechanical Polishing) process is adopted to remove the tungsten being positioned at inter-level dielectric 07 surface, retain the tungsten being positioned at the first contact hole, the second contact hole and the 3rd contact trench, thus form the first contact hole 08, second contact hole 09 and the 3rd contact trench 10 that are filled with tungsten.
Step 06: refer to Figure 12, prepares bottom crown extraction pole 12 and top crown extraction pole 11; Wherein, top crown extraction pole 11 contacts with the first contact hole 08 top; Bottom crown extraction pole 12 connects the second contact hole 09 top and the 3rd contact trench 10 top simultaneously.Here, adopt CMOS common process to prepare bottom crown extraction pole 12 and top crown extraction pole 11, repeat no more here.
Present invention also offers a kind of overall exposing pixels unit, it comprises: photodiode photosensitive region, capacitor regions and interconnection layer, the capacitance structure that capacitor regions is above-mentioned.
Although the present invention discloses as above with preferred embodiment; right described embodiment is citing for convenience of explanation only; and be not used to limit the present invention; those skilled in the art can do some changes and retouching without departing from the spirit and scope of the present invention, and the protection range that the present invention advocates should be as the criterion with described in claims.
Claims (10)
1. the capacitance structure of an overall exposing pixels unit, comprise: silicon substrate, be positioned at the bottom crown on silicon substrate, bottom crown there are the first capacitor dielectric and top crown successively, the bottom crown part surface of top crown both sides are provided with source-drain area, described top crown is provided with inter-level dielectric, top crown connects top crown extraction pole by the first contact hole, source-drain area connects bottom crown extraction pole by the second contact hole, it is characterized in that
Described top crown surface is provided with the second capacitor dielectric;
Some 3rd contact trench are respectively arranged with between described second contact hole and on described second capacitor dielectric of described first contact hole both sides; Described bottom crown extraction pole connects described second contact hole and described 3rd contact trench simultaneously; Described 3rd contact trench is all connected between described bottom crown extraction pole and described second capacitor dielectric;
Wherein, described top crown, between described first capacitor dielectric and described bottom crown, form the first capacitance structure, described first capacitance structure is connected with described top crown extraction pole by described first contact hole, is connected with described bottom crown extraction pole by described second contact hole; The bottom of described 3rd contact trench, between described second capacitor dielectric and the upper surface of described top crown, form the second capacitance structure, described second capacitance structure is connected with described top crown extraction pole by described first contact hole, is connected with described bottom crown extraction pole by described 3rd contact trench; Described 3rd contact trench sidewall, between the described inter-level dielectric of part and the sidewall of described first contact hole form the 3rd capacitance structure, described 3rd capacitance structure is connected with described top crown extraction pole by described first contact hole, is connected with described bottom crown extraction pole by described 3rd contact trench;
The width of described 3rd contact trench is greater than the width of described first contact hole, and is greater than the width of described second contact hole; In described 3rd capacitance structure, the width between the sidewall of described first contact hole and the sidewall of described 3rd contact trench is less than the width between the sidewall of described second contact hole sidewall and adjacent described 3rd contact trench.
2. the capacitance structure of overall exposing pixels unit according to claim 1, is characterized in that, described second contact hole is two, is arranged on described source-drain area respectively, and described 3rd contact trench is two, is separately positioned on described first contact hole both sides.
3. the capacitance structure of overall exposing pixels unit according to claim 1, is characterized in that, described source-drain area is formed with metal silicide, and the bottom of described second contact hole contacts with described metal silicide; The region of described top crown and described first contact holes contact is formed with metal silicide, contacts bottom described first contact hole with described metal silicide.
4. the capacitance structure of the overall exposing pixels unit according to claim 1-3 any one, it is characterized in that, described inter-level dielectric is for the metal interconnected inter-level dielectric in rear road, and the material of described second capacitor dielectric is identical with the material of blocking layer of metal silicide.
5. the capacitance structure of overall exposing pixels unit according to claim 4, is characterized in that, the material of described inter-level dielectric is silica, and the material of described second capacitor dielectric is silicon nitride, silicon oxynitride.
6. the capacitance structure of the overall exposing pixels unit according to claim 1-3 any one, is characterized in that, the doping type of described bottom crown is N-type, and the doping type of described source and drain is N-type, and the material of described top crown is polysilicon.
7. a preparation method for the capacitance structure of overall exposing pixels unit according to claim 1, is characterized in that, comprising:
Step 01: form described bottom crown, described first capacitor dielectric, described top crown and described source-drain area on a silicon substrate;
Step 02: form described second capacitor dielectric on described first inter-level dielectric He on described top crown;
Step 03: form described inter-level dielectric on described second capacitor dielectric;
Step 04: form described first contact hole, described second contact hole and described 3rd contact trench in described inter-level dielectric;
Step 05: fill metal in described first contact hole, described second contact hole and described 3rd contact trench;
Step 06: prepare described bottom crown extraction pole and described top crown extraction pole; Wherein, described top crown extraction pole contacts with described first contact hole top; Described bottom crown extraction pole connects described second contact hole top and described 3rd contact trench top simultaneously.
8. method according to claim 7, is characterized in that, described second capacitor dielectric is blocking layer of metal silicide; Also comprise between described step 02 and described step 03: in described blocking layer of metal silicide, etch metal silicide pattern openings; Then, the top crown part exposed at described opening and described source-drain area part form metal silicide; In described step 04, described first contact hole of formation is connected with the described metal silicide of described source-drain area part with the described metal silicide of described top crown part respectively with bottom described second contact hole.
9. method according to claim 7, is characterized in that, in described step 04, adopts photoetching and dry etch process to form described first contact hole, described second contact hole and described 3rd contact trench.
10. an overall exposing pixels unit, comprises photodiode photosensitive region, capacitor regions and interconnection layer, it is characterized in that, described capacitor regions has capacitance structure according to claim 1.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106783729A (en) * | 2016-12-22 | 2017-05-31 | 上海新微科技服务有限公司 | A kind of method that substrate contact is drawn under SOI |
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| CN106783729A (en) * | 2016-12-22 | 2017-05-31 | 上海新微科技服务有限公司 | A kind of method that substrate contact is drawn under SOI |
| CN106783729B (en) * | 2016-12-22 | 2018-08-31 | 上海新微科技服务有限公司 | A kind of method that substrate contact is drawn under SOI |
| EP3780105A1 (en) * | 2019-08-13 | 2021-02-17 | United Microelectronics Corp. | Semiconductor device and method of fabricating the same |
| CN112397531A (en) * | 2019-08-13 | 2021-02-23 | 联华电子股份有限公司 | Semiconductor device and method for manufacturing the same |
| US10971397B2 (en) | 2019-08-13 | 2021-04-06 | United Microelectronics Corp. | Semiconductor device and method of fabricating the same |
| US11631613B2 (en) | 2019-08-13 | 2023-04-18 | United Microelectronics Corp. | Semiconductor device |
Also Published As
| Publication number | Publication date |
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| CN105552097B (en) | 2018-11-09 |
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