CN106783592A - The frequency reconfigurable holographic antenna preparation method of AlAs/Ge/AlAs structures - Google Patents
The frequency reconfigurable holographic antenna preparation method of AlAs/Ge/AlAs structures Download PDFInfo
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- CN106783592A CN106783592A CN201611183888.2A CN201611183888A CN106783592A CN 106783592 A CN106783592 A CN 106783592A CN 201611183888 A CN201611183888 A CN 201611183888A CN 106783592 A CN106783592 A CN 106783592A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 71
- 239000007787 solid Substances 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 39
- 239000010410 layer Substances 0.000 claims description 88
- 239000000463 material Substances 0.000 claims description 42
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 32
- 239000011241 protective layer Substances 0.000 claims description 26
- 238000002955 isolation Methods 0.000 claims description 19
- 238000001259 photo etching Methods 0.000 claims description 18
- 239000012535 impurity Substances 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 229910052681 coesite Inorganic materials 0.000 claims description 9
- 229910052906 cristobalite Inorganic materials 0.000 claims description 9
- 229910052682 stishovite Inorganic materials 0.000 claims description 9
- 229910052905 tridymite Inorganic materials 0.000 claims description 9
- 238000001039 wet etching Methods 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- 230000005540 biological transmission Effects 0.000 claims description 3
- 239000007769 metal material Substances 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims 1
- 230000009191 jumping Effects 0.000 abstract description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 32
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 31
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/36—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
- H01Q1/38—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith formed by a conductive layer on an insulating support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q23/00—Antennas with active circuits or circuit elements integrated within them or attached to them
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q7/00—Loop antennas with a substantially uniform current distribution around the loop and having a directional radiation pattern in a plane perpendicular to the plane of the loop
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- General Physics & Mathematics (AREA)
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- Ceramic Engineering (AREA)
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Abstract
The present invention relates to a kind of frequency reconfigurable holographic antenna preparation method of AlAs/Ge/AlAs structures, the holographic antenna includes GeOI substrates (1), first antenna arm (2), the second antenna arm (3), coaxial feeder (4), direct current biasing line and holographic annulus (14)；Wherein, the preparation method includes：The solid plasma pin diodes of AlAs/Ge/AlAs structures are made on the GeOI substrates；Joined end to end successively by the solid plasma pin diodes of multiple AlAs/Ge/AlAs structures and form plasma pin diode strings；The first antenna arm and the second antenna arm are made by multiple plasma pin diodes strings；The direct current biasing line is made on the GeOI substrates；Coaxial feeder is made on the first antenna arm and the second antenna arm to form the restructural holographic antenna；The present invention prepare holographic antenna small volume, simple structure, it is easy to process, without complicated feed structure, frequency can rapid jumping, and antenna close when will be in the stealthy state of electromagnetic wave, it is easy to organize battle array, can be used as the basic component units of phased array antenna.
Description
Technical field
The invention belongs to technical field of semiconductors, and in particular to a kind of frequency reconfigurable of AlAs/Ge/AlAs structures is holographic
Antenna preparation method.
Background technology
The concept of reconfigurable antenna is set forth in the sixties in 20th century.Restructural refers in multi-antenna array between each array element
Relation can be according to actual conditions flexibility and changeability, it is and revocable.It is mainly by adjusting state variable device, realizes
The restructural of antenna performance.Reconfigurable antenna by function can be divided into frequency reconfigurable antenna (including realize broadband and realize it is many
Frequency band), directional diagram reconstructable aerial, polarization reconfigurable antenna and many electromagnetic parameter reconfigurable antennas.By changing restructural day
The structure of line can make one or more the realization reconstruct in many kinds of parameters such as frequency, lobe pattern, the polarization mode of antenna, because of it
Have the advantages that small volume, function are more, be easily achieved diversity application, have become study hotspot.
At present, domestic and international application is body silicon materials in the material that the pin diodes of plasma reconfigurable antenna are used, this
Material has that intrinsic region carrier mobility is relatively low, influence pin diodes intrinsic region carrier concentration, and then influences it to consolidate
State plasma density；And the P areas of the structure and N areas are formed using injection technology mostly, the method requirement implantation dosage and
Energy is larger, high to equipment requirement, and incompatible with existing process；And diffusion technique is used, though junction depth is deeper, P areas simultaneously
Area with N areas is larger, and integrated level is low, and doping concentration is uneven, influence pin diodes electric property, cause solid-state etc. from
Daughter concentration and the poor controllability of distribution.
Which kind of therefore, material and technique is selected to make a kind of plasma pin diodes to be applied to solid plasma day
Line just becomes particularly important.
The content of the invention
In order to solve the above-mentioned problems in the prior art, the invention provides a kind of frequency of AlAs/Ge/AlAs structures
Rate restructural holographic antenna preparation method.The technical problem to be solved in the present invention is achieved through the following technical solutions：
The embodiment provides a kind of frequency reconfigurable holographic antenna preparation method of AlAs/Ge/AlAs structures,
The holographic antenna includes GeOI substrates (1), first antenna arm (2), the second antenna arm (3), coaxial feeder (4), direct current biasing
Line and holographic annulus (14)；Wherein, the preparation method includes：
The solid plasma pin diodes of AlAs/Ge/AlAs structures are made on the GeOI substrates；The poles of the pin bis-
The P areas of pipe use AlAs materials, i areas to use Ge materials and N areas to use AlAs materials to form the heterogeneous poles of Ge bases plasma pin bis-
Pipe；
Joined end to end successively by the solid plasma pin diodes of multiple AlAs/Ge/AlAs structures and form plasma
Pin diode strings；
The first antenna arm and the second antenna arm are made by multiple plasma pin diodes strings；
The direct current biasing line is made on the GeOI substrates；Made on the first antenna arm and the second antenna arm
Coaxial feeder is forming the restructural holographic antenna.
In one embodiment of the invention, made on the GeOI substrates solid-states etc. of AlAs/Ge/AlAs structures from
Sub- pin diodes, including：
A () chooses GeOI substrates, and set isolated area in the GeOI substrates；
B () etches the GeOI substrates and forms p-type groove and N-type groove；
C () is in the p-type groove and the N-type groove and whole substrate surface deposits AlAs materials；Planarizing process
After GeOI substrates, AlAs layers is formed on GeOI substrates；
D AlAs layers of () photoetching, p type impurity and N-type are injected separately into the p-type groove and the N-type groove position
Impurity with formed the p-type active area and the N-type active area and simultaneously formed p-type contact zone and N-type contact zone；
E () removes photoresist；The AlAs materials beyond p-type contact zone and N-type contact zone are removed using wet etching；And
F () forms lead in the p-type active area and the N-type surfaces of active regions, to complete the AlAs/Ge/AlAs
The preparation of the solid plasma pin diodes of structure.
Wherein, step (a) includes：
(a1) the first protective layer is formed in the GeOI substrate surfaces；
(a2) the first isolated area figure is formed on first protective layer using photoetching process；
(a3) dry etch process is utilized, in first protection of the specified location etching of the first isolated area figure
Layer and the GeOI substrates to form isolation channel, and the isolation channel depth more than or equal to the top layer Ge's of the GeOI substrates
Thickness；
(a4) isolation channel is filled to form the isolated area.
Further, first protective layer includes SiO2 layers and first SiN layer；Correspondingly, step (a1) includes：
(a11) generate SiO2 materials to form the first SiO2 layers in the GeOI substrate surfaces；
(a12) generate SiN materials to form the first SiN layer in a SiO2 layer surfaces.
In one embodiment of the invention, step (b) includes：
(b1) the second protective layer is formed in the GeOI substrate surfaces；
(b2) the second isolated area figure is formed on second protective layer using photoetching process；
(b3) the specified location etching described second using dry etch process in the second isolated area figure is protected
Layer and top layer Ge the layer of the GeOI substrates are with described top layer Ge layer interior formation the p-type groove and the N-type groove.
Wherein, second protective layer includes the 2nd SiO2 layers and the second SiN layer；Correspondingly, step (b1) includes：
(b11) generate SiO2 materials to form the 2nd SiO2 layers in the GeOI substrate surfaces；
(b12) generate SiN materials to form the second SiN layer in the 2nd SiO2 layer surfaces.
In one embodiment of the invention, step (f) includes：
(f1) the p-type contact zone and N-type contact zone surface specific bit are etched away using anisotropic etch process
The SiO2 materials put are forming the fairlead；
(f2) to depositing metal material in the fairlead, treatment is passivated to whole backing material and photoetching PAD with
Form the solid plasma pin diodes of the AlAs/Ge/AlAs structures.
In one embodiment of the invention, the holographic annulus (14) is by eight sections of isometric AlAs/Ge/AlAs
The solid plasma pin diode string arrangement form octagon structures of structure, the radius of the circumscribed circle of the octagon is
3/4ths of the electromagnetic wavelength of the antenna reception or transmission；Wherein, the length of side of the octagon with described first day
Line arm (2) is identical with the second antenna arm (3) length sum.
In one embodiment of the invention, the first antenna arm (2) and second antenna arm (3) are along described coaxial
The distribution of feeder line (4) axial symmetry and the solid plasma pin diode strings of the AlAs/Ge/AlAs structures including equal number.
In one embodiment of the invention, also including be made in the GeOI substrates (1) direct current biasing line (5,6,7,
8、9、10、11、12)；Direct current biasing line (5,6,7,8,9,10, the 11,12) intermittent is electrically connected to the poles of the SPiN bis-
Pipe string (w1, w2, w3, w4, w5, w6) two ends.
A kind of advantage of frequency reconfigurable holographic antenna of AlAs/Ge/AlAs structures that the present invention is provided is：
1st, small volume, section are low, simple structure, easy to process；
2nd, using coaxial cable as feed, without complicated feed structure；
3rd, need to be only turned on or off by controlling it as the basic component units of antenna using SPiN diodes, you can
Realize the restructural of frequency；
4th, all constituents are in semiconductor chip side, it is easy to plate-making processing.
Brief description of the drawings
Fig. 1 is a kind of system of the fundamental frequency restructural holographic antenna of AlAs/Ge/AlAs structures provided in an embodiment of the present invention
Standby flow chart；
Fig. 2 is a kind of knot of the fundamental frequency restructural holographic antenna of AlAs/Ge/AlAs structures provided in an embodiment of the present invention
Structure schematic diagram；
Fig. 3 is a kind of system of the solid plasma pin diodes of AlAs/Ge/AlAs structures provided in an embodiment of the present invention
Standby flow chart；
Fig. 4 a- Fig. 4 r are a kind of solid plasma pin diodes of AlAs/Ge/AlAs structures of the embodiment of the present invention
Preparation method schematic diagram；
Fig. 5 is a kind of knot of the solid plasma pin diodes of AlAs/Ge/AlAs structures provided in an embodiment of the present invention
Structure schematic diagram；And
Fig. 6 is a kind of solid plasma pin diode strings of AlAs/Ge/AlAs structures provided in an embodiment of the present invention
Structural representation.
Specific embodiment
Further detailed description is done to the present invention with reference to specific embodiment, but embodiments of the present invention are not limited to
This.
Embodiment one
Fig. 2 is referred to, Fig. 2 is that a kind of frequency reconfigurable of AlAs/Ge/AlAs structures provided in an embodiment of the present invention is holographic
Antenna preparation method, the holographic antenna includes GeOI substrates (1), first antenna arm (2), the second antenna arm (3), coaxial feeder
(4), direct current biasing line and holographic annulus (14)；
Fig. 1 is referred to, Fig. 1 is the preparation method flow chart, including：
The solid plasma pin diodes of AlAs/Ge/AlAs structures are made on the GeOI substrates；The poles of the pin bis-
The P areas of pipe use AlAs materials, i areas to use Ge materials and N areas to use AlAs materials to form the heterogeneous poles of Ge bases plasma pin bis-
Pipe；
Joined end to end successively by the solid plasma pin diodes of multiple AlAs/Ge/AlAs structures and form plasma
Pin diode strings；
The first antenna arm and the second antenna arm are made by multiple plasma pin diodes strings；
The direct current biasing line is made on the GeOI substrates；Made on the first antenna arm and the second antenna arm
Coaxial feeder is forming the restructural holographic antenna.
In one embodiment of the invention, made on the GeOI substrates solid-states etc. of AlAs/Ge/AlAs structures from
Sub- pin diodes, refer to Fig. 3, and Fig. 3 is the solid plasma pin diode fabrication flow charts of AlAs/Ge/AlAs structures, bag
Include：
A () chooses GeOI substrates, and set isolated area in the GeOI substrates；
B () etches the GeOI substrates and forms p-type groove and N-type groove；
C () is in the p-type groove and the N-type groove and whole substrate surface deposits AlAs materials；Planarizing process
After GeOI substrates, AlAs layers is formed on GeOI substrates；
D AlAs layers of () photoetching, p type impurity and N-type are injected separately into the p-type groove and the N-type groove position
Impurity with formed the p-type active area and the N-type active area and simultaneously formed p-type contact zone and N-type contact zone；
E () removes photoresist；The AlAs materials beyond p-type contact zone and N-type contact zone are removed using wet etching；And
F () forms lead in the p-type active area and the N-type surfaces of active regions, to complete the AlAs/Ge/AlAs
The preparation of the solid plasma pin diodes of structure.
Wherein, it is for step (a), the reason for using GeOI substrates, for solid plasma antenna because it needs
Good microwave property, and solid plasma pin diodes in order to meet this demand, it is necessary to possess good isolation characteristic and
Carrier is the restriction ability of solid state plasma, and GeOI substrates can be conveniently formed pin because it has with isolation channel
Area of isolation, silica (SiO2) also can be that solid state plasma is limited in top layer Ge by carrier, it is advantageous to adopt
With GeOI as solid plasma pin diodes substrate.Also, because the carrier mobility of germanium material is than larger, therefore can
Plasma density higher is formed in I areas, the performance of device is improved.
Further, step (a) includes：
(a1) the first protective layer is formed in the GeOI substrate surfaces；
(a2) the first isolated area figure is formed on first protective layer using photoetching process；
(a3) dry etch process is utilized, in first protection of the specified location etching of the first isolated area figure
Layer and the GeOI substrates to form isolation channel, and the isolation channel depth more than or equal to the top layer Ge's of the GeOI substrates
Thickness；
(a4) isolation channel is filled to form the isolated area.
Specifically, the first protective layer includes the first silica (SiO2) layer and the first silicon nitride (SiN) layer；Then first protect
The formation of sheath includes：In GeOI substrate surfaces generation silica (SiO2) forming the first silica (SiO2) layer；
One silica (SiO2) layer surface generates silicon nitride (SiN) forming the first silicon nitride (SiN) layer.The benefit of do so exists
In using silica (SiO2) loose nature, by the stress isolation of silicon nitride (SiN), prevent it from conducting into top layer Ge,
Ensure that the stabilization of top layer Ge performances；Based on silicon nitride (SiN) and high selectivities of the Ge in dry etching, using silicon nitride
(SiN) film is sheltered as dry etching, it is easy to which technique is realized.It is, of course, understood that the number of plies of protective layer and protection
The material of layer is not limited herein, as long as protective layer can be formed.
Wherein, thickness of the depth of isolation channel more than or equal to top layer Ge, it is ensured that silica (SiO in follow-up groove2) with
The connection of the oxide layer of GeOI substrates, forms complete being dielectrically separated from.
In one embodiment of the invention, step (b) includes：
(b1) the second protective layer is formed in the GeOI substrate surfaces；
(b2) the second isolated area figure is formed on second protective layer using photoetching process；
(b3) the specified location etching described second using dry etch process in the second isolated area figure is protected
Layer and top layer Ge the layer of the GeOI substrates are with described top layer Ge layer interior formation the p-type groove and the N-type groove.
Specifically, the second protective layer includes the second silica (SiO2) layer and the second silicon nitride (SiN) layer；Then second protect
The formation of sheath includes：In GeOI substrate surfaces generation silica (SiO2) forming the second silica (SiO2) layer；
Two silica (SiO2) layer surface generates silicon nitride (SiN) forming the second silicon nitride (SiN) layer.The benefit of do so is similar to
In the effect of the first protective layer, here is omitted.
Wherein, the depth of p-type groove and N-type groove is served as a contrast more than the second protective layer thickness and less than the second protective layer and GeOI
Bottom top layer Ge thickness sums.Preferably, distance of the bottom of the p-type groove and N-type groove away from the top layer Ge bottoms of GeOI substrates
It is 0.5 micron~30 microns, forms the deep trouth being generally acknowledged that, impurity point can be so formed when p-type and N-type active area is formed
Cloth is uniform and P, N area of high-dopant concentration and tied with precipitous Pi and Ni, is beneficial to and improves i areas plasma density.
Furthermore, before step (f), also include：
(x1) the p-type groove and the N-type groove are aoxidized so that the inwall shape of the p-type groove and the N-type groove
Into oxide layer；
(x2) oxide layer of the p-type groove and the N-type trench wall is etched to complete using wet-etching technology
State the planarizing of p-type groove and the N-type trench wall.This have the advantage that：The projection shape of trenched side-wall can be prevented
Into electric field concentrated area, Pi and Ni junction breakdowns are caused.
Furthermore, before step (f), can also include：
(y1) SiO is generated in whole substrate surface2Material；
(y2) impurity in the p-type active area and the N-type active area is activated using annealing process.
In one embodiment of the invention, step (f) includes：
(f1) the p-type contact zone and N-type contact zone surface specific bit are etched away using anisotropic etch process
The SiO2 materials put are forming the fairlead；
(f2) to depositing metal material in the fairlead, treatment is passivated to whole backing material and photoetching PAD with
Form the solid plasma pin diodes of the AlAs/Ge/AlAs structures.
In one embodiment of the invention, the holographic annulus (14) is by eight sections of isometric AlAs/Ge/AlAs
The solid plasma pin diode string arrangement form octagon structures of structure, the radius of the circumscribed circle of the octagon is
3/4ths of the electromagnetic wavelength of the antenna reception or transmission；Wherein, the length of side of the octagon with described first day
Line arm (2) is identical with the second antenna arm (3) length sum.
In one embodiment of the invention, the first antenna arm (2) and second antenna arm (3) are along described coaxial
The distribution of feeder line (4) axial symmetry and the solid plasma pin diode strings of the AlAs/Ge/AlAs structures including equal number.
In one embodiment of the invention, also including be made in the GeOI substrates (1) direct current biasing line (5,6,7,
8、9、10、11、12)；Direct current biasing line (5,6,7,8,9,10, the 11,12) intermittent is electrically connected to the poles of the SPiN bis-
Pipe string (w1, w2, w3, w4, w5, w6) two ends.
It is multiple using the frequency reconfigurable plasma holographic antenna small volume of present embodiment, simple structure, easy to process, nothing
Miscellaneous feed structure, frequency can rapid jumping, and antenna close when will can be used for various frequency hopping radio sets in the stealthy state of electromagnetic wave
Or equipment；It is planar structure, it is easy to organize battle array because its all constituents is in semiconductor chip side, can be used as phased array
The basic component units of antenna.
Embodiment two
Refer to solid-state of a kind of AlAs/Ge/AlAs structures that Fig. 4 a- Fig. 4 r, Fig. 4 a- Fig. 4 r are the embodiment of the present invention etc.
The preparation method schematic diagram of ion pin diodes, on the basis of above-described embodiment one, with prepare channel length as 22nm (Gu
State ion plasma length of field be 100 microns) AlAs/Ge/AlAs structures solid plasma pin diodes as a example by carry out in detail
Illustrate, comprise the following steps that：
Step 1, backing material preparation process：
(1a) as shown in fig. 4 a, chooses (100) crystal orientation, and doping type is p-type, and doping concentration is 1014cm-3GeOI lining
Egative film 101, the thickness of top layer Ge is 50 μm；
(1b) as shown in Figure 4 b, using chemical vapor deposition (Chemical vapor deposition, abbreviation CVD)
Method, deposits one layer of SiO of 40nm thickness on GeOI substrates2Layer 201；
(1c) deposits one layer of 2 Si of μ m thick using the method for chemical vapor deposition on substrate3N4/ SiN layer
202；
Step 2, isolates preparation process：
(2a) as illustrated in fig. 4 c, isolated area, wet etching isolated area is formed by photoetching process on above-mentioned protective layer
One Si3N4/ SiN layer 202, forms isolated area figure；Using dry etching, form wide 5 μm in isolated area, depth be 50 μm it is deep every
From groove 301；
(2b) as shown in figure 4d, using the method for CVD, deposits SiO2401 fill up the deep isolation trench；
(2c) as shown in fig 4e, using chemically mechanical polishing (Chemical Mechanical Polishing, referred to as
CMP) method, removes the Si of surface the3N4The SiO of/SiN layer 202 and the2Layer 201, makes GeOI substrate surfaces smooth；
Step 3, P, N area deep trouth preparation process：
(3a) as shown in fig. 4f, using CVD method, consecutive deposition prolongs two layer materials on substrate, and ground floor is 300nm thick
2nd SiO of degree2Layer 601, the second layer is the 2nd Si of 500nm thickness3N4/ SiN layer 602；
(3b) as shown in figure 4g, photoetching P, N areas deep trouth, the Si of wet etching P, N areas the 2nd3N4The SiO of/SiN layer 602 and the 2nd2
Layer 601, forms P, N area figure；Using dry etching, form wide 4 μm in P, N area, deep 5 μm deep trouth 701, the length of P, N area groove
Degree determines according to the applicable cases in prepared antenna；
(3c) as shown in figure 4h, at 850 DEG C, high-temperature process 10 minutes, oxidation trough inwall forms oxide layer 801, so that
P, N area groove inwall are smooth；
(3d) as shown in figure 4i, the oxide layer 801 of P, N area groove inwall is removed using wet-etching technology.
Step 4, P, N contact zone preparation process：
(4a) as shown in figure 4j, using Metalorganic chemical vapor deposition (Metal-organic ChemicalVapor
Deposition, abbreviation MOCVD) technique, polymorph A lAs1001 is deposited in P, N area groove, and groove is filled up；
(4b) as shown in fig. 4k, using CMP, removes surface polymorph A lAs1001 and the 2nd Si3N4/ SiN layer 602, makes surface
It is smooth；
(4c) as shown in Fig. 4 l, using the method for CVD, in one layer of polymorph A lAs1201 of surface deposition, thickness is 200~
500nm；
(4d) as shown in Fig. 4 m, photoetching P areas active area carries out P using band glue ion injection method+Injection, makes P areas active
Area's doping concentration reaches 0.5 × 1020cm-3, photoresist is removed, form P contacts 1301；
(4e) photoetching N areas active area, N is carried out using band glue ion injection method+Injection, makes N areas active area doping concentration
It is 0.5 × 1020cm-3, photoresist is removed, form N contacts 1302；
(4f), using wet etching, etches away the polymorph A lAs1201 beyond P, N contact zone as shown in Fig. 4 n, forms P, N
Contact zone；
(4g) as shown in Fig. 4 o, using the method for CVD, in surface deposition SiO21501, thickness is 800nm；
(4h) anneals 1 minute at 1000 DEG C, makes the impurity activation of ion implanting and advances impurity in AlAs；
Step 5, constitutes PIN diode step：
(5a) as shown in Fig. 4 p, the lithography fair lead 1601 in P, N contact zone；
(5b) as shown in Fig. 4 q, substrate surface splash-proofing sputtering metal forms metal silicide 1701, and etch in 750 DEG C of alloys
Fall the metal on surface；
(5c) substrate surface splash-proofing sputtering metal, photoetching lead；
(5d) deposits Si as shown in Fig. 4 r3N4/ SiN forms passivation layer 1801, and photoetching PAD forms PIN diode, as
Prepare solid plasma antenna material.
In the present embodiment, above-mentioned various technological parameters are for example, according to the conventional meanses of those skilled in the art
The conversion done is the protection domain of the application.
The pin diodes for being applied to solid plasma reconfigurable antenna prepared by the present invention, first, the germanium material for being used
Material, due to its high mobility and the characteristic of big carrier lifetime, improves the solid plasma bulk concentration of pin diodes；Secondly,
Germanium material can be in high temperature ring due to the treatment that the characteristic of its oxide GeO heat endurances difference, P areas and N areas deep groove side wall are planarized
Border is automatically performed, and simplifies the preparation method of material；Again, what prepared by the present invention is applied to solid plasma reconfigurable antenna
GeOI base pin diodes employ a kind of Deep trench isolation technique based on etching, are effectively improved the breakdown potential of device
Pressure, it is suppressed that influence of the leakage current to device performance.
Embodiment three
The solid plasma pin bis- of the AlAs/Ge/AlAs structures provided for the present invention please also refer to Fig. 5 and Fig. 6, Fig. 5
The structural representation of pole pipe；Fig. 6 is a kind of solid plasma pin bis- of AlAs/Ge/AlAs structures provided in an embodiment of the present invention
The structural representation of pole pipe string.The solid plasma pin diodes of the AlAs/Ge/AlAs structures are using above-mentioned as shown in Figure 1
Preparation method is made, and specifically, the solid plasma pin diodes of the AlAs/Ge/AlAs structures are made on GeOI substrates 301
It is standby to be formed, and the P areas 304 of pin diodes, N areas 305 and the equal position in I areas that is laterally positioned between the P areas 304 and the N areas 305
In in top layer Ge layers 302 of the GeOI substrates.Wherein, the pin diodes can use STI deep trench isolations, the i.e. He of P areas 304
The outside of the N areas 305 is each provided with an isolation channel 303, and the isolation channel 303 thickness of the depth more than or equal to Ge layers 302 of the top layer
Degree.
Above content is to combine specific preferred embodiment further description made for the present invention, it is impossible to assert
Specific implementation of the invention is confined to these explanations.For general technical staff of the technical field of the invention,
On the premise of not departing from present inventive concept, some simple deduction or replace can also be made, should be all considered as belonging to of the invention
Protection domain.
Claims (10)
1. a kind of frequency reconfigurable holographic antenna preparation method of AlAs/Ge/AlAs structures, it is characterised in that the holographic day
Line includes GeOI substrates (1), first antenna arm (2), the second antenna arm (3), coaxial feeder (4), direct current biasing line and holographic circle
Ring (14)；Wherein, the preparation method includes：
The solid plasma pin diodes of AlAs/Ge/AlAs structures are made on the GeOI substrates；The pin diodes
P areas use AlAs materials, i areas to use Ge materials and N areas to use AlAs materials to form heterogeneous Ge bases plasma pin diodes；
Joined end to end successively by the solid plasma pin diodes of multiple AlAs/Ge/AlAs structures and form plasma pin
Diode string；
The first antenna arm and the second antenna arm are made by multiple plasma pin diodes strings；
The direct current biasing line is made on the GeOI substrates；Made on the first antenna arm and the second antenna arm coaxial
Feeder line is forming the restructural holographic antenna.
2. preparation method according to claim 1, it is characterised in that make AlAs/Ge/AlAs on the GeOI substrates
The solid plasma pin diodes of structure, including：
A () chooses GeOI substrates, and set isolated area in the GeOI substrates；
B () etches the GeOI substrates and forms p-type groove and N-type groove；
C () is in the p-type groove and the N-type groove and whole substrate surface deposits AlAs materials；Planarizing process GeOI
After substrate, AlAs layers is formed on GeOI substrates；
D AlAs layers of () photoetching, p type impurity and N-type impurity are injected separately into the p-type groove and the N-type groove position
To form the p-type active area and the N-type active area and form p-type contact zone and N-type contact zone simultaneously；
E () removes photoresist；The AlAs materials beyond p-type contact zone and N-type contact zone are removed using wet etching；And
F () forms lead in the p-type active area and the N-type surfaces of active regions, to complete the AlAs/Ge/AlAs structures
Solid plasma pin diodes preparation.
3. preparation method according to claim 2, it is characterised in that step (a) includes：
(a1) the first protective layer is formed in the GeOI substrate surfaces；
(a2) the first isolated area figure is formed on first protective layer using photoetching process；
(a3) utilize dry etch process, the specified location of the first isolated area figure etch first protective layer and
The GeOI substrates to form isolation channel, and the isolation channel thickness of the depth more than or equal to the top layer Ge of the GeOI substrates
Degree；
(a4) isolation channel is filled to form the isolated area.
4. preparation method according to claim 2, it is characterised in that first protective layer includes a SiO2Layer and the
One SiN layer；Correspondingly, step (a1) includes：
(a11) SiO is generated in the GeOI substrate surfaces2Material is forming a SiO2Layer；
(a12) in a SiO2Layer surface generates SiN materials to form the first SiN layer.
5. preparation method according to claim 2, it is characterised in that step (b) includes：
(b1) the second protective layer is formed in the GeOI substrate surfaces；
(b2) the second isolated area figure is formed on second protective layer using photoetching process；
(b3) using dry etch process the specified location of the second isolated area figure etch second protective layer and
Top layer Ge layers of the GeOI substrates is with the formation p-type groove and the N-type groove in described top layer Ge layers.
6. preparation method according to claim 2, it is characterised in that second protective layer include the 2nd SiO2 layer with the
Two SiN layers；Correspondingly, step (b1) includes：
(b11) SiO is generated in the GeOI substrate surfaces2Material is forming the 2nd SiO2Layer；
(b12) in the 2nd SiO2Layer surface generates SiN materials to form the second SiN layer.
7. preparation method according to claim 2, it is characterised in that step (f) includes：
(f1) the p-type contact zone and N-type contact zone surface specified location are etched away using anisotropic etch process
SiO2Material is forming the fairlead；
(f2) to metal material is deposited in the fairlead, treatment is passivated to whole backing material and photoetching PAD is to form
The solid plasma pin diodes of the AlAs/Ge/AlAs structures.
8. preparation method according to claim 1, it is characterised in that the holographic annulus (14) is by eight sections of isometric institutes
The solid plasma pin diode string arrangement form octagon structures of AlAs/Ge/AlAs structures are stated, the octagon
The radius of circumscribed circle is 3/4ths of the electromagnetic wavelength of the antenna reception or transmission；Wherein, the side of the octagon
Length is identical with the first antenna arm (2) and second antenna arm (3) length sum.
9. preparation method according to claim 1, it is characterised in that the first antenna arm (2) and second antenna
Arm (3) is distributed and including the solid-state of the AlAs/Ge/AlAs structures of equal number etc. along the coaxial feeder (4) axial symmetry
Ion pin diode strings.
10. preparation method according to claim 1, it is characterised in that also including being made in the straight of the GeOI substrates (1)
Stream offset line (5,6,7,8,9,10,11,12)；The electrical connection of direct current biasing line (5,6,7,8,9,10, the 11,12) intermittent
To SPiN diodes string (w1, w2, w3, w4, the w5, w6) two ends.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102790084A (en) * | 2011-05-16 | 2012-11-21 | 中国科学院上海微系统与信息技术研究所 | Germanium and III-V mixed coplanar silicon on insulator (SOI) semi-conductor structure and preparation method thereof |
| CN105118781A (en) * | 2015-09-02 | 2015-12-02 | 西安科技大学 | UTB-SOI tunneling field-effect transistor with abrupt junction and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102790084A (en) * | 2011-05-16 | 2012-11-21 | 中国科学院上海微系统与信息技术研究所 | Germanium and III-V mixed coplanar silicon on insulator (SOI) semi-conductor structure and preparation method thereof |
| CN105118781A (en) * | 2015-09-02 | 2015-12-02 | 西安科技大学 | UTB-SOI tunneling field-effect transistor with abrupt junction and preparation method thereof |
Non-Patent Citations (1)
| Title |
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| DA-JIN KIM等: "《Optomization of the Intrinsic Length of a PIN Diode for a Reconfigurable Antenna》", 《2016 INTERNATIONAL CONFERENCE ON ELECTRONICS，INFORMATION，AND COMMUNICATIONS》 * |
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