CN106773944B - Digital channel machine interface circuit based on CPLD - Google Patents
Digital channel machine interface circuit based on CPLD Download PDFInfo
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- CN106773944B CN106773944B CN201611140660.5A CN201611140660A CN106773944B CN 106773944 B CN106773944 B CN 106773944B CN 201611140660 A CN201611140660 A CN 201611140660A CN 106773944 B CN106773944 B CN 106773944B
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- 230000005540 biological transmission Effects 0.000 claims abstract description 8
- 230000001360 synchronised effect Effects 0.000 claims description 4
- 238000012827 research and development Methods 0.000 abstract description 8
- 238000000034 method Methods 0.000 abstract description 3
- 238000012545 processing Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 3
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/23—Pc programming
- G05B2219/23216—Extend processing time by extending enable signal with special output signal
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Abstract
The invention discloses a digital channel machine interface circuit based on CPLD, which mainly comprises CPLD chip and gate circuit chip with tri-state output; the I/O Bank2 part of the CPLD adopts 1.8V power supply, and the I/O interface is used as a digital channel machine interface; the I/O Bank1 part adopts 3.3V power supply, and the I/O interface is used as an ARM chip interface; the gate with tri-state output serves as a channel for transmitting data to the digital channelizer. And performing time sequence conversion and interface level bridging on the communication interface data of the digital channel machine and the ARM communication interface data through the CPLD, thereby realizing data transmission communication between the ARM chip and the digital channel machine. The method has the advantages that technical conditions are better utilized in the digitizing process of railway communication, the reliability of equipment is better ensured, meanwhile, the research and development period of the 400MHz digital communication radio station of the railway is shortened, and the research and development cost is saved.
Description
Technical Field
The invention relates to a digital interface circuit for carrying out data transmission communication with a digital channel machine by adopting an ARM chip, in particular to a CPLD-based digital channel machine interface circuit.
Background
Currently, the railway wireless train modulation system in China is in the stage of upgrading from 450MHz analog system to 400MHz digital system, and the main stream 400MHz digital channel machines widely used in the market, such as XIR M6600 series, XIR M8200 series and the like, adopt external control communication interfaces which are 128-bit SSI bus interfaces, and the interface level is generally 1.8V. The bus interface divides each frame of data into 8 time slots, each time slot has 16 bits of data, so that the time division multiplexing of the data bus is realized, the first 2 bus time slots are used for communication inside a channel machine, and the last 6 bus time slots are used for communication between an external controller and the channel machine. The control chip of the radio station equipment of the railway wireless train dispatching system in China currently commonly adopts ARM processors, such as LPC1700 series, LPC4300 series and the like, and the ARM processors have low cost, excellent performance and mature use technology. The SSI bus interface of the ARM chip is a 4-16-bit configurable data bus, and the interface level is 3.3V, so that the ARM chip cannot directly perform data communication with external control interfaces of main stream digital channel machines such as XIR M6600 series, XIR M8200 series and the like.
The number of processor types capable of directly carrying out data communication with the SSI bus interface of the 128-bit digital channel machine is very small, and a corresponding software compiling environment needs to be established by using a novel number of processor chips, so that the product research and development period is delayed, and the research and development cost is increased.
Disclosure of Invention
In view of the problems of the prior art, it is an object of the present invention to provide a CPLD-based digital channel machine interface circuit. The interface circuit mainly comprises CPLD chip and band a gate chip with tri-state output; the I/O Bank2 part of the CPLD adopts 1.8V power supply, and the I/O interface is used as a digital channel machine interface; the I/O Bank1 part adopts 3.3V power supply, and the I/O interface is used as an ARM chip interface; the gate with tri-state output serves as a channel for transmitting data to the digital channelizer. And performing time sequence conversion and interface level bridging on the communication interface data of the digital channel machine and the ARM communication interface data through the CPLD chip, thereby realizing data transmission communication between the ARM chip and the digital channel machine.
The circuit design continues to use ARM processors such as LPC1700 series, LPC4300 series and the like as control chips, can effectively utilize the existing software compiling environment and hardware circuit design experience, greatly shortens the research and development period, saves the research and development cost, and can better ensure the reliability of equipment.
The technical scheme adopted by the invention is as follows: a CPLD-based digital channel machine interface circuit, characterized in that: the circuit comprises a CPLD chip with the model number of 5M40ZE64I5 and a gate chip with the model number of 74LV1T125 and tri-state output; the I/O Bank1 part power supply pin VCCIO1 of the CPLD chip is connected with DC3.3V for power supply, and the I/O Bank2 part power supply pin VCCIO2 is connected with DC1.8V for power supply; the 1 pin, the 2 pin, the 3 pin, the 4 pin and the 5 pin of the CPLD chip I/O Bank1 part are respectively connected with an SSI bus frame synchronization SSP0_FSYNC pin, an SSI bus clock SSP0_SCK pin, an SSI bus data SSP0_MOSI pin and an SSI bus data SSP0_MISO pin of the ARM chip, and are in data communication with the ARM chip; the 63 pin, the 42 pin and the 62 pin of the CPLD chip I/O Bank2 part are respectively connected with an SSI bus frame synchronization SSI_FSYNC pin, an SSI bus clock SSI_SCK pin and an SSI bus data SSI_MOSI pin of an external control interface of the digital channel machine; the 60 pins of the I/O Bank2 part of the CPLD chip are connected with the OE pins of the tri-state output gate circuit chip to control the output state of the gate circuit; the input pin A of the tri-state output gate circuit chip is connected with the 61 pin of the I/O Bank2 part of the CPLD chip, the output pin Y of the tri-state output gate circuit chip is connected with the SSI bus data SSI_MISO pin of the external control interface of the digital channel machine and is used as a data transmission channel.
The beneficial effects of the invention are as follows: the data communication of the ARM processor chips such as LPC1700 series, LPC4300 series and the like and the digital channel machine communication such as XIR M6600 series, XIR M8200 series and the like are realized, so that the technical condition is better utilized in the digitizing process of railway communication, the research and development period of the railway 400MHz digital communication radio station is shortened while the reliability of equipment is better ensured, and the research and development cost is saved.
Drawings
FIG. 1 is a schematic diagram of the principles of the present invention;
FIG. 2 is a schematic diagram of data timing conversion according to the present invention.
Detailed Description
For a clearer understanding of the present invention, reference is made to the following detailed description taken in conjunction with the accompanying drawings and examples.
As shown in fig. 1 and 2, a digital channel machine interface circuit based on a CPLD includes a CPLD chip and a gate chip with tri-state output, wherein the CPLD chip uses a 5M40ZE64I5N chip, and the gate chip with tri-state output uses a 74LV1T125 chip.
The I/O Bank1 part power supply pin VCCIO1 of the CPLD chip is connected with DC3.3V for power supply, and the I/O Bank2 part power supply pin VCCIO2 is connected with DC1.8V for power supply; the 1 pin, the 2 pin, the 3 pin, the 4 pin and the 5 pin of the CPLD chip I/O Bank1 part are respectively connected with an SSI bus frame synchronization SSP0_FSYNC pin, an SSI bus clock SSP0_SCK pin, an SSI bus data SSP0_MOSI pin and an SSI bus data SSP0_MISO pin of the ARM chip, and are in data communication with the ARM chip; the 63 pin, the 42 pin and the 62 pin of the CPLD chip I/O Bank2 part are respectively connected with an SSI bus frame synchronization SSI_FSYNC pin, an SSI bus clock SSI_SCK pin and an SSI bus data SSI_MOSI pin of an external control interface of the digital channel machine; the 60 pins of the I/O Bank2 part of the CPLD chip are connected with the OE pins of the tri-state output gate circuit chip to control the output state of the gate circuit; the input pin A of the tri-state output gate circuit chip is connected with the 61 pin of the I/O Bank2 part of the CPLD chip, and the output pin Y of the tri-state output gate circuit chip is connected with the SSI bus data SSI_MISO pin of the external control interface of the digital channel machine as a data transmission channel.
The working principle of the design is described in detail below with reference to fig. 1 and 2: the I/O Bank1 part of the CPLD chip is powered by DC3.3V through VCCIO1, the signal level of the I/O Bank1 part of the CPLD chip is 3.3V, and the I/O pin of the CPLD chip is used as a power supply for connecting with an ARM processor chip; the I/O (input/output) band 2 part of the CPLD chip is powered by DC1.8V through VCCIO2, the signal level of the I/O pin of the I/O band 2 part is 1.8V, and the I/O pin of the I/O band 2 part is used as a communication interface connected with a digital channel machine, so that signal level bridging of the ARM processor chip and the digital channel machine communication interface is realized.
On an SSI bus for data communication between the digital channel machine and the ARM processor, the digital channel machine is a master device, and the ARM processor is a slave device. The CPLD chip pin 63 is used as an input I/O interface to be connected with a frame synchronization signal pin SSI_FSYNC of a digital channel machine communication interface SSI bus, and the pins 1 and 2 are used as output I/O interfaces to be respectively connected with an external interrupt input pin INT0 of the ARM processing chip and an SSI bus frame synchronization signal pin SSP0_FSYNC. The CPLD chip carries out level conversion on an input SSI_FSYNC signal and outputs the signal to an INT0 pin of the ARM processor as a frame synchronization signal; meanwhile, 7 effective signals are added in each period on the basis of the SSI_FSYNC signal, the SSI_FSYNC signal period is divided into 8 parts, namely a synchronous signal is arranged corresponding to each time slot, and the signals are output to an SSP0_FSYNC pin of an ARM processor chip after level conversion and are used as time slot synchronous signals; pin 42 of the CPLD chip is connected to the clock signal pin ssi_sck of the SSI bus of the digital channel machine communication interface as an input clock signal interface, and pin 3 is connected to the SSI bus clock signal pin ssp0_sck of the ARM processing chip as an output I/O interface. The CPLD chip takes the input SSI_SCK signal as a self working clock, and simultaneously outputs the SSI_SCK signal to an SSP0_SCK pin of the ARM processor after level conversion as an SSI bus clock signal.
Pin 62 of the CPLD chip is connected to the data transmission pin ssi_mosi of the SSI bus of the digital channel machine communication interface as an input I/O interface, and pin 4 is connected to the SSI bus data reception pin ssp0_mosi of the ARM processing chip as an output I/O interface. The CPLD performs level conversion on the input SSI_MOSI data signal and outputs the signal to the SSP0_MOSI pin of the ARM processor.
Pins 61 and 60 of the CPLD chip are used as output I/O interfaces to be respectively connected with an input pin A and an enabling pin OE of the gate circuit chip with tri-state output, and pin 5 is used as an input I/O interface to be connected with an SSI bus data transmission pin SSP0_MISO of the ARM processing chip; the gate chip output pin Y with tri-state output is connected to the data receiving pin ssi_miso of the digital channel machine communication interface SSI bus. The CPLD chip outputs the input SSP0_MISO data signal to the input pin A of the gate circuit chip after level conversion, and simultaneously outputs low-level signals to the enable pin OE of the gate circuit chip in the first 2 time slots of each frame of SSI bus data, so that the gate circuit outputs high-impedance state in time slot 1 and time slot 2, and interference to time slot 1 and time slot 2 data of the SSI bus of the digital channel machine is avoided; the last 6 time slots of the SSI bus data of each frame output a high-level signal to an enable pin OE of the gate circuit chip, so that the gate circuit passes the input data to an SSI_MISO pin of the digital channel machine from time slot 3 to time slot 8.
The ARM processor chip configures the SSI bus into a 16-bit bus, and frames data on the SSI bus by utilizing a frame synchronization signal of an INT0 pin, so that data communication with an external communication interface of the digital channel machine can be realized through the interface circuit.
Claims (1)
1. A CPLD-based digital channel machine interface circuit, characterized in that: the circuit comprises a CPLD chip with the model number of 5M40ZE64I5 and a gate chip with the model number of 74LV1T125 and tri-state output; the I/O Bank1 part power supply pin VCCIO1 of the CPLD chip is connected with DC3.3V for power supply, and the I/O Bank2 part power supply pin VCCIO2 is connected with DC1.8V for power supply; the 1 pin, the 2 pin, the 3 pin, the 4 pin and the 5 pin of the CPLD chip I/O Bank1 part are respectively connected with the SSI bus frame synchronization SSP0_FSYNC pin, the SSI bus clock SSP0_SCK pin, the SSI bus data SSP0_MOSI pin and the SSI bus data SSP0_MISO pin of the ARM chip to realize the signal level bridging of the communication interface of the ARM processor chip and the digital channel machine;
the 63 pin, the 42 pin and the 62 pin of the CPLD chip I/O Bank2 part are respectively connected with an SSI bus frame synchronization SSI_FSYNC pin, an SSI bus clock SSI_SCK pin and an SSI bus data SSI_MOSI pin of an external control interface of the digital channel machine; the CPLD chip carries out level conversion on an input SSI_FSYNC signal and outputs the signal to an INT0 pin of the ARM processor as a frame synchronization signal; dividing the SSI_FSYNC signal period into 8 parts, wherein a synchronous signal is arranged corresponding to each time slot, and outputting the SSI_FSYNC signal to an SSP0_FSYNC pin of an ARM processor chip after performing level conversion as a time slot synchronous signal;
the 60 pins of the I/O Bank2 part of the CPLD chip are connected with the OE pins of the tri-state output gate circuit chip to control the output state of the gate circuit; the input pin A of the tri-state output gate circuit chip is connected with the 61 pin of the I/O Bank2 part of the CPLD chip, and the output pin Y of the tri-state output gate circuit chip is connected with the SSI bus data SSI_MISO pin of the external control interface of the digital channel machine as a data transmission channel.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201611140660.5A CN106773944B (en) | 2016-12-12 | 2016-12-12 | Digital channel machine interface circuit based on CPLD |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201611140660.5A CN106773944B (en) | 2016-12-12 | 2016-12-12 | Digital channel machine interface circuit based on CPLD |
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| CN106773944A CN106773944A (en) | 2017-05-31 |
| CN106773944B true CN106773944B (en) | 2023-12-12 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101807049A (en) * | 2010-02-05 | 2010-08-18 | 国电南京自动化股份有限公司 | Method of externally expanding parallel bus based on embedded ARM CPU |
| CN105224486A (en) * | 2014-11-20 | 2016-01-06 | 天津市英贝特航天科技有限公司 | Based on the 1553B bus protocol module of LBE bus |
| CN206258694U (en) * | 2016-12-12 | 2017-06-16 | 天津七一二通信广播股份有限公司 | Digital channel machine interface circuit based on CPLD |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6653860B2 (en) * | 2001-08-10 | 2003-11-25 | Lattice Semiconductor Corporation | Enhanced macrocell module having expandable product term sharing capability for use in high density CPLD architectures |
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2016
- 2016-12-12 CN CN201611140660.5A patent/CN106773944B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101807049A (en) * | 2010-02-05 | 2010-08-18 | 国电南京自动化股份有限公司 | Method of externally expanding parallel bus based on embedded ARM CPU |
| CN105224486A (en) * | 2014-11-20 | 2016-01-06 | 天津市英贝特航天科技有限公司 | Based on the 1553B bus protocol module of LBE bus |
| CN206258694U (en) * | 2016-12-12 | 2017-06-16 | 天津七一二通信广播股份有限公司 | Digital channel machine interface circuit based on CPLD |
Non-Patent Citations (1)
| Title |
|---|
| 基于CPLD的1_Wire器件控制研究;李江昊等;《微计算机信息》;20090915;正文第223-224、243页 * |
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