CN106095334A - A kind of high-speed data acquisition storage system based on FPGA - Google Patents
A kind of high-speed data acquisition storage system based on FPGA Download PDFInfo
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- CN106095334A CN106095334A CN201610395244.3A CN201610395244A CN106095334A CN 106095334 A CN106095334 A CN 106095334A CN 201610395244 A CN201610395244 A CN 201610395244A CN 106095334 A CN106095334 A CN 106095334A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0685—Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
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Abstract
The invention discloses a kind of high-speed data acquisition storage system based on FPGA, including FPGA core core, data acquisition module, MPU module, Gigabit Ethernet module, display module, input and output, memory module.Described memory module is connected with core devices FPGA by DDR3, and the interface such as display, mouse, keyboard, kilomega network passes through MPU module and is connected with PCI E Switch, it is achieved the data interaction with FPGA.2 MINISAS interface modules are directly connected with FPGA and carry out data interaction.It is capable of the functions such as the importing of data, derivation, the analysis of data, maintenance by the software systems of system, and can realize that simple data are analyzed in real time.The message transmission rate of the present invention is high, amount of storage is big, can on-the-spot dilatation and carry out Bad Block Management；System interface is many, has higher user experience；Between each modular unit of system, interactivity is good, supports remote ethernet control.
Description
Technical field
The present invention relates to a kind of high-speed data acquisition storage system, particularly relate to a kind of high-speed data based on FPGA and adopt
Collection storage system.
Background technology
Becoming increasingly popular along with electronic product, has driven the fast development of data acquisition technology and data storage technology.
Particularly in technical fields such as satellite navigation, electronics, radars, data acquisition storage system increasingly plays very important work
With.And require to the technology of data acquisition and memory system also day by day to improve: high data sample rates, high data rate,
Mass memory capacity, power consumption and low cost.Traditional data acquisition storage system is difficult to meet such requirement.
FPGA (Field Programmable Gate Array, the field programmable gate array) technology of development in recent years
Provide good technical support for a new generation's high-speed data acquisition storage system.FPGA has very many hardware resources, collection
Become utilogic gate circuit on one chip to reach ten million rank, very high time-frequency can be obtained by internal phaselocked loop,
Consume little when internal, and efficiency be very high, flexible structure, can integrated multiple controllers, translate coding and various peripheral interface electricity
Road, therefore can use FPGA to design data acquisition and data storage section.And in terms of signal transacting, FPGA is rich owing to having
Rich kernel resources, facilitates calling of user.Therefore, high-speed data acquisition storage system uses FPGA, can simplify design, carry
The flexibility of high system and processing speed.
Chinese patent 201010623689.5 discloses a kind of high-speed data acquistion system based on FPGA, including receive mould
Intend the A/D converting unit that is connected with described differential amplification unit of differential amplification unit of signal and described A/D converting unit
The microprocessor that the FPGA processing unit being connected is connected with described FPGA processing unit, described microprocessor is by communication
Interface is connected with host computer.But, there is following defect in this system: 1. the data storage capacity of system is little, do not support scene
Dilatation, and cannot be carried out Bad Block Management.2. the interface of system less, without software support, user experience is relatively low.3. system is each
Interactivity difference between modular unit.4. system does not support remote ethernet control.
Content of the invention
In place of it is an object of the invention to overcome the deficiencies in the prior art, a kind of high-speed data acquisition based on FPGA is proposed
Storage system, its memory data output is big, can on-the-spot dilatation and carry out Bad Block Management；The interface of this system is many, powerful
User experience under software support is high；Between each modular unit of system, interactivity is good；Further, this system supports remote ethernet
Control.
In order to solve the problems referred to above of prior art, the present invention is by the following technical solutions.
A kind of high-speed data acquisition storage system based on FPGA of the present invention, including data transmission storage hardware system and
Data transmission storage software systems, it is characterised in that:
Described data transmission storage hardware system, is integrated on a circuit board, comprising: FPGA core core, ETP patch
Part module, PCI-E switch module, MPU daughter card module, gigabit Ethernet mouth die block, display module, input/output module,
MINISAS interface module, SSD storage array module, DDR3 cache module；
Described Gigabit Ethernet module, display module, input/output module, SSD storage array module pass through MPU subcard
Module is connected with PCI-E switch module respectively, it is achieved the data interaction with FPGA core core；
Described SSD storage array module is connected with FPGA core core by least one-level DDR3 cache module；
Described FPGA core core includes GTP module, for being transmitted data with the form of differential signal；
MINISAS interface module described in 2, carries out data interaction for being directly connected with FPGA core core；
Described MPU daughter card module comprises ETX-Express connector, for south bridge and north with described MPU subcard
The data transmission of bridge；
Described SSD storage array module, including at least one is external solid with what control IC formed by Flash flash media
State hard disk；
Described data transmission storage software systems, including operating system, management software, MATLAB, communications protocol, dish battle array
Driving, bottom hardware drive part, for importing, the derivation of data, the analysis of data, maintenance, and simple data are real-time
Analyze；User carries out data interaction by input-output equipment and the system application of display module, input/output module.
Further, described FPGA core core uses Xilinx Zynq-7000 chip, and the GTP module that it includes is
High Data Rate is 6.125Gbps.
Further, described ETP connector module, including the EPT103-40064 connector of 2 96 cores；Described
The interface of EPT103-40064 connector includes 4 passages, and each passage can transmit 4 to LVDS data signal.
Further, described SSD storage array module, including multiple external solid state hard disc, constitutes multichannel data storage
The electric board battle array of passage.
Further, described PCI-E module, can configure port containing 15 tunnels.
Further, the described data in FPGA core core, before being stored in storage array, need to carry out procedure below:
(1) the parallel-to-serial conversion in phase compensation, (2) 8b/10b coding, (3).
Further, the described data in SSD storage array module carry out data process being input to FPGA core core
Before, procedure below need to be carried out: the serial-to-parallel conversion in the recovery of (1) clock, (2), (3) byte of sync, (4) 8b/10b compile
Code, and (5) phase compensation.
Further, the described data transmission storage hardware system based on FPGA, including the data transmission described in 4 is deposited
Storage hardware system surface-mounted integrated circuit；Described VPX interface, for described each data transmission storage hardware system integrated circuit
Being in communication with each other and data interaction between plate.
Compared with prior art, advantages of the present invention and beneficial effect include:
1. the storage system speed of present system is fast, stability is high, strong security.Support on-the-spot capacity extensions, can be straight
Connect replacing hard disk.And, multiple memory channel parallel memorizing, it is simple to the backup unloading of data.
2. software and hardware can be used simultaneously to utilize wear-leveling algorithm, ECC check method, the bad block of storage medium is entered
Row is safeguarded.Effectively prevent from storing the damage of data, it is possible to extend the service life of FLASH.For the data in bad block, during reading
Can be recovered by software.The mode using external solid state hard disc array stores, and the multichannel forming electronic array formula is high
Speed storage, it is simple to the backup unloading of data, it is achieved at a high speed, massive store, playback.Lasting writing speed >=the 700MB/ of veneer
s。
3. can select to be by the importing of data or the derivation of data by software operation, and can realize to data
The functions such as analysis, maintenance.Sophisticated software function, improves Consumer's Experience, mitigates data analysis difficulty.The MPU of employing standard
Subcard realizes the interfaces such as keyboard, mouse, kilomega network.Support operating system, management software, support that MATLAB etc. analyzes software.
4. use VPX interface as the bridge of contact between data board, the number that can be carried out by it between data board
According to alternately.Improve efficiency and the flexibility of whole system recorder memory.
5. the system of the present invention have employed the EPT103-40064 connector of 2 96 cores, and connector is by the difference on backboard
Signal is transferred directly to FPGA, and without being connected with MPU module or PCI-E SWITCH.By VPX connector and other numbers
Carry out the data transmission of high speed according to the interconnection of acquisition and recording plate, flank speed is up to 1.25GB/S.
6. human-computer interaction function can be shown by gui interface, can show receive and send to the control command of equipment,
BIT information, the work state information etc. of equipment.Support remote ethernet control.
Brief description
Fig. 1 is the functional block diagram of one embodiment of the present of invention.
Fig. 2 is the internal logic schematic diagram of the high-speed transceiver (GTP) of one embodiment of the present of invention.
Fig. 3 is the PCI-E Switch functional block diagram of one embodiment of the present of invention.
Fig. 4 is the functional block diagram of the MPU module of one embodiment of the present of invention.
Fig. 5 is the software architecture block diagram of one embodiment of the present of invention.
Detailed description of the invention
A kind of high-speed data acquisition storage system based on FPGA of the present invention, including data transmission storage hardware system and
Data transmission storage software systems, its data transmission storage hardware system, it is integrated on a circuit board, comprising: fpga core
Plate, ETP connector module, PCI-E switch module, MPU daughter card module, gigabit Ethernet mouth die block, display module, input and output
Module, MINISAS interface module, SSD storage array module (electric board battle array), DDR3 cache module；
Described Gigabit Ethernet module, display module, input/output module, SSD storage array module pass through MPU subcard
Module is connected with PCI-E switch module respectively, it is achieved the data interaction with FPGA core core；FPGA module and PCI-E switching molding
Can realize the exchange of data between block, 1 road X4 passage of PCI-E switch module is connected with VPX interface, it is possible to achieve this interface
Other backboards on plate and backboard realize data interaction, and between these backboards are completely self-contained system, can with interaction data,
But it is non-interference.
Described SSD storage array module is connected with FPGA core core by least one-level DDR3 cache module；For adjusting
Joint GTP module and the data difference of SSD.
Described FPGA core core includes GTP module, for being transmitted data with the form of differential signal；Thus subtract
Few interference to data for the external equipment.
MINISAS interface module described in 2, carries out data interaction for being directly connected with FPGA core core；And be not necessarily to
It is connected with MPU module or PCI-E SWITCH.
MPU daughter card module described in the embodiment of the present invention comprises ETX-Express connector, is used for and described MPU
The data transmission of the south bridge of card and north bridge；Its north bridge has 1 road 533MHz 64Bit to be connected with DDR2 caching, has 3 tunnels and ETX-
Express connector is connected, and is 1 road VGA analog signal, 1 road LVDS and 1 road PCI 16 respectively.And between the south bridge of MPU module
Connected by 4 road DMI 2.5GB/s.Comparing north bridge, the passage that south bridge is connected with ETX-Express connector is more, comprising: 1
Road LPC33MHz the 4th, 1 road USB1.5/12/480MHz the 6th, 2 road DATA 1.5GB/s, 1 road A/C, 4 road PCI-Express
2.5GB/s, 1 road IDE, 1 road GPIO, 1 road PCI 33MHz 32, in addition, there is 1 tunnel between south bridge and ETX-Express connector
Connected by 10/100B-T Ethernet.ETX-Express not only carries out data interaction with north and south bridge, also provides for
12VDC and SVSBY signal.
Described SSD storage array module, including at least one is external solid with what control IC formed by Flash flash media
State hard disk；
Described data transmission storage software systems, including operating system, management software, MATLAB, communications protocol, dish battle array
Driving, bottom hardware drive part, for importing, the derivation of data, the analysis of data, maintenance, and simple data are real-time
Analyze；User carries out data interaction by input-output equipment and the system application of display module, input/output module.Should
The function of software systems is mainly reflected in three aspects: the 1st, display function: realize based on Windows operating system, man-machine friendship
Mutual function can be shown by gui interface, can show and receives and send the control command to equipment, BIT information, the work of equipment
Make status information etc..2nd, system hardware equipment control function: include equipment record start/stop, playback startup/stopping,
The work method control of equipment, the selection control etc. of data input channel.3rd, data management function: mainly include to record data
Query function (according to temporal information), the intercepting of data, the upload/download function of data.Additionally can pass through MATLAB
Deng software, data are simply analyzed.
Described FPGA core core uses Xilinx Zynq-7000 chip, the maximum data rate of the GTP module that it includes
For 6.125Gbps.The FPGA of this product has been internally integrated ARM, and both carry out connecting at a high speed by AXI4 bus, efficiently solve
Transmission problem between FPAG and ARM.In addition, the power consumption of its high-speed transceiver GTP is very low, 500Mb/s 6.6Gb/s can be supported
Transfer rate.
Described ETP connector module, including the EPT103-40064 connector of 2 96 cores；Described EPT103-
The interface of 40064 connectors includes 4 passages, and each passage can transmit 4 to LVDS data signal.Described ETP connector mould
The EPT103-40064 connector of 2 96 cores of block, the signal for being transferred to FPGA core core also include 1 tunnel clock signal, 1
Road synchronizing signal and 4 road space signals.
Described SSD storage array module, including multiple external solid state hard disc, constitutes the electronics of multichannel data memory channel
Dish battle array.This electric board battle array can carry out Bad Block Management, wear-leveling algorithm, ECC check etc..The amount of capacity of one paths is
8T, four paths can realize the storage of 32T vast capacity.And the dilatation of the on-the-spot capacity of support, in the case that deposit is expired
Can directly change hard disk.
Described PCI-E module, can configure port containing 15 tunnels.It by these ports, is possible not only to transmission data and control
System/management information, or the bridge that FPGA module is connected with gigabit network interface, display, input-output equipment.
The described data in FPGA core core, before being stored in storage array, need to carry out procedure below: (1) phase place is mended
Repay, (2) 8b/10b coding, (3) parallel-to-serial conversion.
The described data in SSD storage array module are being input to before FPGA core core carries out data process, need to enter
Row procedure below: the serial-to-parallel conversion in the recovery of (1) clock, (2), (3) byte of sync, (4) 8b/10b coding, and
(5) phase compensation.
The described data transmission storage hardware system based on FPGA, including the data transmission described in 4 stores hardware system
System surface-mounted integrated circuit；Described VPX interface, between described each data transmission storage hardware system surface-mounted integrated circuit
It is in communication with each other and data interaction.
Below in conjunction with the accompanying drawings the present invention is described in further details.
Fig. 1 is the functional block diagram of one embodiment of the present of invention.As it is shown in figure 1, the one of one embodiment of the present of invention
Based on the high-speed data acquisition storage system of FPGA, its template size is 6U, a size of 233.35 × 220mm, the thickness of board
It is not more than 40.3mm.The power consumption of the data acquisition storage system board of one monolithic is less than 50W.This data acquisition logging system is logical
Cross the Zynq-7000 Series FPGA of Xilinx to realize the high speed acquisition of data, quick transmission and storage.And FPGA and MPU mould
Then by the PCI-E Switch of Integrated Device Technology, Inc., (external component interconnected EBI is opened in data transmission, control and management between block
Close) chip realization.
Realized the LVDS interface on connector, PCI-E port and 2 MINI SAS (mini strings by FPGA core core
Row connects interface) interface (simply use MINISAS interface, realize the data transmission of LVDS (low-voltage differential signal) signal,
The data width of 12, the clock of employing is 100MHz, and i.e. total data transfer rate is 150MB/S) between data conversion.Notebook data
Acquisition and recording system have employed the EPT103-40064 connector of 2 96 cores.Comprising 4 transmission channels on this interface, each passes
Defeated passage can transmit 2 groups (Rx and Tx) 4 pairs of LVDS signals, and data transfer rate is 80Mbps；Other transmission signals comprise 1 road clock letter
Number, 1 tunnel synchronizing signal and 4 road space signals.I.e. 4 passages can realize the data transmission of 160MB/S, for data storage with
And playback, in order to this data collecting system carries out data acquisition independent of other systems.PCI-E Switch device draws one simultaneously
PCI-E × 4, road, carry out high speed by VPX (high-speed serial bus interface) connector and the interconnection of other data acquiring and recording plates
Data are transmitted, and flank speed is 1.25GB/S.
Native system uses the electric board battle array of SSD storage array module composition as memory, it is achieved at a high speed, Large Copacity deposits
Storage, playback.Electric board battle array operating rate is fast, stability is high, the feature of strong security, is therefore usually used in special machine and Industry Control
Machine.Electric board battle array is made up of Flash flash media and control IC, is a kind of memory that can repeatedly read and write, installs and use non-
Often convenient.Owing to storage medium is flash memory, its shake-proof ability is stronger than common hard disc；And, speed faster, lightweight, very suitable
Use for mobile.Further, since this electric board battle array does not has the rotating media of common hard disc, thus shock resistance is splendid, work simultaneously
Making temperature range width, the electric board battle array of extended temperature can be operated in-40C-+85C, therefore can be widely applied to network computer
(NC), Industry Control, Aero-Space, military, the field such as navigator.
Fig. 2 is the internal logic schematic diagram of the high-speed transceiver (GTP) of one embodiment of the present of invention.As in figure 2 it is shown, this
The GTP high-speed transceiver of inventive embodiments is made up of with PMA (physical medium is connected) PCS (Physical Coding Sublayer).Sendaisle
The parallel signal that the PMA of part is mainly responsible for the input of stringization 8b/10b encoder section is bit stream, and the PMA of receiving portion is responsible for
The data of SFP optical module part input are become parallel by serial, but first has to from serial data, recover clock data
Out.Because the time-frequency required precision that transceiver uses is high, so the signal that first PCS of sendaisle part will send is defeated
Applying aspect compensates FIFO, compensates the PCS phase place of transmitting portion and the difference of FPGA kernel phase place, and outside input reference clock will be logical
Crossing special phase-locked loop circuit to produce, after by phase compensation FIFO, parallel data and serial data just can be highly same
Step.
Fig. 3 is the PCI-E Switch functional block diagram of one embodiment of the present of invention.As it is shown on figure 3, PCI-E Switch
It is the equipment of a kind of USB Hub being similar to and commonly using, but it can have up to N number of port, has been widely used in biography
In the storage system of system.Switch is new ideas, and it is compared with the bridge mode of previous generation standard PCI-X, a maximum basis
Matter difference uses Switch exchange exactly between the multiple roles within same Bus, and is no longer Bus, one
Switch is equivalent to the set of a virtual bridge and virtual Bus.Other PCI-E Switch can be by affairs between each port
Transmission.
The 92HD81B1B5NLB of Integrated Device Technology, Inc. is that the PCI Express Gen 2 supporting 15 ports 48 passage (Lanes) opens
Closing chip, the number of channels of each port may be configured to x4, x8 or x16, adds up to the bandwidth of 480GT/S.
It is flexible that the structure of 92HD81B1B5NLB chip is designed to comparison, and it is distributed in 48 passages in 3 Station, and each
Individual Station can be connected in Packet RAM by internal bus, is greatly improved efficiency.Each passage can also be joined
It is set to upstream and downstream port.
The each wide mouth of concrete PCI-E uses: the PCI-E of 5 road X2 for interface, the PCI-E of 1 road X4 for X86 module,
The PCI-E of 1 road X1 is for optical fiber.
Fig. 4 is the functional block diagram of the MPU module of one embodiment of the present of invention.As shown in Figure 4, MPU of standard is used
Card (being allocated as motherboard with storage part) realizes the interfaces such as display, keyboard, mouse, kilomega network.MPU daughter card module includes a piece of master
Frequency is at the Centrino processor of 1.4G to 2.13G.The a width of 133MHz of band between this processor and ITP-700.Pass through 533MHz
FSB*64-Bit is connected with the north bridge of MPU module.Kernel supply voltage is provided by RM-IMVP-IV.
The north bridge of MPU module has 1 road 533MHz 64Bit to be connected with DDR2 caching, has 3 tunnels and ETX-Express connector
It is connected, be 1 road VGA analog signal, 1 road LVDS and 1 road PCI 16 respectively.And pass through 4 road DMI between the south bridge of MPU module
2.5GB/s connect.Comparing north bridge, the passage that south bridge is connected with ETX-Express connector includes: 1 road LPC33MHz the 4th, 1 tunnel
USB1.5/12/480MHz the 6th, 2 road DATA 1.5GB/s, 1 road A/C, 4 road PCI-Express 2.5GB/s, 1 road IDE, 1 tunnel
GPIO, 1 road PCI 33MHz 32, also have 1 tunnel to be connected by 10/100B-T Ethernet in addition between south bridge with connector.
ETX-Express not only carries out data interaction with north and south bridge, also provides 12VDC and SVSBY signal.
Fig. 5 is the software architecture block diagram of one embodiment of the present of invention.As it is shown in figure 5, the software of high speed acquisition equipment is
Realize based on Windows operating system, be mainly used to realize man-machine interaction, the control of functions of the equipments module, data management, letter
Forms data is analyzed, the BIT work etc. of system.According to shown in software architecture, when operator needs to carry out data interaction with machine,
Can be accepted by display, keyboard, mouse or send to equipment control command.(1) it is control command when equipment receives
When, the just communications protocol according to response, control bottom hardware is driven, and operating result is returned to application layer is shown by display
Illustrate.(2) receive when equipment is data management instruction, and the dish battle array just starting response drives, and dish battle array drives further
Call bottom hardware to drive, equally operating result is shown by display.
Equipment control function includes the record startup/stopping of equipment, the startup/stopping of playback, the working method control of equipment
System, the selection control etc. of data input channel.
Its data management function mainly includes the query function to record data, the intercepting of data, the upload/download of data
Function.
In a word, a kind of high-speed data acquisition storage system based on FPGA of the present invention, can pass through EPT from terminal device
Connector sampled echo data, by the transmission of low voltage difference (LVDS) technology high-speed, are transferred to FPGA and carry out at real time data
Reason is analyzed.Data after FPGA process carry out the high speed storing of data via Optical Fiber Transmission to storage array.This design carries
Pass through PCI-E Switch device for interfaces such as mouse, keyboard, gigabit Ethernets, with the interconnection of fpga core board chip, support data
Inquiry with intercepting, recording status monitoring, fileinfo instruction, remote ethernet control function.
Claims (8)
1. the high-speed data acquisition storage system based on FPGA, including data transmission storage hardware system and data transmission are deposited
Storage software systems, it is characterised in that:
Described data transmission storage hardware system, is integrated on a circuit board, comprising: FPGA core core, ETP connector mould
Block, PCI-E switch module, MPU daughter card module, gigabit Ethernet mouth die block, display module, input/output module, MINISAS connect
Mouth die block, SSD storage array module, DDR3 cache module；
Described Gigabit Ethernet module, display module, input/output module, SSD storage array module pass through MPU daughter card module
It is connected with PCI-E switch module respectively, it is achieved the data interaction with FPGA core core；
Described SSD storage array module is connected with FPGA core core by least one-level DDR3 cache module；
Described FPGA core core includes GTP module, for being transmitted data with the form of differential signal；
MINISAS interface module described in 2, carries out data interaction for being directly connected with FPGA core core；
Described MPU daughter card module comprises ETX-Express connector, for the south bridge and north bridge with described MPU subcard
Data are transmitted；
Described SSD storage array module, including at least one external solid-state being made up of Flash flash media and control IC is hard
Dish；
Described data transmission storage software systems, including operating system, management software, MATLAB, communications protocol, dish battle array are driven
Dynamic, bottom hardware drive part, divides in real time for importing, the derivation of data, the analysis of data, maintenance, and simple data
Analysis；User carries out data interaction by input-output equipment and the system application of display module, input/output module.
2. a kind of high-speed data acquisition storage system based on FPGA according to claim 1, is characterized in that: described
FPGA core core uses Xilinx Zynq-7000 chip, and the maximum data rate of the GTP module that it includes is 6.125Gbps.
3. a kind of high-speed data acquisition storage system based on FPGA according to claim 1, is characterized in that: described
ETP connector module, including the EPT103-40064 connector of 2 96 cores；The interface of described EPT103-40064 connector
Including 4 passages, each passage can transmit 4 to LVDS data signal.
4. a kind of high-speed data acquisition storage system based on FPGA according to claim 1, is characterized in that: described
SSD storage array module, including multiple external solid state hard disc, constitutes the electric board battle array of multichannel data memory channel.
5. a kind of high-speed data acquisition storage system based on FPGA according to claim 1, is characterized in that: described
PCI-E module, can configure port containing 15 tunnels.
6. a kind of high-speed data acquisition storage system based on FPGA according to claim 1, is characterized in that: described
Data in FPGA core core, before being stored in storage array, need to carry out procedure below:
(1) phase compensation；
(2) 8b/10b coding；
(3) parallel-to-serial conversion.
7. a kind of high-speed data acquisition storage system based on FPGA according to claim 1, is characterized in that: described
Data in SSD storage array module are being input to before FPGA core core carries out data process, need to carry out procedure below:
(1) recovery of clock；
(2) serial-to-parallel conversion；
(3) byte of sync；
(4) 8b/10b coding；
(5) phase compensation.
8. a kind of high-speed data acquisition storage system based on FPGA according to claim 1, is characterized in that: described base
In the data transmission storage hardware system of FPGA, including the data transmission storage hardware system surface-mounted integrated circuit described in 4 and VPX
Interface；Described VPX interface, for being in communication with each other between described each data transmission storage hardware system surface-mounted integrated circuit
With data interaction.
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106933165A (en) * | 2017-05-05 | 2017-07-07 | 天津市英贝特航天科技有限公司 | Method and equipment for multi-way switching value input and output |
| CN107167773A (en) * | 2017-05-10 | 2017-09-15 | 湖北航天技术研究院总体设计所 | Radar Signal Processing System and Design Internet Applications method based on VPX platforms |
| CN109541994A (en) * | 2018-10-29 | 2019-03-29 | 浙江求是科教设备有限公司 | A kind of real-time acquisition system and its acquisition method of high anti-interference ability |
| CN109581375A (en) * | 2018-12-24 | 2019-04-05 | 中国科学院电子学研究所 | A kind of distributed SAR initial data playback apparatus |
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| CN110209358A (en) * | 2019-06-05 | 2019-09-06 | 哈尔滨工业大学 | A kind of NVMe equipment storage speed method for improving based on FPGA |
| CN110502198A (en) * | 2018-09-29 | 2019-11-26 | 国核自仪系统工程有限公司 | Interface display system based on FPGA |
| CN111708001A (en) * | 2020-06-17 | 2020-09-25 | 桂林理工大学 | Laser radar data acquisition system with remote data transmission function |
| CN113259318A (en) * | 2021-04-12 | 2021-08-13 | 中国科学院上海技术物理研究所 | High-speed data transmission method, system, storage medium, information data processing terminal |
| CN114002602A (en) * | 2021-11-01 | 2022-02-01 | 山东芯慧微电子科技有限公司 | VPX power battery monomer voltage acquisition blade based on FPGA |
| CN114281254A (en) * | 2021-12-16 | 2022-04-05 | 中国兵器装备集团自动化研究所有限公司 | Multi-channel data acquisition and storage system |
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| CN106933165A (en) * | 2017-05-05 | 2017-07-07 | 天津市英贝特航天科技有限公司 | Method and equipment for multi-way switching value input and output |
| CN107167773A (en) * | 2017-05-10 | 2017-09-15 | 湖北航天技术研究院总体设计所 | Radar Signal Processing System and Design Internet Applications method based on VPX platforms |
| CN107167773B (en) * | 2017-05-10 | 2019-10-08 | 湖北航天技术研究院总体设计所 | Radar Signal Processing System and Design Internet Applications method based on VPX platform |
| CN110502198B (en) * | 2018-09-29 | 2023-06-16 | 国核自仪系统工程有限公司 | Interface display system based on FPGA |
| CN110502198A (en) * | 2018-09-29 | 2019-11-26 | 国核自仪系统工程有限公司 | Interface display system based on FPGA |
| CN109541994A (en) * | 2018-10-29 | 2019-03-29 | 浙江求是科教设备有限公司 | A kind of real-time acquisition system and its acquisition method of high anti-interference ability |
| CN109581375A (en) * | 2018-12-24 | 2019-04-05 | 中国科学院电子学研究所 | A kind of distributed SAR initial data playback apparatus |
| CN109581375B (en) * | 2018-12-24 | 2022-08-02 | 中国科学院电子学研究所 | Distributed SAR raw data playback equipment |
| CN110069442A (en) * | 2019-04-24 | 2019-07-30 | 北京计算机技术及应用研究所 | A kind of ultra-high-speed data acquisition device and method based on ZYNQ Series FPGA |
| CN110069442B (en) * | 2019-04-24 | 2022-10-14 | 北京计算机技术及应用研究所 | Ultrahigh-speed data acquisition device and method based on ZYNQ series FPGA |
| CN110209358B (en) * | 2019-06-05 | 2022-07-15 | 哈尔滨工业大学 | NVMe equipment storage speed improving method based on FPGA |
| CN110209358A (en) * | 2019-06-05 | 2019-09-06 | 哈尔滨工业大学 | A kind of NVMe equipment storage speed method for improving based on FPGA |
| CN111708001A (en) * | 2020-06-17 | 2020-09-25 | 桂林理工大学 | Laser radar data acquisition system with remote data transmission function |
| CN113259318A (en) * | 2021-04-12 | 2021-08-13 | 中国科学院上海技术物理研究所 | High-speed data transmission method, system, storage medium, information data processing terminal |
| CN113259318B (en) * | 2021-04-12 | 2023-05-05 | 中国科学院上海技术物理研究所 | High-speed data transmission method, system, storage medium and information data processing terminal |
| CN114002602A (en) * | 2021-11-01 | 2022-02-01 | 山东芯慧微电子科技有限公司 | VPX power battery monomer voltage acquisition blade based on FPGA |
| CN114281254A (en) * | 2021-12-16 | 2022-04-05 | 中国兵器装备集团自动化研究所有限公司 | Multi-channel data acquisition and storage system |
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