TWM596388U - Control system of accessing data for memory cards - Google Patents

Abstract

A control system of accessing data for memory cards is provided. The control system includes a memory card interface, a host system interface, and a control device. When a memory card operates in a first communication protocol, the memory card interface electrically connects to the host system interface via a selector and a bridge device. When a memory card operates in a second communication protocol, the memory card interface electrically connects to the host system interface via the selector, and the memory card interface electrically connects to the host system interface via the bridge device.

Description

Memory card read-write control system

This creation is about an electronic device, especially about a read-write control system of a memory card.

With the rapid development of information technology, the application of electronic products is becoming more and more popular, such as notebook computers, mobile phones, tablet computers and other handheld electronic devices are everywhere. Because the characteristics of these electronic devices are that they can be carried anywhere and used anytime and anywhere, and in order to allow various electronic devices to be connected to each other for a large amount of data transmission, usually a memory card is inserted into the card reader to make the above The electronic product can read and write the data of the memory card to expand the memory storage capacity of the electronic product.

However, as the data access speed of the memory card becomes faster and faster, the memory card of the newer version specification cannot be accessed by the control method of the older version specification, so that the memory card of the newer specification cannot be read in the older version specification. The use in the card machine causes the compatibility problem between the memory card and the control chip of the card reader, and reduces the flexibility of using the memory card. When the memory card of the newer version specification is also accessed by the control method of the newer version specification, the transmission bandwidth of this control method is much larger than that of the older version specification, so that the memory card and the card reader control chip The inter-communication design is relatively complicated, resulting in an increase in the cost of the control chip. In view of this, there is still a need to develop a new type of electronic device to improve the above problems.

One purpose of this creation is to provide a reading and writing control system for memory cards The bridging device and selector of the device enable the host system to read and write data of the memory card through a non-volatile memory shortcut (NVMe) protocol driver, which can solve the problem of memory card and read-write control system. Compatibility issues, and improve the flexibility of memory card use, while reducing the production cost of the read-write control system.

To achieve the above purpose, the read-write control system in one embodiment of the present invention is used for a host system to read and write data of a memory card. The read-write control system includes: a memory card interface for connecting the memory card A host system interface, electrically connected to the memory card interface, and the host system interface connected to the host system; and a control device, electrically connected to the memory card interface and the host system interface, including: a bridge device, electrical Connected to the host system interface and the memory card interface; and a selector to electrically connect the host system interface, the memory card interface and the bridge device; wherein, when the memory card operates with a first communication protocol, the memory The card interface is electrically connected to the host system interface via the selector and the bridge device; wherein, when the memory card operates with a second communication protocol, the memory card interface is electrically connected to the host system interface via the selector Sexual connection, the memory card interface is also electrically connected to the host system interface via the bridge device.

In one embodiment, the control device detects that the memory card is electrically connected to the memory card interface, and presets to connect to the memory card by the first communication protocol, and activates the memory card by the first communication protocol.

In an embodiment, the bridge device includes: a first interface electrically connecting the memory card interface and the host system interface; and a second interface electrically connecting the memory card interface and the selector; wherein, when When the memory card operates with the first communication protocol, the memory card interface is electrically connected to the host system interface through the selector, the second interface, and the first interface, wherein the memory card interface, the second The transmission path between the interface, the first interface and the host system interface is defined as a first transmission The transmission path between the memory card interface, the selector, the second interface, the first interface, and the host system interface is defined as a second transmission path, which allows the host system to pass the first transmission path to Communicate with the memory card interface and read and write the data of the memory card through the second transmission path with the first communication protocol; wherein, when the memory card operates with the second communication protocol, the memory card interface passes the selection The device is electrically connected to the host system interface, and the memory card interface is electrically connected to the host system interface through the first interface of the bridge device, wherein the memory card interface, the selector, and the host system interface The transmission path between is defined as a third transmission path, and the transmission path between the memory card interface, the first interface and the host system interface is defined as a fourth transmission path, so that the host system can communicate with the third transmission path The memory card interface communicates and reads and writes the data of the memory card through the fourth transmission path and the second communication protocol.

In one embodiment, the host system interface includes a first sub-interface and a second sub-interface. The memory card interface is electrically connected to the second sub-interface of the host system interface through the bridge device. The memory card interface is also The first sub-interface of the host system interface is electrically connected through the selector.

In one embodiment, when the memory card operates with the second communication protocol, the second interface triggers the selector with a trigger signal, so that the memory card interface is electrically connected to the host system interface through the selector The first sub-interface, and the memory card interface is electrically connected to the second sub-interface of the host system interface through the first interface.

In one embodiment, the host system communicates with the memory card through the host system interface, the bridge device, and the selector to determine whether the memory card supports the protocol version of the host system. The protocol version includes PCIe1.0, PCIe2.0 and PCIe3.0 protocol versions.

In one embodiment, when the host system confirms that the first communication protocol of the memory card supports the PCIe1.0 protocol version or the PCIe2.0 protocol version of the host system through the host system interface, the host The host system reads and writes the data of the memory card through the host system interface, the first interface, the second interface, and the selector. When the host system confirms the second communication protocol of the memory card via the host system interface Supporting the PCIe3.0 protocol version of the host system, the host system reads and writes the data of the memory card through the host system interface and the first interface of the bridge device.

In one embodiment, the bridge device further includes a non-volatile memory shortcut protocol controller that is electrically connected to the second sub-interface of the host system interface through the first interface, when the memory card does not support the second When the communication protocol is in operation, a non-volatile memory shortcut (NVMe) protocol driver of the host system passes through the host system interface, the first interface, the non-volatile memory shortcut protocol controller, and the second interface to Access the data of the memory card with the non-volatile memory shortcut protocol controller, and when the memory card supports the operation of the second communication protocol, the non-volatile memory shortcut (NVMe) protocol driver of the host system passes through the The host system interface and the first interface access the data of the memory card.

In one embodiment, the second interface is electrically connected to the first interface via the non-volatile memory shortcut protocol controller.

In one embodiment, the first communication protocol of the memory card is defined as a secure digital (SD) mode, and the second communication protocol of the memory card is defined as an SD Express mode.

In one embodiment, the data transmission rate of the first communication protocol of the memory card is less than the data transmission rate of the second communication protocol.

The creation of the read-write control system allows the host system to use only a non-volatile memory shortcut (NVMe) protocol driver through the bridge device and selector of the control device, that is, it can read and write memory cards with different communication protocols. Data, to solve the problem of compatibility between the memory card and the read-write control system, and improve the flexibility of use of the memory card, while reducing the production cost of the read-write control system.

100: memory card

101: Memory card interface

102: Host system interface

102a: the first sub-interface

102b: second sub-interface

103: Host system

106: control device

109: Bridge device

110: the first interface

112: Second interface

112a: Control interface

112b: Transmission interface

114: selector

200: NVMe controller

TS: trigger signal

DAT 0~3: data

P1: First transmission path

P2: Second transmission path

P3: Third transmission path

P4: Fourth transmission path

SD DAT 0~3: Secure digital data

SD CMD: Safe digital instructions

SD CLK: Safe digital clock

TX/RX: data transmission/reception

PERST#: Fast reset signal for interconnection of peripheral components

CLKREQ#: clock request running signal

REFCLK+, REFCLK-: reference clock differential pair signal

In order to more clearly explain the technical solutions in the authored embodiment, the following will briefly introduce the drawings needed in the description of the embodiment. Obviously, the drawings in the following description are only some embodiments of the creation, For those with ordinary knowledge in the technical field to which this creation belongs, other drawings can also be obtained based on these drawings.

FIG. 1 is a block diagram of a read-write control system according to this creative embodiment.

Please refer to the drawings, in which the same component symbols represent the same components or similar components. The principle of the present invention is illustrated by implementation in an appropriate computing environment. The following description is based on the illustrated specific embodiment of the creation, which should not be considered as limiting other specific embodiments of the creation that are not detailed here.

Refer to FIG. 1, which is a block diagram of the read-write control system according to the first embodiment of the present invention. The read-write control system is used for a host system 103 to read and write data of a memory card 100. The read-write control system includes a memory card interface 101, a host system interface 102, and a control device 106.

As shown in FIG. 1, the memory card interface 101 is used to connect to the memory card 100. The host system interface 102 is electrically connected to the memory card interface 101, and the host system 103 is connected to the host system interface 102. The control device 106 includes a bridge device 109 and a selector 114. The bridge device 109 is electrically connected to the host system interface 102 and the memory card interface 101. The selector 114 is electrically connected to the host system interface 102 and the memory card interface 101和该桥接装置109。 And the bridge device 109. When the memory card 100 operates with the first communication protocol, the memory card interface 101 is electrically connected to the host system interface 101 via the selector 114 and the bridge device 109. When the memory card 100 operates with the second communication protocol, the memory card interface 101 The selector 114 is electrically connected to the host system interface 101, and the memory card interface 101 is also electrically connected to the host system interface 102 via the bridge device 109.

As shown in FIG. 1, in an embodiment, the host system 103 detects that the memory card interface 101 is electrically connected to the host system interface 102 via the control device 106, and presets the first communication protocol to the The memory card 100 is connected to initialize or initiate the memory card 100 with the first communication protocol. The initialization is, for example, the host system interface 102 provides power required for operation of the memory card 100, the host system interface 102 transmits operation and access commands to the memory card 100, and the host system is established through the memory card interface 101 The interface 102 communicates with the memory card 100 in two ways.

As shown in FIG. 1, in an embodiment, the bridge device 109 includes a first interface 110 and a second interface 112. The first interface 110 is electrically connected to the memory card interface 101 and the host system interface 102, and the second interface 112 is electrically connected to the memory card interface 101 and the selector 114. In an embodiment, the first interface 110 is, for example, a control interface or a controller. The second interface 112 is, for example, a control interface or a controller.

As shown in FIG. 1, in an embodiment, when the memory card 100 operates with the first communication protocol, and the first communication protocol of the memory card 100 is, for example, a secure digital (SD) mode, the memory card The interface 101 is electrically connected to the host system interface 102 via the selector 114, the second interface 112 and the first interface 110, wherein the memory card interface 101, the second interface 112, the first interface 110 and The transmission path between the host system interface 102 is defined as the first transmission path P1, the transmission path between the memory card interface 101, the selector 114, the second interface 112, the first interface 110, and the host system interface 102 Defined as a second transmission path P2, the host system 103 communicates with the memory card interface 101 through the first transmission path P1 and reads and writes the memory card 100 through the second transmission path P2 with the first communication protocol data. In one embodiment, the host system 103 passes the first host system interface 102 via the first The transmission path P1 detects that the memory card interface 101 is electrically connected to the host system interface 102. The host system 103 initializes the memory card 100 with the first communication protocol through the first transmission path P1 through the host system interface 102. In a preferred embodiment, during the detection of the connection of the memory card 100, the host system 103, for example, through the host system interface 102 and the first interface 110 of the bridge device 109, the non-volatile memory shortcut ( The NVMe) controller 200 and the second interface 112 initialize or activate the memory card 100 with the first communication protocol.

As shown in FIG. 1, in an embodiment, when the memory card 100 operates with the second communication protocol, for example, when the second communication protocol of the memory card 100 is in the SD Express mode, the memory The card interface 101 is electrically connected to the host system interface 102 via the selector 114, and the memory card interface 102 is electrically connected to the host system interface 102 via the first interface 110 of the bridge device 109, wherein the The transmission path between the memory card interface 101, the selector 114, and the host system interface 102 is defined as a third transmission path P3, and the transmission path between the memory card interface 101, the first interface 110, and the host system interface 102 is defined as A fourth transmission path P4 enables the host system 103 to communicate with the memory card interface 101 through the third transmission path P3 and read and write the data of the memory card 100 through the fourth transmission path P4 with the second communication protocol . After determining that the memory card 100 supports the operation of the second communication protocol, for example, the embodiment will first initialize or activate the memory card 100 with the second communication protocol for subsequent communication or reading Write homework.

As shown in FIG. 1, in one embodiment, the memory card interface 101 conforms to a secure digital memory card protocol, such as SD-UHS I, SD-UHS II, SD-UHS III, SD 7.0, etc. Agreement version, but not limited to this. In one embodiment, the first communication protocol of the memory card 100 is defined as a secure digital (SD) mode, such as SD-UHS I, SD-UHS II, and SD-UHS III protocol versions. The second communication protocol of the memory card 100 is defined as an SD Express mode. Cain The all-digital mode is a protocol version prior to the quick-safe digital mode. The quick-safe digital mode is the secure digital (SD) 7.0 protocol version, for example, it supports the secure digital (SD) 7.0 protocol version or a later updated protocol version. The data transmission rate of the first communication protocol of the memory card 100 is less than the data transmission rate of the second communication protocol. The host system interface 102 is, for example, a peripheral component interconnect express (PCIe) root complex component, which is used to connect the processor and the memory to a PCIe switching architecture composed of one or more switching devices, which can be set It is used in notebook computers, mobile phones, tablets, or other electronic devices with processors connected to memory. The control device 106 is, for example, a control chip of a card reader or a control circuit, but it is not limited thereto.

As shown in FIG. 1, in an embodiment, the host system interface 102 includes a first sub-interface 102a and a second sub-interface 102b. For example, the first sub-interface 102a includes a shortcut peripheral component interconnect reset (PCI Express Reset, PERST#) signal, a clock request run signal (clock request, CLKREQ#), and a reference clock differential pair signal (reference clock, REFCLK+ , REFCLK-), where the fast peripheral component interconnect reset (PERST#) signal is used to manage the reset operation of the second sub-interface 102b; the clock request operation signal (clock request, CLKREQ#) is used to request the reference clock operation; The reference clock differential pair signals (reference clock, REFCLK+, REFCLK-) are used to provide the reference clock. The first sub-interface 102a is electrically connected to the first interface 110 of the bridge device 109 and the selector 114 to transmit the above four signals, including PERST#, CLKREQ#, REFCLK+, and REFCLK-4 signals. The second sub-interface 102b is used to perform data transmission/reception (TX/RX) between the host system interface 102 and the memory card interface 101. The second sub-interface 102b supports PCIe1.0, PCIe2.0 and PCIe3.0 protocol versions. For example, the transmission bandwidth of PCIe 1.0 is 2.5 GHz, the transmission bandwidth of PCIe 2.0 is 5.0 GHz, and the transmission bandwidth of PCIe 3.0 is 8.0 GHz. In an embodiment, the memory card interface 101 is electrically connected to the second sub-interface 102b of the host system interface 102 through the bridge device 109, the memory card The interface 101 is also electrically connected to the first sub-interface 102a of the host system interface 102 through the selector 114.

As shown in FIG. 1, in one embodiment, when the memory card 100 operates with the second communication protocol, the second interface 112 triggers the selector 114 with a trigger signal TS to allow the memory card interface 101 The selector 114 is electrically connected to the first sub-interface 102a of the host system interface 102, and the memory card interface 101 is electrically connected to the second sub-interface 102b of the host system interface 102 through the first interface 110.

As shown in FIG. 1, in an embodiment, the host system 103 communicates with the memory card 100 through the host system interface 102, the bridge device 109, and the selector 114 to determine whether the memory card 100 supports the host The protocol version of the system 103, which includes PCIe 1.0, PCIe 2.0, and PCIe 3.0 protocol versions. When the host system 103 confirms through the host system interface 102 that the first communication protocol of the memory card 100 supports the PCIe 1.0 protocol version or the PCIe 2.0 protocol version of the host system 103, the host system 103 passes the host system interface 102, the first interface 110, the second interface 112, and the selector 114 to read and write the data of the memory card 100, when the host system 103 confirms the second communication of the memory card 100 via the host system interface 102 The protocol supports the PCIe3.0 protocol version of the host system 103. The host system 103 reads and writes the data of the memory card 100 through the host system interface 102 and the first interface 110 of the bridge device 109.

As shown in FIG. 1, in an embodiment, the second interface 112 of the bridge device 109 includes a control interface 112a and a transmission and reception interface 112b, the control interface 112a is connected to the memory card interface 101, and the transmission and reception interface 112b is connected to the The selector 114, the second interface 112 is used for the operation of the control interface 112a and the transmission interface 112b. The control interface 112a includes signals such as a secure digital command (SD CMD) and a secure digital clock (SD CLK) to establish a communication link between the second interface 112 and the memory card interface 101. The transmission and reception interface 112b includes secure digital data (secure digital data (SD DAT), for example, SD DAT 0~3, which includes 4 bits for transmitting and receiving data between the second interface 112 and the memory card interface 101. The control interface 112a and the transmission interface 112b of the second interface 112 are respectively used to convert the communication and data transmission format between the first sub-interface 102a and the second sub-interface 102b of the host system interface 102 and the first communication protocol . In an embodiment, the selector 114 is, for example, a multiplexer, but it is not limited thereto, such as a selector composed of circuit elements or logic elements. In one embodiment, the second interface 112 is, for example, the main controller of the SD-UHS I. In an embodiment, the first interface 110 is used to switch between the first communication protocol and the second communication protocol, or the first interface 110 passes the first sub-interface 102a and the second sub-interface of the host system interface 102 The interface 102b receives commands for switching between the first communication protocol and the second communication protocol.

As shown in FIG. 1, in an embodiment, the bridge device 109 further includes an NVMe controller 200 that is electrically connected to the second sub-interface 102b of the host system interface 102 through the first interface 110 when the memory card When 100 does not support the operation of the second communication protocol, a non-volatile memory shortcut (NVMe) protocol driver of the host system 103 passes through the host system interface 102, the first interface 110, the NVMe controller 200, the The second interface 112 and the selector 114 use the NVMe controller 200 to access the data of the memory card 100. When the memory card 100 supports the operation of the second communication protocol, the non-volatile memory of the host system 103 The NVMe protocol driver accesses the data of the memory card 100 through the host system interface 102 and the first interface 110.

According to the above, the creation of the read-write control system, through the bridging device 109 and the selector 114 of the control device 106, allows the host system 103 to support different through a non-volatile memory shortcut (NVMe) protocol driver The communication protocol reads and writes the data of the memory card 100, solves the compatibility problem between the memory card 100 and the read-write control system, and improves the flexibility of use of the memory card 100, while reducing the production cost of the read-write control system.

To sum up, the creation of the read-write control system, through the control module and selector of the control device, allows the host system to read and write the data of the memory card through a single interface, which can solve the memory card through different communication protocols. The problem of compatibility with the read-write control system, and improve the use flexibility of the memory card, while reducing the production cost of the read-write control system.

Although this creation has been disclosed as above with the preferred embodiments, it is not intended to limit this creation. Those with ordinary knowledge in the technical field to which this creation belongs can make various modifications and changes without departing from the spirit and scope of this creation. Retouching, therefore the scope of protection of this creation shall be subject to the scope defined in the attached patent application.

100: memory card

101: Memory card interface

102: Host system interface

102a: the first sub-interface

102b: second sub-interface

103: Host system

106: control device

109: Bridge device

110: the first interface

112: Second interface

112a: Control interface

112b: Transmission interface

114: selector

200: NVMe controller

TS: trigger signal

DAT 0~3: data

P1: First transmission path

P2: Second transmission path

P3: Third transmission path

P4: Fourth transmission path

SD DAT 0~3: Secure digital data

SD CMD: Safe digital instructions

SD CLK: Safe digital clock

TX/RX: data transmission/reception

PERST#: Fast reset signal for interconnection of peripheral components

CLKREQ#: clock request running signal

REFCLK+, REFCLK-: reference clock differential pair signal

Claims (11)

A read-write control system for a host system to read and write data of a memory card. The read-write control system includes: A memory card interface for connecting the memory card; A host system interface electrically connected to the memory card interface, and the host system interface connected to the host system; and A control device, electrically connected to the memory card interface and the host system interface, including: A bridge device electrically connected to the host system interface and the memory card interface; and A selector, electrically connected to the host system interface, the memory card interface and the bridge device; Wherein, when the memory card operates with a first communication protocol, the memory card interface is electrically connected to the host system interface via the selector and the bridge device; Wherein, when the memory card operates with a second communication protocol, the memory card interface is electrically connected to the host system interface through the selector, and the memory card interface is also electrically connected to the host system interface through the bridge device connection. The read-write control system as described in item 1 of the patent application scope, wherein the control device detects that the memory card is electrically connected to the memory card interface and presets to connect to the memory card by the first communication protocol. A communication protocol activates the memory card. The read-write control system as described in item 1 of the patent application scope, wherein the bridge device includes: A first interface electrically connected to the memory card interface and the host system interface; and A second interface, electrically connected to the memory card interface and the selector; Wherein, when the memory card operates with the first communication protocol, the memory card interface is electrically connected to the host system interface through the selector, the second interface, and the first interface, wherein the memory card interface, The transmission path between the second interface, the first interface and the host system interface is defined as a first transmission path, the memory card interface, the selector, the second interface, the first interface, and the host system interface The transmission path between is defined as a second transmission path, so that the host system communicates with the memory card interface through the first transmission path and reads and writes the data of the memory card through the second transmission path with the first communication protocol ; Wherein, when the memory card operates with the second communication protocol, the memory card interface is electrically connected to the host system interface through the selector, and the memory card interface passes through the first interface of the bridge device to communicate with The host system interface is electrically connected, wherein the transmission path between the memory card interface, the selector, and the host system interface is defined as a third transmission path, and the communication path between the memory card interface, the first interface, and the host system interface The transmission path is defined as a fourth transmission path, so that the host system communicates with the memory card interface through the third transmission path and reads and writes the data of the memory card through the fourth transmission path and the second communication protocol. The read-write control system as described in item 3 of the patent scope, wherein the host system interface includes a first sub-interface and a second sub-interface, and the memory card interface is electrically connected to the host system interface through the bridge device The second sub-interface, the memory card interface is also electrically connected to the first sub-interface of the host system interface through the selector. The read-write control system as described in item 4 of the patent application scope, wherein when the memory card operates with the second communication protocol, the second interface triggers the selector with a trigger signal to allow the memory card interface to pass through the The selector is electrically connected to the first sub-interface of the host system interface, and the memory card interface is electrically connected to the second sub-interface of the host system interface through the first interface. The read-write control system as described in item 4 of the patent application scope, wherein the host system communicates with the memory card through the host system interface, the bridge device, and the selector to determine whether the memory card supports the protocol of the host system Version, the protocol version includes PCIe1.0, PCIe2.0 and PCIe3.0 protocol versions. The read-write control system as described in item 6 of the patent application scope, wherein when the host system confirms via the host system interface that the first communication protocol of the memory card supports the PCIe1.0 protocol version or PCIe2.0 of the host system Protocol version, the host system reads and writes the data of the memory card through the host system interface, the first interface, the second interface, and the selector, when the host system confirms the memory card's data through the host system interface The second communication protocol supports the PCIe3.0 protocol version of the host system. The host system reads and writes the data of the memory card through the host system interface and the first interface of the bridge device. The read-write control system as described in item 4 of the patent application scope, wherein the bridge device further includes a non-volatile memory shortcut protocol controller, which is electrically connected to the second sub-interface of the host system interface through the first interface When the memory card does not support the operation of the second communication protocol, a non-volatile memory shortcut (NVMe) protocol driver of the host system passes the host system interface, the first interface, and the non-volatile memory shortcut The protocol controller, the second interface, and the selector access the data of the memory card with the non-volatile memory shortcut protocol controller. When the memory card supports the operation of the second communication protocol, the non-volatile memory of the host system The volatile memory shortcut (NVMe) protocol driver accesses the data of the memory card through the host system interface and the first interface. The read-write control system as described in item 8 of the patent application scope, wherein the second interface is electrically connected to the first interface via the non-volatile memory shortcut protocol controller. The read-write control system as described in item 1 of the patent application scope, wherein the first communication protocol of the memory card is defined as a secure digital (SD) mode, and the second communication protocol of the memory card is defined as a fast and secure digital (SD) Express) mode. The read-write control system as described in item 1 of the patent application scope, wherein the data transmission rate of the first communication protocol of the memory card is less than the data transmission rate of the second communication protocol.

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