CN116795758A - Multichannel synchronous Biss-C protocol decoding transmission device based on FPGA - Google Patents
Multichannel synchronous Biss-C protocol decoding transmission device based on FPGA Download PDFInfo
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- CN116795758A CN116795758A CN202310605289.9A CN202310605289A CN116795758A CN 116795758 A CN116795758 A CN 116795758A CN 202310605289 A CN202310605289 A CN 202310605289A CN 116795758 A CN116795758 A CN 116795758A
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/396—Clock trees
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
Abstract
The invention relates to a multi-channel synchronous Biss-C protocol decoding and transmitting device based on an FPGA, which comprises a decoding module, a control module and a transmitting module; the decoding module comprises a receiving detection unit, a clock frequency division unit, a data reading unit and a verification unit; the receiving detection unit receives the reading control signal and drives the clock frequency division unit to generate an MA clock signal; the data reading unit reads data; the checking unit performs CRC check on the data and sends the data and the check result to the control module; the control module comprises a decoding control unit and a data output unit; the decoding control unit detects the reading states of a plurality of decoding modules, and outputs a reading control signal to the receiving detection unit when all the decoding modules are confirmed to be ready; the data output unit packages the verified data and the verification result into an initial data packet and sends the initial data packet to the transmission module; and the transmission module processes the initial data packet into a final data packet and sends the final data packet to the upper computer.
Description
Technical Field
The invention relates to the field of serial port communication, in particular to a multichannel synchronous Biss-C protocol decoding and transmitting device based on an FPGA.
Background
The Biss-C protocol is a fast synchronous serial interface comprising two sets of unidirectional differential lines, a set of MA clocks, and a set of SLO data. The Biss-C is a special data transmission protocol, is a data format for data exchange between an absolute encoder and an external system, and the Biss-C mode is a fast synchronous serial interface for the encoder to collect position data, and is a master-slave interface. The master interface controls the position acquisition time sequence and the data transmission speed, the encoder is a slave interface, and the interfaces are connected by two pairs of unidirectional differential lines. The Biss-C protocol uses RS422 level standard, +2V— +6V represents 1, -2V— -6V represents 0, more than +200mV represents 1 between the receiving terminals AB, and less than-200 mV represents 0 between the receiving terminals AB.
Referring to fig. 1, fig. 1 is a schematic diagram of a structure of a data frame of a bss-C protocol. In the figure, MA is a clock bus, defaults to high level, and when the FPGA needs to read data, MA clock signals are output externally. The SLO is a data output bus of the Biss-C device, when the MA bus starts to output a clock signal, the Biss-C device does not respond in the first clock period, the Biss-C sove device pulls down the SLO data bus at the rising edge of the second clock period, and enters an ACK (data preparation) state, and when the internal data processing of the Biss-C sove device is finished and can be output, the SLO is pulled up to enter a Start (ready) state, which indicates that the data can be transmitted. The SLO starts to transmit data after maintaining a high level of one clock, and the SLO's data changes at the rising edge of each clock. The first data bit is CDS (control data bit), then outputs each bit of data from high to low, outputs Error and Warning bits after data output is completed, and then outputs each bit of CRC check result from high to low. After the data output is completed, the Biss-C wave device enters into a Biss-Timeout state, the SLO level is lowered, and during the period, the FPGA cannot read the data in the Biss-C wave device. After maintaining the SLO low for a certain period of time, the Biss-C device pulls the SLO high, indicating that the next data transfer can begin.
An FPGA (Field Programmable Gate Array ) is an integrated circuit with programmable features that is pre-designed and implemented on a silicon chip that can be configured into a specified circuit configuration according to the needs of the designer.
The traditional Biss-C protocol decoding chip cannot flexibly support multi-path Biss-C protocol decoding, and when a plurality of Biss-C devices are supported, specially designed hardware is needed to meet the requirements.
Disclosure of Invention
Accordingly, an object of the present invention is to provide an FPGA-based multi-channel synchronous Biss-C protocol decoding and transmitting device that can flexibly support multi-channel Biss-C protocol decoding and can detect clock synchronicity of the multi-channel decoding.
A multipath synchronous Biss-C protocol decoding and transmitting device based on an FPGA comprises a decoding module, a control module and a transmitting module;
the decoding module comprises a receiving detection unit, a clock frequency division unit, a data reading unit and a verification unit;
the receiving detection unit receives the read control signal, detects the state of the SLO bus of the Biss-C equipment when the receiving detection unit receives the read control signal, and continuously waits for one internal clock period of the FPGA when detecting that the SLO bus is at a low level until the level state of the SLO bus is at a high level, and drives the clock frequency division unit to generate an MA clock signal;
the clock frequency dividing unit divides the frequency of the internal clock signal of the FPGA according to the content of the read control signal to generate an MA clock signal;
the data reading unit is used for reading bit data output by the Biss-C device at the falling edge of each MA clock signal from the next MA clock period when the receiving and detecting unit receives a reading control signal and the Biss-C device is in a Start state;
the checking unit is used for detecting and CRC checking Error bits and Warning bits of the data after the data reading unit finishes reading the data, and sending the checked data and checking results to the data output unit of the control module;
the control module comprises a decoding control unit and a data output unit;
the decoding control unit detects the reading states of a plurality of decoding modules, and when the fact that the data reading units of all the decoding modules are not in the reading states and all the Biss-C devices are not in the Biss-Timeout states is confirmed, the decoding control unit outputs reading control signals to the receiving detection units of the plurality of decoding modules at the same time;
the data output unit packages the verified data and the verification result into an initial data packet and sends the initial data packet to the transmission module;
and the transmission module processes the initial data packet into a final data packet and sends the final data packet to the upper computer.
The multi-channel synchronous Biss-C protocol decoding transmission device based on the FPGA can flexibly connect multi-channel Biss-C equipment through the copy decoding module to carry out multi-channel synchronous Biss-C protocol decoding.
Further, the decoding module further comprises a synchronization reading unit; the control module further comprises a synchronous detection unit;
the synchronous reading unit is used for reading the reading state data of the Biss-C device from the next MA clock period at the falling edge of each MA clock signal when the receiving and detecting unit receives the reading control signal and the Biss-C device is in the Start state; the reading state data is a natural number and represents the stage of the data output period of the Biss-C equipment;
the synchronous detection unit detects the read state data of the plurality of decoding modules in each MA clock period after the data reading unit starts to read the data; calculating the range of a plurality of pieces of read state data, and taking the maximum value of the range as clock synchronism information;
the data output unit packages the verified data, the verification result and the clock synchronism information into an initial data packet and sends the initial data packet to the transmission module;
because the read state data is located at a certain stage of a data output period corresponding to the Biss-C device, and the time length of each stage is the clock signal period of the Biss-C device, the extremely poor maximum value of the read state data can directly reflect the synchronism of the output data of a plurality of Biss-C devices; the larger the maximum value of the range of the read state data is, the poorer the synchronism of the output data of the plurality of Biss-C devices is.
Further, the synchronization detection unit further comprises a synchronization status register; the synchronization detection unit detects the read state data of the plurality of decoding modules every MA clock period after the data reading unit starts to read the data, calculates the range of the read state data, compares the calculated range with the value in the synchronization state register, and replaces the value in the synchronization state register with the calculated range when the calculated range is larger than the value in the synchronization state register, otherwise does not update the value in the synchronization state register.
Further, the transmission module adds a time stamp, a version number and a reserved byte to the packet header of the initial data packet, performs CRC check on the time stamp, the version number, the reserved byte and the initial data packet together, adds a check result to the packet tail, and packages the data into a final data packet comprising the time stamp, the version number, the reserved byte, the initial data packet and the CRC check result.
Further, the transmission module sends the final data packet to the upper computer through an SPI protocol.
Further, the decoding module is connected to a Biss-C device through an RS422 level conversion chip; the paths of the IO ports of the decoding modules connected to the corresponding RS422 level conversion chips are equal in length; the paths of the RS422 level conversion chip connected to the corresponding Biss-C device are equal in length.
For a better understanding and implementation, the present invention is described in detail below with reference to the drawings.
Drawings
FIG. 1 is a diagram of a structure of a Biss-C protocol data frame;
fig. 2 is a schematic diagram of a multi-channel synchronous Biss-C protocol decoding and transmitting device based on an FPGA according to an embodiment of the present invention.
Detailed Description
Referring to fig. 2, fig. 2 is a schematic diagram of a multi-channel synchronous Biss-C protocol decoding and transmitting device based on an FPGA according to an embodiment of the invention. The invention discloses a multipath synchronous Biss-C protocol decoding and transmitting device based on an FPGA, which comprises a decoding module, a control module and a transmitting module. One or more decoding modules can be provided, in this embodiment, the number of the decoding modules is multiple, and the decoding modules respectively decode information sent by different Biss-C devices; the control module controls the working process of the decoding modules; and the transmission module transmits the decoded data packet to the upper computer through an SPI protocol.
Specifically, the decoding module comprises a receiving detection unit, a clock frequency division unit, a data reading unit, a synchronism reading unit and a verification unit.
The reception detection unit includes an external control register and a data ready state register. The receiving detection unit receives a reading control signal sent by the control module and writes the content of the reading control signal into an external control register; and when the receiving detection unit receives the reading control signal, detecting the state of the SLO bus of the Biss-C device, and when the SLO bus is detected to be low, continuing to wait for one FPGA internal clock period until the level state of the SLO bus is high, writing the data reading ready state information into a data ready state register by the receiving detection unit, and driving the clock frequency dividing unit to generate an MA clock signal.
The clock frequency dividing unit performs frequency division by 8, 16, 32, 64 or 128 on the internal clock signal of the FPGA according to the content in the external control register to generate the MA clock signal.
The data reading unit includes a shift data register. When the receiving detection unit receives a reading control signal and the Biss-C device is in a Start state, the data reading unit reads bit data output by the Biss-C device at the falling edge of each MA clock signal from the next MA clock period, and writes the read data into the shift data register.
The synchronous read unit includes a read status register. The synchronous reading unit writes the read state data into the read state register at the falling edge of each MA clock signal from the next MA clock period when the receiving detection unit receives the read control signal and the Biss-C device is in the Start state. The read status data is a natural number, and corresponds to the stage of the data output period of the Biss-C device: for example, when the SLO bus of the Biss-C device is in a stage of outputting the "ack=0" signal, the read status data is 0; when the SLO bus of the Biss-C device is in a stage of outputting a "start=1" signal, the read status data is 1; when the SLO bus of the Biss-C device is in a stage of outputting the CDS signal, the read status data is 2; when the SLO bus of the Biss-C device is in a stage of outputting n-1 bit data, the read state data is 3; when the SLO bus of the Biss-C device is in the phase of outputting bit 0 data, the read status data is n+2, and so on.
The verification unit includes a data output register and a data correct status register. After the data reading unit finishes reading data and the Biss-C device enters into a Biss-Timeout state, the checking unit detects and CRC checks Error bits and Warning bits of data in the shift data register, then writes the checked data into the data output register, and writes a checking result into the data correct state register.
Specifically, the control module comprises a decoding control unit, a synchronous detection unit and a data output unit. In this embodiment, the control module controls a plurality of decoding modules to simultaneously decode data transmitted by a plurality of Biss-C devices.
The decoding control unit detects the read status registers and the data ready status registers of the plurality of decoding modules, and when it is confirmed that all decoding modules are ready (the data read unit is not in the read state and the Biss-C device is not in the Biss-Timeout state), the decoding control unit outputs the read control signal to the reception detection units of the plurality of decoding modules at the same time.
The synchronization detection unit comprises a synchronization status register; the synchronous detection unit detects a read state register in each MA clock period after the data reading unit starts to read data to obtain read state data of a plurality of decoding modules; calculating the range of the plurality of read state data, comparing the calculated range with the value in the synchronous state register, and replacing the value in the synchronous state register with the calculated range when the calculated range is larger than the value in the synchronous state register, otherwise, not updating the value in the synchronous state register. The synchronous state register stores clock synchronism information; the clock synchronicity information refers to the maximum value of the read state data of the plurality of decoding modules. The reading state data represent the stages of a data output period of the Biss-C device, and the duration of each stage is the MA clock signal period of the Biss-C device, so that the extremely poor maximum value of the reading state data can directly reflect the synchronism of the output data of a plurality of Biss-C devices; the greater the maximum value of the range of the read status data, the poorer the synchronicity of the output data of the plurality of Biss-C devices.
The data output unit comprises a data register and a data state register; the data output unit detects a data output register of the decoding module after the data reading unit finishes data reading, and writes data in the data output register into the data register; detecting a data correct state register of the decoding module, and writing data in the data correct state register into the data state register; and then, packaging the data in the data register, the data state register and the synchronous state register into an initial data packet, and sending the initial data packet to the transmission module.
Specifically, the transmission module receives an initial data packet sent by a data output unit of the control module, and adds a time stamp, a version number and a reserved byte in a packet header; the transmission module performs CRC check on the time stamp, the version number, the reserved bytes and the initial data packet together, adds the check result to the packet tail, and packages the data into a final data packet comprising the time stamp, the version number, the reserved bytes, the initial data packet and the CRC check result. And the transmission module sends the final data packet to the upper computer through an SPI protocol.
Further, the decoding module is connected to a Biss-C device through an RS422 level conversion chip; the paths of the IO ports of the decoding modules connected to the corresponding RS422 level conversion chips are equal in length; the paths of the RS422 level conversion chip connected to the corresponding Biss-C device are equal in length. The circuit equal length processing is to ensure the synchronism of the multi-path decoding.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that modifications and improvements can be made by those skilled in the art without departing from the spirit of the invention, and the invention is intended to encompass such modifications and improvements.
Claims (6)
1. A multipath synchronous Biss-C protocol decoding and transmitting device based on an FPGA comprises a decoding module, a control module and a transmitting module;
the decoding module comprises a receiving detection unit, a clock frequency division unit, a data reading unit and a verification unit;
the receiving detection unit receives the read control signal, detects the state of the SLO bus of the Biss-C equipment when the receiving detection unit receives the read control signal, and continuously waits for one internal clock period of the FPGA when detecting that the SLO bus is at a low level until the level state of the SLO bus is at a high level, and drives the clock frequency division unit to generate an MA clock signal;
the clock frequency dividing unit divides the frequency of the internal clock signal of the FPGA according to the content of the read control signal to generate an MA clock signal;
the data reading unit is used for reading bit data output by the Biss-C device at the falling edge of each MA clock signal from the next MA clock period when the receiving and detecting unit receives the reading control signal and the Biss-C device is in the Start state;
the checking unit is used for detecting and CRC checking Error bits and Warning bits of the data after the data reading unit finishes reading the data, and sending the checked data and checking results to the data output unit of the control module;
the control module comprises a decoding control unit and a data output unit;
the decoding control unit detects the reading states of a plurality of decoding modules, and when the fact that the data reading units of all the decoding modules are not in the reading states and all the Biss-C devices are not in the Biss-Timeout states is confirmed, the decoding control unit outputs reading control signals to the receiving detection units of the plurality of decoding modules at the same time;
the data output unit packages the verified data and the verification result into an initial data packet and sends the initial data packet to the transmission module;
and the transmission module processes the initial data packet into a final data packet and sends the final data packet to the upper computer.
2. The FPGA-based multi-channel synchronous Biss-C protocol decoding and transmitting device of claim 1, wherein: the decoding module further comprises a synchronous reading unit; the control module further comprises a synchronous detection unit;
the synchronous reading unit is used for reading the reading state data of the Biss-C device from the next MA clock period and at the falling edge of each MA clock signal when the receiving and detecting unit receives the reading control signal and the Biss-C device is in the Start state; the reading state data is a natural number and represents the stage of the data output period of the Biss-C equipment;
the synchronous detection unit detects the read state data of the plurality of decoding modules in each MA clock period after the data reading unit starts to read the data; calculating the range of a plurality of pieces of read state data, and taking the maximum value of the range as clock synchronism information;
and the data output unit packages the verified data, the verification result and the clock synchronism information into an initial data packet and sends the initial data packet to the transmission module.
3. The FPGA-based multi-channel synchronous Biss-C protocol decoding and transmitting device of claim 2, wherein: the synchronization detection unit further comprises a synchronization status register; the synchronization detection unit detects the read state data of the plurality of decoding modules every MA clock period after the data reading unit starts to read the data, calculates the range of the read state data, compares the calculated range with the value in the synchronization state register, and replaces the value in the synchronization state register with the calculated range when the calculated range is larger than the value in the synchronization state register, otherwise does not update the value in the synchronization state register.
4. The FPGA-based multi-channel synchronous Biss-C protocol decoding and transmitting device of claim 3, wherein: the transmission module adds a time stamp, a version number and reserved bytes in the packet head of the initial data packet, performs CRC check on the time stamp, the version number, the reserved bytes and the initial data packet together, adds a check result to the packet tail, and packages the data into a final data packet comprising the time stamp, the version number, the reserved bytes, the initial data packet and the CRC check result.
5. The FPGA-based multi-channel synchronous Biss-C protocol decoding and transmitting device of claim 4, wherein: and the transmission module sends the final data packet to the upper computer through an SPI protocol.
6. The FPGA-based multi-channel synchronous Biss-C protocol decoding and transmitting device of claim 5, wherein: the decoding module is connected to the Biss-C equipment through an RS422 level conversion chip; the paths of the IO ports of the decoding modules connected to the corresponding RS422 level conversion chips are equal in length; the paths of the RS422 level conversion chip connected to the corresponding Biss-C device are equal in length.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117749912B (en) * | 2024-02-19 | 2024-05-10 | 浙江双元科技股份有限公司 | Data transmission control method and system based on FPGA module |
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| CN117749912B (en) * | 2024-02-19 | 2024-05-10 | 浙江双元科技股份有限公司 | Data transmission control method and system based on FPGA module |
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