CN106711306A - Method for preparing high-voltage LED chips - Google Patents
Method for preparing high-voltage LED chips Download PDFInfo
- Publication number
- CN106711306A CN106711306A CN201611187170.0A CN201611187170A CN106711306A CN 106711306 A CN106711306 A CN 106711306A CN 201611187170 A CN201611187170 A CN 201611187170A CN 106711306 A CN106711306 A CN 106711306A
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- Prior art keywords
- sio
- sio2
- etching
- voltage led
- pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0025—Processes relating to coatings
Abstract
The invention provides a method for preparing high-voltage LED chips, comprising the following steps: (1) selecting and using a sapphire substrate to grow a GaN epitaxy, and depositing a P-SiO2 film after Mesa etching and gallium nitride deep etching (ISO), wherein the thickness of the P-SiO2 film is from 100nm to 1 micron; (2) carrying out layout design on the substrate prepared in the previous step, and during layout design, on the basis of P-SiO2 prepared through six photo-etching methods, retaining P-SiO2 at all etching slopes; (3) after P-SiO2 photo-etching, removing non-retained P-SiO2 through wet etching; (4) after P-SiO2 is finished, continuing subsequent ITO and PN- Pad processes; and (5) after the PN- Pad process, annealing products for 10min at 250 DEG C and in a nitrogen protective atmosphere, and spot-testing and judging the products based on photoelectric parameters. As P-SiO2 protects etching slopes and there is no SiO2 passivation process, corrosion caused by halogen elements to PN-Pad metal pads during dry-etching of passivated SiO2 is avoided, and the use reliability of high-voltage LED chip products is ensured.
Description
Technical field
The present invention relates to high voltage LED chip design field, specially a kind of high voltage LED chip preparation method.
Background technology
High voltage LED chip is by chip level, the individual dice of two and the above being carried out into circuit connected in series, so that core
Piece voltage when in use increases (an individual dice voltage * series connection number).High voltage LED chip key technology includes：Gallium nitride depth
Etching (ISO) technique, P-SiO2Current barrier layer (CBL) technique and metallic bone technique.Gallium nitride deep etching (ISO) technique master
It is so that between the tube core of series connection and is isolated, forms individual dice.Current barrier layer (CBL) technique can in high-voltage chip
Play the effect for preventing subsequent metal lap joint process from causing tube core short circuit.Metallic bone technique causes that deep etching (ISO) is formed afterwards
Individual dice carry out circuit connected in series, so as to form high-voltage chip.
The method that current preparation method is mainly 6 road photoetching from from the point of view of photoetching, i.e.,：MESA photoetching → deep etching
(ISO) photoetching → P-SiO2 photoetching → ITO photoetching → PN-Pad photoetching → passivation SiO2 photoetching.Last one of the preparation method
After passivation SiO2 photoetching, the passivation SiO2 on PN-Pad metal pads is typically removed with the method for ICP dry etchings, due to ICP dry etchings
When PN-Pad metal pads be not fee from the halogen (such as F, Cl) that can be touched in etching cavity, post-etch residue, absorption
Different degrees of corrosion can be produced to PN-Pad metal pads, influence whether that product makes when serious in the halogen of chip surface
Reliability.
Passivation SiO2It is main in LED product to play protection chip surface, domatic (the exposed amount after especially MESA is etched
Sub- trap side), equally played a role for high-voltage product, it is domatic (exposed SQW side) and deep after being etched for MESA
Slope protection after etching (ISO) is particularly important for electrical parameter (Vf4) in high-voltage product.
The content of the invention
Technical problem solved by the invention is to provide a kind of high voltage LED chip preparation method, to solve above-mentioned background
Problem in technology.
Technical problem solved by the invention is realized using following technical scheme：A kind of high voltage LED chip preparation method,
Its preparation method from the method that photoetching knot angle is 5 road photoetching, i.e.,：MESA photoetching → deep etching (ISO) photoetching → P-SiO2 light
Quarter → ITO photoetching → PN-Pad photoetching.Comprise the following steps：
(1) GaN epitaxy is grown from Sapphire Substrate, is deposited after Mesa etchings, gallium nitride deep etching (ISO) is completed
P-SiO2Film, P-SiO2The thickness of deposition is 100nm-1um；
(2) layout design is carried out on substrate prepared by previous step, in the P-SiO of 6 road photolithography methods during layout design2Base
On plinth, retained in the domatic place of all etchings；
(3) P-SiO is finished2After photoetching, the P-SiO of non-reserved is removed by the method for wet etching2；
(4) P-SiO is finished2Afterwards, follow-up ITO, PN-Pad technique is continued；
(5) after PN-Pad techniques are completed, using the 10min that annealed under 250 DEG C, nitrogen protection atmosphere, product is through light for product
Electrical parameter takes a sample test judgement.
P-SiO in the step (1)2The plasma of laughing gas is used alone in deposition process to P-SiO2At film layer
Reason.
Growth ito film layer in the step (4), thickness is 0.05 μm -0.3 μm.
Compared with disclosed technology, there is advantages below in the present invention：The present invention is due to P-SiO2To etching domatic protection,
Current passivation SiO can be saved2Deposition, passivation SiO2Photoetching, passivation SiO2Dry etching and the follow-up processing procedure that removes photoresist, due to not
Passivation SiO is again2Technique, it is to avoid to passivation SiO2Halogen produces corrosion to PN-Pad metal pads during dry etching, it is ensured that high
The reliability that pressure LED core flake products are used.
Brief description of the drawings
Fig. 1 is the diagram of 6 road photolithography method P-SiO2 reticles.
Fig. 2 is the diagram of P-SiO2 reticles of the invention.
Specific embodiment
In order that technological means of the invention, creation characteristic, workflow, application method reached purpose and effect are easy to bright
It is white to understand, below in conjunction with the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described,
Obviously, described embodiment is only a part of embodiment of the invention, rather than whole embodiments.Based in the present invention
Embodiment, the every other embodiment that those of ordinary skill in the art are obtained under the premise of creative work is not made, all
Belong to the scope of protection of the invention.
Embodiment 1
A kind of high voltage LED chip preparation method, comprises the following steps：
(1) GaN epitaxy is grown from Sapphire Substrate, is deposited after Mesa etchings, gallium nitride deep etching (ISO) is completed
P-SiO2The film of deposition, P-SiO2The thickness of deposition is 200nm；P-SiO2The plasma of laughing gas is used alone in deposition process
To P-SiO2Film layer is processed.
(2) layout design is carried out on substrate prepared by previous step, in the P-SiO of 6 road photolithography methods during layout design2Base
On plinth, retained in the domatic place of all etchings；
(3) P-SiO is finished2After photoetching, the P-SiO of non-reserved is removed by the method for wet etching2；
(4) P-SiO is finished2Afterwards, follow-up ITO, PN-Pad technique is continued；Growth ito film layer, thickness is 0.2 μm.
(5) after PN-Pad techniques are completed, using the 10min that annealed under 250 DEG C, nitrogen protection atmosphere, product is through light for product
Electrical parameter takes a sample test judgement.
Embodiment 2
A kind of high voltage LED chip preparation method, comprises the following steps：
(1) GaN epitaxy is grown from Sapphire Substrate, is deposited after Mesa etchings, gallium nitride deep etching (ISO) is completed
P-SiO2The film of deposition, P-SiO2The thickness of deposition is 500nm；P-SiO2The plasma of laughing gas is used alone in deposition process
To P-SiO2Film layer is processed.
(2) layout design is carried out on substrate prepared by previous step, in the P-SiO of 6 road photolithography methods during layout design2's
On the basis of, retained in the domatic place of all etchings；
(3) P-SiO is finished2After photoetching, the P-SiO of non-reserved is removed by the method for wet etching2；
(4) P-SiO is finished2Afterwards, follow-up ITO, PN-Pad technique is continued；Growth ito film layer, thickness is 0.1 μm.
(5) after PN-Pad techniques are completed, using the 10min that annealed under 250 DEG C, nitrogen protection atmosphere, product is through light for product
Electrical parameter takes a sample test judgement.
Embodiment 3
A kind of high voltage LED chip preparation method, comprises the following steps：
(1) GaN epitaxy is grown from Sapphire Substrate, is deposited after Mesa etchings, gallium nitride deep etching (ISO) is completed
P-SiO2The film of deposition, P-SiO2The thickness of deposition is 1um；P-SiO2The plasma pair of laughing gas is used alone in deposition process
P-SiO2Film layer is processed.
(2) layout design is carried out on substrate prepared by previous step, in the P-SiO of 6 road photolithography methods during layout design2's
On the basis of, retained in the domatic place of all etchings；
(3) P-SiO is finished2After photoetching, the P-SiO of non-reserved is removed by the method for wet etching2；
(4) P-SiO is finished2Afterwards, follow-up ITO, PN-Pad technique is continued；Growth ito film layer, thickness is 0.05 μm.
(5) after PN-Pad techniques are completed, using the 10min that annealed under 250 DEG C, nitrogen protection atmosphere, product is through light for product
Electrical parameter takes a sample test judgement.
Compared with disclosed technology, there is advantages below in the present invention：The present invention is due to P-SiO2To etching domatic protection,
The passivation SiO in 6 road photolithography methods can be saved2Deposition, passivation SiO2Photoetching, passivation SiO2Dry etching and the follow-up system of removing photoresist
Journey, due to being no longer passivation SiO2Technique, it is to avoid to passivation SiO2Halogen produces rotten to PN-Pad metal pads during dry etching
Erosion, it is ensured that the reliability that high voltage LED chip product is used.
The present invention after deep etching (ISO), deposits P-SiO for the preparation method of current high-voltage LED2, it is being P-SiO2
During photoetching, retain original P-SiO2On the basis of current barrier layer (CBL), then domatic (exposed quantum well side is etched by all of
Face) P-SiO2Retain, so that using P-SiO2Substitute passivation SiO2Protection etching is domatic.Subsequently normally do ITO, PN-Pad work
Skill, due to P-SiO2To etching domatic protection, the passivation SiO in 6 road photolithography methods can be saved2Deposition, passivation SiO2Light
Carve, be passivated SiO2Dry etching and the follow-up processing procedure that removes photoresist, due to being no longer passivation SiO2Technique, it is to avoid to passivation SiO2Dry etching
When halogen to PN-Pad metal pads produce corrosion, it is ensured that the reliability that high voltage LED chip product is used.The invention enables
The preparation method of current high voltage LED chip is reduced to 5 road photoetching (MESA photoetching → deep etching (ISO) photoetching → P- by 6 road photoetching
SiO2Photoetching → ITO photoetching → PN-Pad photoetching), improve production efficiency, reduce production cost.
General principle of the invention, principal character and advantages of the present invention has been shown and described above.The technology of the industry
Personnel it should be appreciated that the present invention is not limited to the above embodiments, simply explanation described in above-described embodiment and specification this
The principle of invention, without departing from the spirit and scope of the present invention, various changes and modifications of the present invention are possible, these changes
Change and improvement all fall within the protetion scope of the claimed invention.Claimed scope of the invention by appending claims and
Its equivalent thereof.
Claims (3)
1. a kind of high voltage LED chip preparation method, it is characterised in that：Comprise the following steps：
(1) GaN epitaxy is grown from Sapphire Substrate, P- is deposited after Mesa etchings, gallium nitride deep etching (ISO) is completed
SiO2The film of deposition, P-SiO2The thickness of deposition is 100nm-1um；
(2) layout design is carried out on substrate prepared by previous step, in the P-SiO of 6 road photolithography methods during layout design2Basis
On, retained in the domatic place of all etchings；
(3) P-SiO is finished2After photoetching, the P-SiO of non-reserved is removed by the method for wet etching2；
(4) P-SiO is finished2Afterwards, follow-up ITO, PN-Pad technique is continued；
(5) after PN-Pad techniques are completed, product is joined using the 10min that annealed under 250 DEG C, nitrogen protection atmosphere, product through photoelectricity
Number takes a sample test judgement.
2. a kind of high voltage LED chip preparation method according to claim 1, it is characterised in that：P- in the step (1)
SiO2The plasma of laughing gas is used alone in deposition process to P-SiO2Film layer is processed.
3. a kind of high voltage LED chip preparation method according to claim 1, it is characterised in that：Growth in the step (4)
Ito film layer, thickness is 0.05 μm -0.3 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611187170.0A CN106711306A (en) | 2016-12-20 | 2016-12-20 | Method for preparing high-voltage LED chips |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611187170.0A CN106711306A (en) | 2016-12-20 | 2016-12-20 | Method for preparing high-voltage LED chips |
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| CN106711306A true CN106711306A (en) | 2017-05-24 |
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| CN201611187170.0A Pending CN106711306A (en) | 2016-12-20 | 2016-12-20 | Method for preparing high-voltage LED chips |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107611235A (en) * | 2017-08-29 | 2018-01-19 | 合肥彩虹蓝光科技有限公司 | A kind of method for lifting high voltage LED chip luminous efficiency |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103855180A (en) * | 2012-12-06 | 2014-06-11 | Lg伊诺特有限公司 | Light emitting device |
| CN104157765A (en) * | 2014-08-07 | 2014-11-19 | 湘能华磊光电股份有限公司 | Semiconductor luminescent device and manufacturing method thereof |
-
2016
- 2016-12-20 CN CN201611187170.0A patent/CN106711306A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103855180A (en) * | 2012-12-06 | 2014-06-11 | Lg伊诺特有限公司 | Light emitting device |
| CN104157765A (en) * | 2014-08-07 | 2014-11-19 | 湘能华磊光电股份有限公司 | Semiconductor luminescent device and manufacturing method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107611235A (en) * | 2017-08-29 | 2018-01-19 | 合肥彩虹蓝光科技有限公司 | A kind of method for lifting high voltage LED chip luminous efficiency |
| CN107611235B (en) * | 2017-08-29 | 2019-06-25 | 合肥彩虹蓝光科技有限公司 | A method of promoting high voltage LED chip luminous efficiency |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170524 |
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| RJ01 | Rejection of invention patent application after publication |