CN105870267B - A kind of quantum dot super-radiance light emitting diode and preparation method thereof - Google Patents
A kind of quantum dot super-radiance light emitting diode and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/0004—Devices characterised by their operation
- H01L33/0045—Devices characterised by their operation the devices being superluminescent diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
Abstract
The present invention relates to a kind of preparation method of quantum dot super-radiance light emitting diode, this method comprises the following steps：Epitaxial growth steps：Epitaxial structure is grown using MBE, its structure includes N successively along crystal orientation+GaAs substrate layers (1), N GaAs cushions (2), N AlGaAs coatings (3), AlGaAs lower limit layers (4), the active area (5) containing Multilayer InAs Quantum Dots, AlGaAs upper limiting layers (6), P AlGaAs coatings (7), P GaAs protective layers (8)；The step of forming ridge shape；The step of growing buried heterostructure；The step of evaporating N, P-type electrode；Plating steps.The invention also provides a kind of quantum dot super-radiance light emitting diode.Super-radiance light emitting diode chip proposed by the present invention has the advantages of high power, wide spectrum output, low jitter.
Description
Technical field
The present invention relates to a kind of light emitting diode, and in particular to a kind of quantum dot super-radiance light emitting diode and its making side
Method.
Background technology
Super-radiance light emitting diode (Super luminescent Diodes, SLD) is a kind of high-output power, wide spectrum
The high stable light source of scope, it has luminous spectrum more broader than semiconductor laser and lower coherence length；With light-emitting diodes
Pipe is compared, and has higher power output, is widely used in OCT (optical coherence tomography) imaging, optical fibre gyro, fibre optical sensor
Etc. in system.For the SLD light sources currently used for OCT (optical coherence tomography) 800nm wavelength, because its spectrum width is narrower,
Simultaneously its peak wavelength it is shorter caused by backscattering largely have impact on OCT imaging resolution and detect it is sensitive
Degree.Therefore the peak wavelength of light source how is further improved, increase spectrum width is to improve to be used for 800nm GaAs bases in OCT at this stage
One important method of SLD light sources.
Conventional uniform MQW, its gain spectral all relative narrowers, it is difficult to obtain the output of wide spectrum；For non-homogeneous
For MQW, output spectrum width can be improved to a certain extent, but because the electron energy state between different SQWs is discontinuous,
It is difficult to obtain the spectrum with regular gaussian shape.
For quantum spot semiconductor device, dimensionally there is necessarily non-by the quantum dot of self-organizing growth
Even property, this heteropical quantum dot are a favourable factors for the device for making wide spectrum.Related research
As a result show, the quantum point set with certain size distribution is with wider gain spectral, and size heterogeneity is bigger, under peak value
Drop is bigger, broadening is stronger.Meanwhile the Size Distribution general satisfaction Gaussian Profile of quantum dot, the ground state of different dimensional quantum points with
Excited level is overlapping together so that the energy level approximate continuous distribution of quantum point set, is more likely formed the output of regular shape
Spectrum.For single quantum well or uniform MQW super-radiance light emitting diode, can only obtain under relatively low injected current density
Very narrow spectral width, for MQW SLD, different in width SQW ground state transition energy is discontinuously so that bands of a spectrum can be caused
It is in irregular shape.To deepen with the research of super-radiance light emitting diode, the application of super-radiance light emitting diode is more and more extensive,
Therewith to the performance requirement more and more higher of device.SLD there is also some problems design of material and structure, it is necessary to SLD at present
Optimize, further improve device output power, widen spectral width etc..
The content of the invention
Present invention aims at a kind of quantum dot super-radiance light emitting diode for OCT and preparation method thereof is provided, lead to
The material component and growth temperature of quantum dot barrier layer are crossed, realizes that wide spectrum exports；On the other hand realized using buried structure low
The angle of divergence and high carrier injection efficiency, the SLD chips of making have wide spectrum, the output of low ripple.
A kind of preparation method of quantum dot super-radiance light emitting diode, this method comprise the following steps：
Epitaxial growth steps：Epitaxial structure is grown using MBE, its structure includes N successively along crystal orientation+-GaAs
Substrate layer, N-GaAs cushions, N-AlGaAs coatings, AlGaAs lower limit layers, the active area containing Multilayer InAs Quantum Dots,
AlGaAs upper limiting layers, P-AlGaAs coatings, P-GaAs protective layers；Wherein active area includes first undoped with GaAs layers, more
Layer InAs quantum dots and second undoped with GaAs layers, every layer of InAs quantum dot include InAs quantum dots, InGaAs coatings and
GaAs coatings；
The step of forming ridge shape：After removing the P-GaAs protective layers in an epitaxial structure, deposition medium film, light
Quarter, etch media film, corrosion form ridge structure；
The step of growing buried heterostructure：Burial growth is carried out to the slice, thin piece for forming ridge structure using MOCVD epitaxy growth,
Form buried heterostructure structure；
The step of evaporating N, P-type electrode：Slice, thin piece is carried out deposit passivation layer, photoetching, Etch Passivation, deposition P faces metal,
It is thinned, deposition N faces metal, alloy, forms chip；
Plating steps：A bar bar is dissociated into along crystal orientation to slice, thin piece, evaporation optical film is carried out to a bar bar light extraction, backlight end face.
Further, an epitaxial growth steps are specifically, in N+On-GaAs substrates, MBE grows and mixed at 500 DEG C
Miscellaneous concentration 1 × 1018200nm N-GaAs cushions, doping concentration 1 × 1018100nm N-AlGaAs coatings, 200nm
AlGaAs lower limit layers, the active area containing Multilayer InAs Quantum Dots, then grow at 500 DEG C 200nm AlGaAs upper limiting layers,
Doping concentration 1 × 1018100nm P-AlGaAs coatings, doping concentration 1 × 101810nm P-GaAs protective layers.
Further, the InGaAs coatings are specially In0.05Ga0.95As coatings, having containing Multilayer InAs Quantum Dots
Source region is the active area containing four layers of InAs quantum dots, and the specific growing method of the active area is as follows：100nm is grown at 500 DEG C
First, undoped with GaAs layers, grows 2ML InAs quantum dots, grows 5nm In0.05Ga0.95As coatings, growth temperature is improved
To 600 DEG C, anneal 30s, 25nm GaAs coatings is then grown, so as to grow first layer InAs on undoped with GaAs layers
Quantum dot；500 DEG C are cooled the temperature to, 2ML InAs quantum dots are grown on the GaAs coatings grown before, grows 5nm
In0.08Ga0.92As coatings, growth temperature is increased to 600 DEG C, anneal 30s, grows 25nm GaAs coatings, so as to the
Second layer InAs quantum dots are grown on one layer of InAs quantum dot；Above-mentioned InAs Quantum Dots Growths step, Zhi Dao are repeated again
Third layer InAs quantum dots are grown on second layer InAs quantum dots and grow the 4th layer on third layer InAs quantum dots
InAs quantum dots；100nm second is grown on the 4th layer of InAs quantum dot at 500 DEG C again undoped with GaAs layers, is completed active
Area grows.
Further, the step of formation ridge shape is specially：P-GaAs protective layers are removed, deposit 250nm SiO2
Dielectric layer, it is lithographically formed ridge pattern, RIE etchings point exposure area dielectric layer, using H2O:H2O2:H2SO4(8:8:1) corrosive liquid,
Corrode at room temperature to N-GaAs cushions, form ridge structure, 1.2 μm of corrosion depth, a width of 2um of ridge.
Further, the ridge structure includes straight wave guide region and tapered waveguide region, tapered waveguide region and straight wave guide
Region is connected, and tapered waveguide region is close to light output end, and straight wave guide region is close to backlight end face.
Further, wherein straight wave guide region and chip end face normal direction is into 2~5 ° of angles, preferably 3 °；Tapered transmission line area
Domain subtended angle is 2~5 °, preferably 3 °.
Further, a length of 1000 μm of its chips chamber, straight wave guide region is along 750 μm of cavity length direction length, tapered transmission line
Region is along 250 μm of cavity length direction length.
Further, the step of growth buried heterostructure is specially：The sample for forming ridge structure is put into MOCVD to set
In standby, AsH is led at 630 DEG C3Remove ridge sidewall surfaces oxide layer within 15 minutes, grow 600nm P-AlGaAs buried layers successively
With 900nm N-GaAs buried layers as current barrier layer；Remove the SiO on ridge2Dielectric layer, then grow 200nm P with MOCVD+-
GaAs contact layers, complete to bury growth.
Further, the step of evaporation N, P-type electrode is specially：In sample surfaces deposition 300nm SiO2Passivation
Layer, by photoetching, RIE etching exposure area passivation layers, electron beam evaporation Au (20nm)/Zn (50nm)/Au (1000nm) is used as P
Face metal, sample is thinned to 110 μm of thickness, electron beam evaporation AuGe (500nm)/Ni (800nm)/Au (1000nm) is used as N
Face metal, 420 DEG C of alloy 60s in a nitrogen atmosphere.
Further, the plating steps are specially：Sample dissociation coelosis is grown to 1000 μm of bar bar, steamed using electron beam
Individual layer SiO is deposited in hair on the light output end of chip and backlight end face2High transmittance film, complete the making of chip.
The invention also provides a kind of quantum dot super-radiance light emitting diode, the quantum dot super-radiance light emitting diode bag
Include：Epitaxial structure and buried heterostructure structure, wherein, an epitaxial structure includes：The N set gradually along crystal orientation+-
GaAs substrate layers, N-GaAs cushions, N-AlGaAs coatings, AlGaAs lower limit layers, containing the active of Multilayer InAs Quantum Dots
Area, AlGaAs upper limiting layers and P-AlGaAs coatings；Wherein active area include along crystal orientation set gradually first undoped with
GaAs layers, Multilayer InAs Quantum Dots and second are undoped with GaAs layers；
N-AlGaAs coatings, AlGaAs lower limit layers, the active area containing Multilayer InAs Quantum Dots, AlGaAs upper limiting layers
The ridge structure along crystal orientation is formed with P-AlGaAs coatings, ridge structure is divided into straight wave guide region and tapered transmission line area along cavity length direction
Domain, tapered waveguide region are connected with straight wave guide region, and tapered waveguide region is close to light output end, and straight wave guide region is close to backlight end
Face；
The P-AlGaAs that the buried heterostructure structure is included on N-GaAs cushions and set gradually along crystal orientation is buried
Layer, N-GaAs buried layers and P+- GaAs contact layers, P-AlGaAs buried layers and N-GaAs buried layers are as current barrier layer, P-
AlGaAs buried layers and N-GaAs buried layers form the sidewall surfaces in ridge structure, N-GaAs buried layers and P-AlGaAs coatings
Upper surface is concordant, P+- GaAs contact layers are formed on N-GaAs buried layers and P-AlGaAs coatings upper surface.
Further, the quantum dot super-radiance light emitting diode is used as preceding any preparation method is made.
Beneficial effects of the present invention：The super-radiance light emitting diode of quantum-dot structure proposed by the present invention and its making side
Method, its epitaxial structure are grown successively using MBE on N+-GaAs substrate layers：N-GaAs cushions, N-AlGaAs coverings
Layer, AlGaAs lower limit layers, the active area containing four layers of InAs quantum dots, AlGaAs upper limiting layers, P-AlGaAs coatings, P-
GaAs protective layers, complete an epitaxial growth；Used in an extension active region growth and become component and high temperature quantum dot cap rock,
The growth of different sizes, even density quantum dot is realized, it is achieved thereby that an epitaxial structure of wide gain spectrum.To an extension
Piece is corroded, and is completed the buried heterostructure of chip using the method for MOCVD diauxic growths, is realized the horizontal stroke of light field and carrier
To limitation；Inclined tapered transmission line is used simultaneously, further to optimize output spectrum, finally in chip light-emitting end face and backlight end
High transmittance film is all deposited in face, to reduce the feedback of Cavity surface pattern, reduces spectral ripple.Super-radiance light emitting diode proposed by the present invention
Chip has the advantages of high power, wide spectrum output, low jitter.
Brief description of the drawings
Fig. 1 is quantum dot super-radiance light emitting diode process chart of the present invention.
Fig. 2 is an epitaxial slice structure schematic diagram of the super-radiance light emitting diode of the quantum-dot structure of the present invention.
Fig. 3 is the structural representation of the light emitting diode with quantum dots chip of the present invention.
Description of reference numerals：1N+- GaAs substrates, 2N-GaAs cushions, 3N-AlGaAs coatings, limit under 4AlGaAs
Layer, 5 active areas containing four layers of InAs quantum dots, 6AlGaAs upper limiting layers, 7P-AlGaAs coatings, 8P-GaAs protective layers,
9InAs quantum dots, 10InGaAs coatings, 11GaAs coatings；12P-AlGaAs buried layers, 13N-GaAs buried layers, 14P+-
GaAs contact layers, 15 tapered waveguide regions, 16 straight wave guide regions, 17 light output ends, 18 backlight end faces.
Embodiment
For the object, technical solutions and advantages of the present invention are more clearly understood, below in conjunction with specific embodiment, and reference
Accompanying drawing, the present invention is described in more detail.But those skilled in the art know, the invention is not limited in accompanying drawing and following reality
Apply example.
The present invention relates to a kind of quantum dot super-radiance light emitting diode and preparation method thereof, the present invention exists successively with MBE
Grown cushion, coating, lower limit layer, containing quantum dot active region, upper limiting layer, coating, protective layer complete one
Secondary epitaxial growth；In an extension active region growth using component and high temperature quantum dot cap rock is become, different sizes, density are realized
The growth of uniform quantum dot.Epitaxial wafer is corroded, the burial that chip is completed using the method for MOCVD diauxic growths is different
Matter structure, realize laterally limiting for light field and carrier；Inclined tapered transmission line is used simultaneously, further to optimize output light
Spectrum.High transmittance film is all finally deposited in chip light-emitting end face and backlight end face, to reduce the feedback of Cavity surface pattern, reduces spectrum ripple
Line.The quantum dot super-radiance light emitting diode has the advantages that high power, wide spectrum, low jitter.
Embodiment 1：
The preparation method of a kind of quantum dot super-radiance light emitting diode proposed by the present invention, as shown in figure 1, this method includes
Following steps：
A 1. epitaxial growth steps：As shown in Fig. 2 using MBE grow an epitaxial structure, its structure along crystal orientation successively
(as shown in Figure 2 from top to bottom) N is included+- GaAs substrate layers 1, N-GaAs cushions 2, N-AlGaAs coatings 3, AlGaAs
Lower limit layer 4, the active area 5 containing four layers of InAs quantum dots, AlGaAs upper limiting layers 6, P-AlGaAs coatings 7, P-GaAs are protected
Sheath 8.
Wherein active area 5 includes first undoped with GaAs layers, four layers of InAs quantum dots and second undoped with GaAs layers, every layer
InAs quantum dots include InAs quantum dots 9, InGaAs coatings 10 and GaAs coatings 11.
During active region growth, larger In components are advantageous to discharge in InAs quantum dots in InGaAs coatings
Stress, reduce the lattice mismatch between InAs and GaAs cap rocks so that the size increase of InAs quantum dots, peak luminous wavelength are red
Move.On the other hand, larger In components be advantageous to suppress In separated out from InAs quantum dots to cap rock so that In in InAs quantum dots
Component improve, quantum dot band gap reduces, and peak luminous wavelength red shift moves.The InGaAs cap rocks of growth can cover most of
Quantum dot, in further high growth temperature GaAs overlay process, high growth temperature can melt excessive quantum dot so that growth
Surface is smooth, and this causes, and the quantum dot stress of subsequent growth is low, density is big.Therefore change of component InGaAs/ high temperature GaAs is used
Double-canopy layer can realize uniform quantum dot density, wide spectrum and peak luminous wavelength red shift.
2. the step of forming ridge shape：As shown in figure 3, removing P-GaAs protective layers 8, deposition medium film, photoetching, etching are situated between
Plasma membrane, corrosion form ridge structure；
3. the step of growing buried heterostructure：As shown in figure 3, using MOCVD epitaxy growth to the slice, thin piece of formation ridge structure
Burial growth is carried out, forms buried heterostructure structure；
4. the step of evaporating N, P-type electrode：Deposit passivation layer, photoetching, Etch Passivation, deposition P faces gold are carried out to slice, thin piece
Category, it is thinned, deposition N faces metal, alloy, forms chip；
5. plating steps：A bar bar is dissociated into along crystal orientation to slice, thin piece, evaporation optical film is carried out to a bar bar light extraction, backlight end face.
Embodiment 2：
The present embodiment is the preferred embodiment on the basis of embodiment 1.Quantum dot superradiation light-emitting proposed by the present invention
The preparation method of diode is as shown in figure 1, this method includes：
A 1. epitaxial growth steps：As shown in Fig. 2 in N+On-GaAs substrates 1, MBE grows doping concentration 1 at 500 DEG C
×1018200nm N-GaAs cushions 2, doping concentration 1 × 1018100nm N-AlGaAs coatings 3,200nm AlGaAs
Lower limit layer 4, the active area 5 containing four layers of InAs quantum dots, 200nm AlGaAs upper limiting layers 6, doping are then grown at 500 DEG C
Concentration 1 × 1018100nm P-AlGaAs coatings 7, doping concentration 1 × 101810nm P-GaAs protective layers 8, complete once
The growth of extension, its structure are as shown in Figure 2.
The wherein growing method of active area 5 is as follows：100nm is grown at 500 DEG C undoped with GaAs layers, growth 2ML (ML：Atom
Layer) InAs quantum dots 9, growth 5nm In0.05Ga0.95As coatings 10, growth temperature is improved to 600 DEG C, anneal 30s, connects
Growth 25nm GaAs coatings 11, so as to grow first layer InAs quantum dots on undoped with GaAs layers；Temperature is dropped
To 500 DEG C, 2ML InAs quantum dots are grown on the GaAs coatings 11 grown before, grow 5nmIn0.08Ga0.92As is covered
Layer, growth temperature is increased to 600 DEG C, anneal 30s, grows 25nm GaAs coatings, so as on first layer InAs quantum dots
Grow second layer InAs quantum dots；Above-mentioned InAs Quantum Dots Growths step is repeated again, until in second layer InAs quantum dots
On grow third layer InAs quantum dots and the 4th layer of InAs quantum dot grown on third layer InAs quantum dots；Again 500
100nm is grown undoped with GaAs layers on the 4th layer of InAs quantum dot at DEG C, completes active region growth.
2. the step of forming ridge shape：As shown in figure 3, removing P-GaAs protective layers, 250nm SiO is deposited2Dielectric layer,
It is lithographically formed ridge pattern, RIE etchings point exposure area dielectric layer, using H2O:H2O2:H2SO4(8:8:1) corrosive liquid, at room temperature
Corrosion forms ridge structure, 1.2 μm of corrosion depth to N-GaAs cushions 2.As shown in figure 3, a length of 1000 μm of chip chamber, ridge is wide
For 2um.Ridge structure includes straight wave guide region 16 and tapered waveguide region 15, and tapered waveguide region 15 is close to light output end 17, directly
Waveguide region 16 close to backlight end face 18, wherein straight wave guide region 16 along 750 μm of cavity length direction length, with chip end face normal direction into
2~5 ° of angles, preferably 3 °；Tapered waveguide region 15 is connected with straight wave guide region 16, the subtended angle of tapered waveguide region 15 be 2~
5 °, preferably 3 °.
3. the step of growing buried heterostructure：As shown in figure 3, the sample for forming ridge structure is put into MOCVD device,
Lead to AsH at 630 DEG C3Remove ridge sidewall surfaces oxide layer within 15 minutes, grow the He of 600nm P-AlGaAs buried layers 12 successively
900nm N-GaAs buried layers 13 are used as current barrier layer；Remove the SiO on ridge2Dielectric layer, then grow 200nm P with MOCVD+-
GaAs contact layers 14, complete to bury growth.
4. the step of evaporating N, P-type electrode：In sample surfaces deposition 300nm SiO2Passivation layer, pass through photoetching, RIE etchings
Exposure area passivation layer, electron beam evaporation Au (20nm)/Zn (50nm)/Au (1000nm) are used as P faces metal, sample are thinned to
110 μm of thickness, electron beam evaporation AuGe (500nm)/Ni (800nm)/Au (1000nm) are used as N faces metal, and 420 DEG C in nitrogen gas
Alloy 60s under atmosphere.
5. plating steps：Sample dissociation coelosis is grown to 1000 μm of bar bar, using electron beam evaporation at the light extraction end of chip
Individual layer SiO is deposited on face and backlight end face2High transmittance film, complete the making of chip.
Embodiment 3：
Quantum dot super-radiance light emitting diode proposed by the present invention as shown in Figures 2 and 3, the quantum dot superradiation light-emitting two
Pole pipe includes：Epitaxial structure and buried heterostructure structure, wherein, an epitaxial structure includes：Set successively along crystal orientation
The N put+- GaAs substrate layers 1, N-GaAs cushions 2, N-AlGaAs coatings 3, AlGaAs lower limit layers 4, containing four layers of InAs amounts
Active area 5, AlGaAs upper limiting layers 6 and the P-AlGaAs coatings 7 of son point；Wherein active area 5 includes setting gradually along crystal orientation
First undoped with GaAs layers, four layers of InAs quantum dots and second undoped with GaAs layers.
N-AlGaAs coatings 3, AlGaAs lower limit layers 4, the active area 5 containing four layers of InAs quantum dots, the AlGaAs upper limits
Preparative layer 6 and P-AlGaAs coatings 7 form the ridge structure along crystal orientation, and ridge structure is divided into straight wave guide region 16 and cone along cavity length direction
Shape waveguide region 15, tapered waveguide region 15 are connected with straight wave guide region 16, and tapered waveguide region 15 is close to light output end 17, directly
Waveguide region 16 is close to backlight end face 18.Preferably, individual layer SiO is deposited on the light output end of chip and backlight end face2High transmittance film.
Wherein straight wave guide region 16 is along 750 μm of cavity length direction length, with chip end face normal direction into 3 ° of angles；Tapered transmission line area
The subtended angle of domain 15 is 3 °, along 250 μm of cavity length direction length.
The P-AlGaAs that the buried heterostructure structure is included on N-GaAs cushions 2 and set gradually along crystal orientation is buried
Layer 12, N-GaAs buried layers 13 and P+- GaAs contact layers 14, P-AlGaAs buried layers 12 and N-GaAs buried layers 13 are used as electric current
Barrier layer, P-AlGaAs buried layers 12 and N-GaAs buried layers 13 form side wall (side wall as shown in Figure 3) table in ridge structure
Face, N-GaAs buried layers 13 and the upper surface of P-AlGaAs coatings 7 (upper surface as shown in Figure 3) concordant, P+- GaAs contact layers
14 form on N-GaAs buried layers 13 and the upper surface of P-AlGaAs coatings 7.
Wherein, SiO is deposited in sample surfaces2Passivation layer, by photoetching, RIE etching exposure area passivation layers, electron beam steams
Hair Au (20nm)/Zn (50nm)/Au (1000nm) is used as P faces metal, electron beam evaporation AuGe (500nm)/Ni (800nm)/Au
(1000nm) is used as N faces metal.
Preferably, the quantum dot super-radiance light emitting diode of the present embodiment can use any making side in embodiment 1 to 2
Method makes.
More than, embodiments of the present invention are illustrated.But the present invention is not limited to above-mentioned embodiment.It is all
Within the spirit and principles in the present invention, any modification, equivalent substitution and improvements done etc., it should be included in the guarantor of the present invention
Within the scope of shield.
Claims (17)
1. a kind of preparation method of quantum dot super-radiance light emitting diode, it is characterised in that this method comprises the following steps：
Epitaxial growth steps：Epitaxial structure is grown using MBE, its structure includes N successively along crystal orientation+- GaAs substrate layers
(1), N-GaAs cushions (2), N-AlGaAs coatings (3), AlGaAs lower limit layers (4), having containing Multilayer InAs Quantum Dots
Source region (5), AlGaAs upper limiting layers (6), P-AlGaAs coatings (7), P-GaAs protective layers (8)；Wherein active area (5) includes
First includes InAs quantum undoped with GaAs layers, Multilayer InAs Quantum Dots and second undoped with GaAs layers, every layer of InAs quantum dot
Point (9), InGaAs coatings (10) and GaAs coatings (11)；
The step of forming ridge shape：After removing the P-GaAs protective layers (8) in an epitaxial structure, deposition medium film, light
Quarter, etch media film, corrosion form ridge structure；Wherein, the ridge structure includes straight wave guide region (16) and tapered waveguide region
(15), tapered waveguide region (15) are connected with straight wave guide region (16), tapered waveguide region (15) close light output end (17), directly
Waveguide region (16) is close to backlight end face (18)；
The step of growing buried heterostructure：Burial growth is carried out to the slice, thin piece for forming ridge structure using MOCVD epitaxy growth, formed
Buried heterostructure structure；
The step of evaporating N, P-type electrode：Deposit passivation layer, photoetching are carried out to slice, thin piece, Etch Passivation, deposition P faces metal, is subtracted
Thin, deposition N faces metal, alloy, form chip；
Plating steps：A bar bar is dissociated into along crystal orientation to slice, thin piece, evaporation optical film is carried out to a bar bar light extraction, backlight end face.
2. preparation method according to claim 1 a, it is characterised in that epitaxial growth steps are specifically, in N+-
On GaAs substrate layers (1), MBE grows doping concentration 1 × 10 at 500 DEG C18200nm N-GaAs cushions (2), doping concentration 1
×1018100nm N-AlGaAs coatings (3), 200nm AlGaAs lower limit layers (4), containing the active of Multilayer InAs Quantum Dots
Area (5), 200nm AlGaAs upper limiting layers (6), doping concentration 1 × 10 are then grown at 500 DEG C18100nm P-AlGaAs cover
Cap rock (7), doping concentration 1 × 101810nm P-GaAs protective layers (8).
3. preparation method according to claim 2, it is characterised in that the InGaAs coatings (10) are specially
In0.05Ga0.95As coatings (10), the active area (5) containing Multilayer InAs Quantum Dots are the active area containing four layers of InAs quantum dots,
The specific growing method of the active area (5) is as follows：100nm first is grown at 500 DEG C undoped with GaAs layers, grows 2ML's
InAs quantum dots (9), growth 5nm In0.05Ga0.95As coatings (10), growth temperature is improved to 600 DEG C, anneal 30s, connects
Growth 25nm GaAs coatings (11), so as to grow first layer InAs quantum dots on undoped with GaAs layers；By temperature
500 DEG C are down to, 2ML InAs quantum dots, growth 5nm In are grown on the GaAs coatings (11) grown before0.08Ga0.92As
Coating, growth temperature is increased to 600 DEG C, anneal 30s, grows 25nm GaAs coatings, so as in first layer InAs quantum
Second layer InAs quantum dots are grown on point；Above-mentioned InAs Quantum Dots Growths step is repeated again, until in second layer InAs amounts
Third layer InAs quantum dots are grown on son point and the 4th layer of InAs quantum dot is grown on third layer InAs quantum dots；Exist again
100nm second is grown undoped with GaAs layers on the 4th layer of InAs quantum dot at 500 DEG C, completes active region growth.
4. preparation method according to claim 3, it is characterised in that it is described formation ridge shape the step of be specially：Remove
P-GaAs protective layers, deposit 250nm SiO2Dielectric layer, ridge pattern is lithographically formed, RIE etchings point exposure area dielectric layer, is adopted
Use H2O:H2O2:H2SO4(8:8:1) corrosive liquid, corrode at room temperature to N-GaAs cushions (2), form ridge structure, corrosion depth
1.2 μm, a width of 2um of ridge.
5. preparation method according to claim 1, it is characterised in that straight wave guide region (16) and chip end face normal direction are into 2
~5 ° of angles；Tapered waveguide region (15) subtended angle is 2~5 °.
6. preparation method according to claim 5, it is characterised in that the straight wave guide region (16) and chip end face normal direction
Into 3 ° of angles.
7. preparation method according to claim 5, it is characterised in that tapered waveguide region (15) subtended angle is 3 °.
8. preparation method according to claim 5, it is characterised in that a length of 1000 μm of chip chamber, straight wave guide region (16)
Along 750 μm of cavity length direction length, tapered waveguide region (15) are along 250 μm of cavity length direction length.
9. preparation method according to claim 4, it is characterised in that straight wave guide region (16) and chip end face normal direction are into 2
~5 ° of angles；Tapered waveguide region (15) subtended angle is 2~5 °.
10. preparation method according to claim 9, it is characterised in that the straight wave guide region (16) and chip end face method
To into 3 ° of angles.
11. preparation method according to claim 9, it is characterised in that tapered waveguide region (15) subtended angle is 3 °.
12. preparation method according to claim 9, it is characterised in that a length of 1000 μm of chip chamber, straight wave guide region (16)
Along 750 μm of cavity length direction length, tapered waveguide region (15) are along 250 μm of cavity length direction length.
13. the preparation method according to any one of claim 5 to 12, it is characterised in that the growth buried heterostructure
The step of be specially：The sample for forming ridge structure is put into MOCVD device, AsH is led at 630 DEG C3Remove ridge side within 15 minutes
Wall surface oxide layer, grow 600nm P-AlGaAs buried layers (12) successively and 900nm N-GaAs buried layers (13) are used as electric current
Barrier layer；Remove the SiO on ridge2Dielectric layer, then grow 200nm P with MOCVD+- GaAs contact layers (14), complete to bury growth.
14. preparation method according to claim 13, it is characterised in that be specially the step of the evaporation N, P-type electrode：
In sample surfaces deposition 300nm SiO2Passivation layer, pass through photoetching, RIE etching exposure area passivation layers, electron beam evaporation Au/
Zn/Au is thinned to 110 μm of thickness as P faces metal, by sample, and electron beam evaporation AuGe/Ni/Au is as N faces metal, 420 DEG C
Alloy 60s in a nitrogen atmosphere.
15. preparation method according to claim 14, it is characterised in that the plating steps are specially：Sample is dissociated
Coelosis grows 1000 μm of bar bar, and individual layer SiO is deposited on the light output end of chip and backlight end face using electron beam evaporation2It is high
Permeable membrane, complete the making of chip.
16. a kind of quantum dot super-radiance light emitting diode, it is characterised in that the quantum dot super-radiance light emitting diode includes：One
Secondary epitaxial structure and buried heterostructure structure, wherein, an epitaxial structure includes：The N set gradually along crystal orientation+-GaAs
Substrate layer (1), N-GaAs cushions (2), N-AlGaAs coatings (3), AlGaAs lower limit layers (4), the quantum of InAs containing multilayer
Active area (5), AlGaAs upper limiting layers (6) and the P-AlGaAs coatings (7) of point；Wherein active area (5) include along crystal orientation according to
The first of secondary setting is undoped with GaAs layers, Multilayer InAs Quantum Dots and second undoped with GaAs layers；
N-AlGaAs coatings (3), AlGaAs lower limit layers (4), the active area (5) containing Multilayer InAs Quantum Dots, on AlGaAs
Limiting layer (6) and P-AlGaAs coatings (7) form the ridge structure along crystal orientation, and ridge structure is divided into straight wave guide region along cavity length direction
(16) it is connected with tapered waveguide region (15), tapered waveguide region (15) with straight wave guide region (16), tapered waveguide region (15)
Close to light output end (17), straight wave guide region (16) are close to backlight end face (18)；
The P-AlGaAs buried layers that the buried heterostructure structure is included on N-GaAs cushions (2) and set gradually along crystal orientation
(12), N-GaAs buried layers (13) and P+- GaAs contact layers (14), P-AlGaAs buried layers (12) and N-GaAs buried layers (13)
As current barrier layer, P-AlGaAs buried layers (12) and N-GaAs buried layers (13) formation are in the sidewall surfaces of ridge structure, N-
GaAs buried layers (13) are concordant with P-AlGaAs coatings (7) upper surface, P+- GaAs contact layers (14) are formed buries in N-GaAs
On layer (13) and P-AlGaAs coatings (7) upper surface.
17. quantum dot super-radiance light emitting diode according to claim 16, it is characterised in that the quantum dot superradiance is sent out
Optical diode is made using the preparation method as any one of claim 1 to 15.
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| CN105280763A (en) * | 2015-09-14 | 2016-01-27 | 中国科学院福建物质结构研究所 | Manufacturing method of superradiation light emitting diode and light emitting diode manufactured by method |
| CN205582962U (en) * | 2016-04-28 | 2016-09-14 | 中国科学院福建物质结构研究所 | Quantum dot superradiance emitting diode |
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| CN105098006A (en) * | 2015-09-09 | 2015-11-25 | 中国科学院福建物质结构研究所 | Fabrication method of superluminescent diode chip and fabricated light emitting diode chip |
| CN105280763A (en) * | 2015-09-14 | 2016-01-27 | 中国科学院福建物质结构研究所 | Manufacturing method of superradiation light emitting diode and light emitting diode manufactured by method |
| CN205582962U (en) * | 2016-04-28 | 2016-09-14 | 中国科学院福建物质结构研究所 | Quantum dot superradiance emitting diode |
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