JP5301418B2 - Semiconductor light emitting device and method for manufacturing semiconductor light emitting device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To secure a high yield by stably forming a protective film terminated at the predetermined position of a semiconductor film side surface exposed by forming element separation grooves for partitioning a discrete semiconductor light-emitting device. <P>SOLUTION: A method for manufacturing a light-emitting device includes: forming a semiconductor film 20 on a substrate for growth, forming element separation grooves reaching the substrate for growth on the semiconductor film 20; and also forming a protective film 50 partially covering the side surface of the semiconductor film 20 exposed by forming the element separation grooves and being apart from the substrate for growth. A process for forming the element separation grooves includes: a first etching process etching the semiconductor film 20 so that an inclined angle of the exposed surface by etching to the main surface of the semiconductor film 20 has a first inclined angle; and a second etching process forming the exposed surface having a different inclined angle by etching the semiconductor film 20 after the first etching process so that an inclined angle of the exposed surface by etching to the semiconductor film 20 has a second inclined angle greater than the first inclined angle. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor light emitting device such as an LED (light emitting diode).

Conventional technology

  Patent Document 1 discloses a configuration of a semiconductor light emitting device in which an element dividing groove is formed in a semiconductor film formed on a sapphire substrate, and a protective film is formed on a side surface of the semiconductor film exposed by forming the element dividing groove. It is disclosed.

  On the other hand, an LED having a so-called bonded structure in which a semiconductor film is supported by a support substrate different from a sapphire substrate is known. An LED having such a structure is obtained by growing a semiconductor film on a sapphire substrate, bonding the support substrate and the semiconductor film, and then removing the sapphire substrate by a method such as laser lift-off (hereinafter referred to as LLO). Can do. By adopting a bonded structure, it is possible to improve the thermal conductivity and light extraction efficiency of the LED by selecting the material of the support substrate. It is also possible to use the support substrate as a conductive layer.

JP 2009-111102 A

In the LLO method, laser is irradiated from the back side of a growth substrate such as a sapphire substrate, and the GaN layer formed on the growth substrate is decomposed into metal Ga and N ₂ gas. It is known that the GaN layer formed on the sapphire substrate is destroyed by the pressure of the N ₂ gas generated at this time. In order to avoid this, a method has been proposed in which element dividing grooves (streets) are formed along the outer edge of each LED chip before LLO. By forming the element dividing grooves in the semiconductor film in advance, a discharge path for N ₂ gas generated during LLO is secured, and element destruction can be avoided. If conductive foreign matter adheres to the side surface of the semiconductor film exposed by forming the element dividing groove, the characteristics may be adversely affected. For this reason, the exposed side surface of the semiconductor film is covered with an insulating protective film such as SiO ₂ . At this time, the sapphire substrate exposed at the bottom surface of the element dividing groove is also partially covered with the protective film. Thereafter, when the sapphire substrate is removed from the semiconductor film using the LLO method, the protective film formed on the sapphire substrate may be cracked or peeled off due to laser irradiation to the protective film or generation of N ₂ gas. . Since SiO _{2 that} is generally used as a protective film is hard and brittle, cracks and delamination that occur near the interface with the sapphire substrate also propagate to the portion that covers the side surface of the semiconductor film. If peeling or cracking occurs in the protective film that covers the side surface of the semiconductor film, the function as the protective film cannot be performed sufficiently, and yield and reliability are lowered.

  In order to avoid such a problem, it is necessary to prevent the cracks and separation of the protective film generated on the sapphire substrate during LLO from propagating to the portion formed on the side surface of the semiconductor. For example, avoiding the propagation of cracks and delamination by forming a protective film that covers part of the p-GaN layer, active layer and n-GaN layer on the side of the semiconductor film and does not reach the sapphire substrate Can do. That is, the protective film is patterned so that the protective film on the side surface of the semiconductor film is terminated at a position separated from the sapphire substrate. Patent Document 1 describes that a protective film having such a structure is formed by side etching in wet etching.

However, when the element dividing groove is formed by general dry etching using Cl ₂ plasma or the like, the inclination angle of the side surface of the semiconductor film with respect to the main surface becomes 90 ° or a value close thereto, and the amount of side etching in the wet etching process Therefore, it is difficult to remove the protective film in an appropriate range on the side surface of the GaN semiconductor film due to the problem of processing accuracy.

  FIG. 1 is a cross-sectional view and a plan view of a semiconductor light emitting device having a protective film 200 that terminates at the intermediate position of the side surface of the n layer 110 on the side surface of the semiconductor film 100. The protective film 200 plays a role in preventing foreign matter from adhering to the exposed side surfaces of the semiconductor film 100 and avoiding an increase in leakage current. For this reason, the protective film 200 must be formed so as to cover at least part of the p layer 130, the active layer 120, and the n layer 110.

  For example, the side length of the side surface of the semiconductor film 100 divided by forming the element dividing grooves by RIE using chlorine gas and argon plasma is about 3 to 7 μm. When the protective film 200 is partially etched, it is necessary to align the mask for exposing the resist. This alignment is performed while viewing the wafer from above through a microscope. When the side length of the side surface of the semiconductor film 10 is about 3 to 7 μm, the projected dimension of the side surface portion of the semiconductor film when the wafer is viewed from above is about 1.5 to 4.5 μm, and the mask alignment is performed. It becomes difficult. That is, a desired protective film cannot be obtained due to slight mask displacement.

For example, when etching the protective film 200 made of SiO ₂ , buffered hydrofluoric acid is generally used as an etchant. In this case, the etching rate depends on the film quality of SiO ₂ , the surface area with which the etchant is in contact, the environmental temperature, and the like, and has a width of about several nm / sec to several hundred nm / sec. Even if the etching rate is stably controlled to the maximum, in order to partially remove the protective film 200 on the side surface of the semiconductor film having the dimensions as described above, it is necessary to control the etching time in units of less than 1 second to several seconds. Become. In addition, etching that progresses in a short time from the etchant to lifting the wafer and cleaning it becomes a problem. Further, the etching of the protective film may proceed during cleaning due to the etchant remaining in the step structure of the device, and the protective film 200 may not be formed as intended. As described above, depending on the conventional method, it has been difficult to stably form a protective film having an appropriate pattern on the side surface of the semiconductor film due to a problem of processing accuracy by wet etching.

  The present invention has been made in view of the above points, and stably forms a protective film having a desired pattern on the side surface of a semiconductor film exposed by forming element dividing grooves for partitioning individual semiconductor light emitting devices. It is an object of the present invention to provide a semiconductor light emitting device and a method for manufacturing the same that can secure a high yield.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor light emitting device, comprising: forming a semiconductor film on a growth substrate; etching the semiconductor film from a main surface of the semiconductor film along an element dividing line; Forming an element dividing groove; and forming a protective film partially covering a side surface of the semiconductor film exposed by forming the element dividing groove and spaced apart from the growth substrate. The step of forming the element dividing groove includes a first etching step of etching the semiconductor film such that an inclination angle of an exposed surface with respect to the main surface of the semiconductor film has a first inclination angle; After the one etching step, the semiconductor film is etched so that an inclination angle of the exposed surface with respect to the semiconductor film has a second inclination angle larger than the first inclination angle. A second etching step of the inclination angle to form a different exposed surface, and comprising a.

  According to the method for manufacturing a semiconductor light emitting device according to the present invention, since the inclination angle of the etching surface is controlled in the etching performed when the element dividing groove (street) is formed, it is formed on the side surface of the semiconductor film. The protective film thus patterned can be easily patterned, and a high yield can be secured.

It is sectional drawing and a top view which show the structure of the conventional semiconductor light-emitting device. It is sectional drawing which shows the structure of the semiconductor light emission measure which concerns on Example 1 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor light-emitting device concerning Example 1 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor light-emitting device concerning Example 1 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor light-emitting device concerning Example 1 of this invention. It is sectional drawing which shows the structure of the semiconductor light emission measure which concerns on Example 2 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor light-emitting device based on Example 2 of this invention.

Embodiments of the present invention will be described below with reference to the drawings. In the drawings shown below, substantially the same or equivalent components and parts are denoted by the same reference numerals. In the following description, the present invention is applied to an LED made of Al _x In _y Ga _z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) as an example. The case will be described.

  FIG. 2 is a cross-sectional view illustrating the configuration of the semiconductor light emitting device 1 according to the first embodiment of the invention. The semiconductor light emitting device 1 has a so-called bonded structure, and a semiconductor film 20 including an n-GaN layer 21, an active layer 22, and a p-GaN layer 23 is bonded to a silicon substrate 80 as a support substrate. The semiconductor film 20 is bonded to the silicon substrate 80 by bonding the electrode layer 81 including a eutectic material formed on the silicon substrate 80 and the p-electrode 70. A growth substrate (not shown) such as a sapphire substrate used for the growth of the semiconductor film 20 is removed after the semiconductor film 20 is bonded to the silicon substrate 80. An n-electrode 71 is formed on the surface of the n-GaN layer 21 exposed by removing the growth substrate.

  The semiconductor film 20 has two side surfaces 30a and 30b having different inclination angles with respect to the main surface. That is, the semiconductor film 20 has a bending point A on the side surface of the n-GaN layer 21, and the inclination angle of the side surface 30a in the upper part from the bending point A with respect to the main surface of the semiconductor film 20 in FIG. It is relatively loose. On the other hand, the inclination angle of the side surface 30b of the lower part from the bending point A with respect to the main surface of the semiconductor film 20 is relatively steep as 40 to 45 °. The total length of the side of the side surface of the semiconductor film 20 having such a two-step tilt angle is 20 to 30 μm, and the projected dimension L of the side surface when viewed from the main surface direction of the semiconductor film 20 is 5 to 15 μm. It becomes. That is, the semiconductor light emitting device 1 according to this example has a sufficiently long projected dimension L as compared with the conventional structure (1.5 to 4.5 μm).

A protective film 50 made of an insulating material such as SiO ₂ is formed on the side surface of the semiconductor film 20. The protective film 50 plays a role such as preventing foreign matter from adhering to the semiconductor film 20. The protective film 50 is formed so as to cover a part of the upper surface of the p-GaN layer 23 and a part of the p-GaN layer 23, the active layer 22, and the n-GaN layer 21 on the side surface of the semiconductor film 20. The protective film 50 is formed so as to terminate on the side surface 30a where the inclination angle of the side surface of the n-GaN layer 21 is relatively gentle. The protective film 50 is formed before removing the growth substrate. If the protective film 50 covers the entire side surface of the semiconductor film 20 and is in contact with the growth substrate, cracks in the protective film 50 generated near the interface with the growth substrate when the growth substrate is removed by the LLO method. There is a risk that the peeling propagates to a portion covering the side surface of the semiconductor film 20. As in the present embodiment, the propagation of cracks during LLO can be prevented by terminating the protective film 50 on the side surface of the n-GaN layer 21 separated from the growth substrate. Such a patterning of the protective film 50 is performed by a photolithography technique with a normal accuracy by having the side surface of the semiconductor film 20 having a gentle inclination and sufficiently ensuring the length of the side of the side surface and the projection dimension L thereof. Can be used. In general, since the accuracy of photolithography is about 2 to 5 μm, in order to appropriately pattern the protective film 50 formed on the side surface of the semiconductor film 20, the projected dimension L of the side surface portion of the semiconductor film 20 is at least 5 μm. The above is desirable. Since the projected dimension L of the side surface of the semiconductor film 20 of the semiconductor light emitting device 1 according to the present invention is 5 to 15 μm as described above, it is possible to appropriately protect the side surface of the semiconductor film within the accuracy of existing photolithography technology. It is possible to pattern the film 50. The reason why the inclination angle of the side surface of the semiconductor film is in two stages is to achieve both the securing of the oblique side length and the shortening of the etching time of the semiconductor film, as will be described later.

  Next, a method for manufacturing the semiconductor light emitting device 1 having the above structure will be described. 3-5 is sectional drawing which shows the manufacturing method of the semiconductor light-emitting device 1 which is an Example of this invention.

(Semiconductor film formation process)
A sapphire substrate 10 is prepared for use as a semiconductor film growth substrate. The sapphire substrate 10 is heated at 1000 ° C. for 10 minutes in a hydrogen atmosphere to perform thermal cleaning of the sapphire substrate 10. Next, a semiconductor film 20 made of Al _x In _y Ga _z N is formed on the sapphire substrate 10 by MOCVD (metal organic chemical vapor deposition). Specifically, the substrate temperature is set to 500 ° C., TMG (trimethylgallium) (flow rate 10.4 μmol / min) and NH ₃ (flow rate 3.3 LM) are supplied for about 3 minutes, and a low-temperature buffer layer (not shown) made of GaN. Is formed on the sapphire substrate 10. Thereafter, the substrate temperature is raised to 1000 ° C. and held for about 30 seconds to crystallize the low-temperature buffer layer. Subsequently, while maintaining the substrate temperature at 1000 ° C., TMG (flow rate 45 μmol / min) and NH ₃ (flow rate 4.4LM) are supplied for about 20 minutes to form a base GaN layer (not shown) having a thickness of about 1 μm. . Next, at a substrate temperature of 1000 ° C., TMG (flow rate 45 μmol / min), NH ₃ (flow rate 4.4 LM) and SiH ₄ (flow rate 2.7 × 10 ⁻⁹ mol / min) as a dopant gas are supplied for about 120 minutes to obtain a film thickness. An n-GaN layer 21 of about 7 μm is formed. Subsequently, an active layer 22 is formed on the n-GaN layer 21. In this example, a multiple quantum well structure made of InGaN / GaN was applied as the active layer 22. That is, five cycles of growth are performed with InGaN / GaN as one cycle. Specifically, the substrate temperature is set to 700 ° C., TMG (flow rate 3.6 μmol / min), TMI (trimethylindium) (flow rate 10 μmol / min), NH ₃ (flow rate 4.4 LM) are supplied for about 33 seconds, and the film thickness is about A 2.2 nm InGaN well layer is formed, and then TMG (flow rate 3.6 μmol / min) and NH ₃ (flow rate 4.4 LM) are supplied for about 320 seconds to form a GaN barrier layer having a thickness of about 15 nm. The active layer 22 is formed by repeating this process for five cycles. Next, the substrate temperature was raised to 870 ° C., TMG (flow rate 8.1 μmol / min), TMA (trimethylaluminum) (flow rate 7.5 μmol / min), NH ₃ (flow rate 4.4 LM), and Cp ₂ Mg (bis -cyclopentadienyl Mg) (flow rate 2.9 × 10 ⁻⁷ μmol / min) is supplied for about 5 minutes to form a p-type AlGaN cladding layer (not shown) having a film thickness of about 40 nm. Subsequently, while maintaining the substrate temperature, TMG (flow rate 18 μmol / min), NH ₃ (flow rate 4.4 LM) and Cp ₂ Mg (flow rate 2.9 × 10 ⁻⁷ μmol / min) as a dopant were supplied for about 7 minutes, A p-GaN layer 23 having a thickness of about 150 nm is formed. A semiconductor film 20 composed of these layers is formed on the sapphire substrate 10 (FIG. 3A).

(First etching process)
Next, element dividing grooves (streets) for partitioning individual semiconductor light emitting devices are formed in the semiconductor film 20. The element dividing grooves (streets) 30 are formed by dry etching (RIE: reactive ion etching) of the semiconductor film 20 at different etching rates along the element dividing lines in the first etching process and the second etching process. .

  In RIE, high-frequency power is applied to a process gas to form a plasma state, and etching is performed with ions and radicals contained in the plasma. The object to be etched is placed on one side of the parallel plate electrode in the chamber, and by applying a voltage to the parallel plate electrode, ions are attracted to the object and collide with the object to perform etching. For this reason, etching by ions has anisotropy and is physically performed (anisotropic etching, physical etching). On the other hand, radical etching is caused by a chemical reaction and progresses more isotropically than ion etching (isotropic etching, chemical etching), although the degree varies depending on the object to be etched. Thus, RIE proceeds by simultaneously performing two types of etching with different properties. In the first etching step and the second etching step according to the present invention, the desired semiconductor film shape is obtained by adjusting the etching rate and the ratio of anisotropic etching and isotropic etching by adjusting each parameter. That is, if anisotropic etching is dominant, the inclination angle of the side surface of the semiconductor film formed by etching becomes steeper and the etching rate in the semiconductor stacking direction becomes higher. On the other hand, when the ratio of anisotropic etching decreases, the inclination angle of the side surface of the semiconductor film formed by etching becomes gentler, and the etching rate in the semiconductor stacking direction becomes lower.

In the first etching step, first, a resist material is applied to the surface of the p-GaN layer 23, and then the resist material is subjected to patterning corresponding to element dividing grooves (streets) by exposure / development processing to form a resist mask 40. . Next, the wafer is put into an RIE (reactive ion etching) apparatus, and the semiconductor film 20 exposed at the opening of the resist mask 40 is etched by dry etching using Cl ₂ plasma. The etching conditions in the first etching step were a process pressure of 1.0 Pa, an antenna power of 100 W, a bias power of 50 W, a Cl ₂ supply amount of 20 sccm, and a processing time of 280 seconds.

  Here, the process pressure refers to the pressure of the process gas in the processing chamber. When the process pressure is low, the movement direction of ions in the plasma easily aligns, so that the anisotropic etching (physical etching) component is included. As a result, the etching rate in the semiconductor film stacking direction increases, and the inclination angle of the side surface of the recess formed by etching becomes steep. The antenna power refers to high frequency power applied to an antenna provided in the RIE apparatus, and the process gas is brought into a plasma state by applying the antenna power. As the antenna power increases, the plasma density increases and the etching rate tends to increase. Further, when the antenna power is increased, a stable plasma state can be created even at a low process gas pressure. Bias power refers to high-frequency power applied to a substrate electrode having a mounting surface on which a wafer to be processed is placed in a processing chamber. By applying bias power, ions irradiated on the wafer are accelerated. Let The larger the bias power, the larger the anisotropic etching component and the higher the etching rate.

  According to the etching conditions described above, the etching rate of the semiconductor film 20 is relatively low at 2.5 nm / sec, and the angle formed between the side surface 30a of the groove 31 formed by this etching and the main surface of the semiconductor film 20 is 20 It becomes relatively loose at ˜25 °. Thus, in the first etching step, etching is performed at a relatively low etching rate, and the depth that does not reach the sapphire substrate 10 so that the side surface has a relatively gentle inclination angle along the element dividing line ( For example, 0.7 to 1 μm) grooves 31 are formed (FIG. 3B).

(Second etching process)
In the second etching process, dry etching is further performed at an etching rate higher than the etching rate in the first etching process to form element dividing grooves (streets) 30 reaching the sapphire substrate 10. The etching conditions in the second etching step were a process pressure of 0.2 Pa, an antenna power of 200 W, a bias power of 50 W, a Cl ₂ supply amount of 20 sccm, and a processing time of 1660 seconds. Under such etching conditions, the etching rate of the semiconductor film 20 is 3.5 nm / sec, which is higher than the etching rate in the previous first etching step. Further, the angle formed between the groove side surface 30b formed by etching in the second etching step and the main surface of the semiconductor film 20 is 40 to 45 °, which is steeper than the inclination angle in the previous first etching step. That is, by setting the process pressure as low as 1.0 Pa to 0.2 Pa, as described above, the rate at which anisotropic etching occurs was increased, and in particular, the etching rate in the semiconductor film stacking direction was accelerated. In addition, the antenna power was increased because it was difficult to maintain the plasma state when the pressure of the process gas decreased.

  By the two-stage etching process with different etching rates, the semiconductor film 20 has side surfaces 30a and 30b having different inclination angles with respect to the main surface, and the bending point A is formed on the side surface of the n-GaN layer 20. (FIG. 3C). In FIG. 3C, the side surface 30a of the portion below the bending point A of the semiconductor film 20 has an inclination angle (about 20 to 25 °) based on the etching rate in the first etching step. The side surface 30b of the upper part from the bending point A of the semiconductor film 20 has an inclination angle (about 40 ° to 45 °) based on the etching rate in the second etching step. The total length of the side of the semiconductor film 20 exposed by the two etching processes is 20 to 30 μm, and the projected dimension L when the side surface portion is viewed from the main surface direction of the semiconductor film 20 is 5 to 15 μm. Thus, it is greatly enlarged as compared with the conventional structure shown in FIG.

(Protective film formation process)
Next, a protective film 50 made of, for example, SiO ₂ is formed on the side surface of the semiconductor film 20 exposed by forming the element dividing grooves (streets) 30. The protective film 50 plays a role of protecting the semiconductor film 20 such as preventing foreign matters from adhering to the exposed surface of the semiconductor film 20. The protective film 50 is patterned so as to terminate at a position away from the sapphire substrate 10, that is, on the side surface of the n-GaN layer 21, so that cracks and peeling do not occur in the subsequent removal process of the sapphire substrate 10 by the LLO method. . For the patterning of the protective film 50, for example, a lift-off method can be used. Specifically, a resist material is applied to the entire surface of the semiconductor film 20, exposed and developed, and a resist mask 60 having a pattern corresponding to the pattern of the protective film 50 is formed. The resist mask 60 includes a part of the upper surface of the p-GaN layer 23 where the protective film 50 is not formed, a part of the side surface of the n-GaN layer 21 exposed by forming the element dividing groove (street) 30, and the sapphire substrate 10. It is formed so as to cover the top. In the exposure process for patterning the resist material, the wafer is observed from above through a microscope to align the mask that defines the exposed portion. As described above, the projection dimension L of the side surface of the semiconductor film 20 has a sufficient length as compared with the conventional case, so that the allowable range for mask displacement is expanded. In other words, the mask alignment for forming the resist mask 60 does not require high accuracy as in the case of the conventional structure, and appropriate patterning can be performed even with a normal level of accuracy.

Next, an SiO ₂ film constituting the protective film 50 is formed on the entire surface of the wafer by sputtering or the like (FIG. 4A). Thereafter, the protective film 50 is patterned by removing the resist mask 60 together with the unnecessary portion of the SiO ₂ film by a registry mover. In this way, on the side surface of the semiconductor film 20, the protective film 50 that covers a part of the p-GaN layer 23, the active layer 22, and the n-GaN layer 21 and is separated from the sapphire substrate 10 is formed.

(P electrode formation process)
Next, a resist mask corresponding to the pattern of the p electrode is formed on the surface of the p-GaN layer 23, and Pt (1 nm) / Ag (150 nm) / Ti (100 nm) / Au (by an electron beam evaporation method or the like). 200 nm) are sequentially deposited on the surface of the semiconductor film 20. The parentheses indicate the film thickness. Thereafter, by lifting off these metal films deposited on the resist mask, a p-electrode 70 having a function as a reflection layer is formed on the surface of the p-GaN layer 23 (FIG. 4B). The p-electrode 70 may be formed after the element dividing groove 30 is formed and before the protective film 50 is formed. In this case, a process such as covering the surface of the semiconductor film 20 with a resist is performed as necessary.

(Support substrate bonding process)
A silicon substrate 80 made of a silicon single crystal or the like used as a support substrate is prepared. Next, Pt (200 nm), Ti (1500 nm), Ni (500 nm), Au (100 nm), Pt (200 nm), and AuSn (1000 nm) are sequentially formed on the surface of the silicon substrate 80, thereby forming the eutectic material. An electrode layer 81 is formed. In addition to the silicon substrate, a metal substrate made of a Ge substrate, a GaAs substrate, Cu, or the like can be used as the support substrate.

  Next, the semiconductor film 20 and the silicon substrate 80 are brought into close contact with the p electrode layer 70 and the electrode layer 81 containing a eutectic material facing each other, and thermocompression bonded in a nitrogen atmosphere. The semiconductor film 20 and the silicon substrate 80 are joined by melting and solidifying the eutectic material contained in the electrode layer 81 on the silicon substrate 20 (FIG. 4C).

(Sapphire substrate removal process)
Next, the sapphire substrate 10 is peeled from the semiconductor film 20. For peeling off the sapphire substrate 10, an LLO (laser lift-off) method can be used. In the LLO method, the irradiated laser decomposes the GaN layer formed on the sapphire substrate 10 into metal Ga and N ₂ gas. For this reason, the above decomposition occurs in the n-GaN layer 21 in the semiconductor film, and the n-GaN layer 21 appears on the surface from which the sapphire substrate 10 is peeled off. Since the element dividing groove 30 formed in the semiconductor film 20 functions as an N ₂ gas emission path, element destruction can be prevented. Since the protective film 50 covering the side surface of the semiconductor film 20 is patterned so as to terminate at a position away from the sapphire substrate 10, cracks and peeling do not occur in the protective film 50 during LLO (FIG. 5 ( a)).

(N-electrode formation process)
Next, a resist mask corresponding to the pattern of the n electrode is formed on the surface of the n-GaN layer 21 exposed by peeling off the sapphire substrate 10, and Ti / Au or the like is deposited by electron beam evaporation or the like. . Thereafter, by lifting off these metal films deposited on the resist mask, an n-electrode 70 is formed on the surface of the n-GaN layer 21 (FIG. 5B).

(Element splitting process)
Next, the support substrate 80 exposed from the element dividing grooves 30 is divided along the element dividing grooves 30 by a laser scribing method or a dicing method or the like, and is divided into chips (FIG. 5C). The semiconductor light emitting device is completed through the above steps.

  When the inclination angle is moderated so as to ensure the length of the side surface of the semiconductor film 20, the film thickness of the outer edge portion of the semiconductor film 20 becomes thin. For this reason, there is a concern that the strength of this portion is reduced and cracks occur during LLO. Since the crack generated in the semiconductor film 20 also propagates to the protective film 50, it becomes a factor that deteriorates the yield of the semiconductor light emitting device. The semiconductor light emitting device 2 according to Example 2 has a structure in which the strength of the outer edge portion of the semiconductor film 20 is improved. Hereinafter, the semiconductor light emitting device 2 according to the second embodiment of the present invention will be described with respect to portions different from those of the first embodiment.

  FIG. 6 is a cross-sectional view showing the configuration of the semiconductor light emitting device 2 according to Example 2 of the invention. The side surface of the semiconductor film 20 is a convex curved surface, and the film thickness of the outer edge B of the semiconductor film 20 surrounded by a broken line in FIG. 6 is thicker than that in the case of the first embodiment. Thereby, the strength of the outer edge portion can be secured while securing the length of the side of the semiconductor film 20.

  The shape of the side surface of the semiconductor film 20 is as described above under the same etching conditions as in Example 1 above by devising the shape of the resist mask used for etching for forming the element dividing groove in the semiconductor film 20. A curved surface shape can be obtained. Hereinafter, of the manufacturing process of the semiconductor light emitting device 2 according to the second embodiment, portions different from the first embodiment will be mainly described with reference to FIG.

(Formation of thick film resist)
After forming the semiconductor film 20 including the n-GaN layer 21, the active layer 22, and the p-GaN layer 23 on the sapphire substrate 10, the surface of the semiconductor film 20 is about twice as thick as usual by spin coating ( For example, a resist material (for example, AZ6130 manufactured by Clariant Japan) is applied with a thickness of 12 μm. Next, heat treatment is performed at 90 ° C. for 120 seconds (first baking). Thereafter, the resist material is exposed at 250 mJ / cm ² using a predetermined mask. Next, the resist material is solidified by a heat treatment at 110 ° C. for 120 seconds (second baking). Thereafter, venting is performed for 50 minutes. Next, a developing process is performed using a developer (for example, AZ600MIF) to pattern the resist, thereby forming a resist mask 40a. Thereafter, heat treatment (third baking) is further performed at 130 ° C. for 20 minutes. As a result, the solidified resist is softened again, the outer edge portion of the resist mask 40a is tightened by heat shrinkage, the shoulder portion of the resist mask 40a is rounded, and the thickness of this portion is thicker than the other portions. . In this state, the resist is solidified again through the temperature lowering process, and a thick resist mask 40a is formed (FIG. 7A).

(First etching process)
After forming the resist mask 40a, the semiconductor film 20 is subjected to the etching conditions in the first etching process of Example 1 (process pressure 1.0 Pa, Ant power 100 W, bias power 50 W, Cl ₂ supply amount 20 sccm, processing time 280 seconds). Etching is performed. At this time, since the shoulder portion of the resist mask 40a is a curved surface and the film thickness is thicker than other portions, the etching resistance of the resist shoulder portion is improved as compared with the other portions. For this reason, the side etching of the peripheral part of the resist mask 40a gradually proceeds, and the side etching of the semiconductor film 20 that appears sequentially immediately below the resist mask 40a also moderates. As a result, the etching rate in the horizontal direction becomes slower than the etching rate in the depth direction of the semiconductor film 20, and the side surface of the semiconductor film 20 exposed by the etching becomes a curved surface. In the first etching step, the etching rate is relatively low, and the inclination angle of the side surface of the semiconductor film 20 is gentle. In the first etching step, a groove having a depth (for example, 0.7 to 1 μm) reaching the n-GaN layer 21 and not reaching the sapphire substrate 10 is formed (FIG. 7B).

(Second etching process)
Next, the semiconductor film 20 is etched under the etching conditions in the second etching step of Example 1 (process pressure 0.2 Pa, Ant power 200 W, bias power 50 W, Cl ₂ supply amount 20 sccm, processing time 1660 seconds). Then, an element dividing groove (street) 30 reaching from the surface of the semiconductor film 20 to the sapphire substrate 10 is completed. The inclination angle of the groove formed by this etching is steeper than the inclination angle in the previous first etching step. That is, the bending point A is formed in the n-GaN layer 20 by two-stage etching processes with different etching rates. A portion below the bending point A of the semiconductor film 20 has an inclination angle based on the etching rate in the first etching step, and the curved surface shape is substantially maintained as it is. The portion above the bending point A has an inclination angle based on the etching rate in the second etching step. The projected dimension of the side surface portion of the semiconductor film 20 exposed by two etching processes with different etching rates is 5 to 15 μm, which is greatly enlarged as compared with the conventional structure shown in FIG. 1 (FIG. 7C). . Further, since the side surface of the semiconductor film 20 has a curved shape, the film thickness of the outer edge portion B surrounded by the broken line in FIG. 7C can be increased, and the strength of this portion can be increased.

  As described above, in the method for manufacturing a semiconductor light emitting device according to the present invention, the first etching process for etching the semiconductor film at a relatively low etching rate and the second etching process for etching the semiconductor film at a relatively high etching rate. The element dividing groove 30 is formed by two-stage etching. In the first etching step, by making the etching rate relatively low, the inclination angle of the side surface of the semiconductor film 20 (n-GaN layer 21) becomes gentle, and the side length of the side surface of the semiconductor film 20 can be secured. It becomes possible. According to the manufacturing method of the present invention, the projected dimension of the side surface portion of the semiconductor film when viewed from the main surface direction of the semiconductor light emitting device is 5 to 15 μm, and the dimension when using the conventional etching method (1.5 to 4). Longer than 5 μm). As a result, the resist patterning on the side surface of the semiconductor film can be easily performed with the accuracy of the existing photolithography technique, and the appropriate protective film can be patterned with a normal level of processing accuracy. That is, on the side surface of the semiconductor film 20, the p-GaN layer 23, the active layer 22, and the n-GaN layer 21 are partially covered, and the protective film that is separated from the sapphire substrate 10 is easily patterned. This makes it possible to improve the yield of the semiconductor light emitting device.

  In the embodiment described above, the element dividing groove is formed by two-stage etching, but it is also possible to form the element dividing groove only by etching at a low etching rate. However, in this case, the semiconductor film is exposed to plasma for a long time, which may adversely affect the characteristics. Contrary to the above-described embodiment, it is also possible to form the element dividing groove by etching the semiconductor film 20 at a relatively high etching rate and then etching the semiconductor film 20 at a relatively low etching rate. is there. In this case, the same side shape (tilt angle) as that of the above-described embodiment can be obtained. However, finally, in order to obtain a desired tilt angle at a low etching rate, the semiconductor film is exposed to plasma for a long time, which may adversely affect the characteristics, which is not preferable. In this embodiment, the etching is first performed at a low etching rate to obtain a desired inclination angle on the side surface of the semiconductor film 20, and then the element dividing groove is completed by etching at a high etching rate. Thus, it is possible to shorten the time during which the surfaces of the p-GaN layer 23 and the active layer 22 that are exposed are exposed to plasma. That is, in the etching for forming the element dividing groove 30, by performing the etching in the order of low etching rate and high etching rate, the inclination angle of the side surface of the semiconductor film is made gentle and the semiconductor film by plasma during etching Damage can be suppressed, and the total etching processing time can be shortened.

  In the above embodiment, the protective film 50 is patterned by the lift-off method. However, the patterning can also be performed by photolithography / etching. In this case, after forming the protective film 50 on the surface of the semiconductor film 20, a resist mask having a pattern opposite to that in the lift-off is formed on the surface of the protective film 50, and the protective film exposed at the opening of the resist mask. 50 is etched with buffered hydrofluoric acid to pattern the protective film. According to the manufacturing method according to the present invention, even if the patterning is performed by such wet etching, the side length of the side surface of the semiconductor film 20 is sufficiently secured. There is nothing. That is, when patterning the protective film 50 by wet etching, a desired pattern can be stably obtained without requiring strict management of etching conditions.

DESCRIPTION OF SYMBOLS 10 Sapphire substrate 20 Semiconductor film 21 n-GaN layer 22 Active layer 23 p-GaN layer 30 Element division groove (street)
40 resist mask 50 protective film 70 p-electrode 71 n-electrode 80 support substrate

Claims (10)

Forming a semiconductor film on a growth substrate;
Etching the semiconductor film from the main surface of the semiconductor film along an element dividing line to form an element dividing groove in the semiconductor film;
Forming a protective film partially covering a side surface of the semiconductor film exposed by forming the element dividing groove and spaced apart from the growth substrate,
The step of forming the element dividing groove includes a first etching step of etching the semiconductor film such that an inclination angle of an exposed surface with respect to the main surface of the semiconductor film has a first inclination angle, and the first etching. After the step, the semiconductor film is etched to form exposed surfaces having different inclination angles so that the inclination angle of the exposed surface with respect to the semiconductor film by etching has a second inclination angle larger than the first inclination angle. A method of manufacturing a semiconductor light emitting device, comprising: a second etching step.   The manufacturing method according to claim 1, wherein an etching rate in the first etching step is lower than an etching rate in the second etching step.   The projected dimension when the side surface of the semiconductor film exposed by forming the element dividing groove is viewed from the main surface direction of the semiconductor film is 5 μm or more. The manufacturing method as described.   The step of forming the protective film includes forming a resist mask that partially covers a side surface of the semiconductor film exposed by forming the element dividing groove, and patterning the protective film using the resist mask. The manufacturing method according to claim 1, further comprising a step. The first and second etching steps include a step of etching the semiconductor film through a resist mask formed on the surface of the semiconductor film,
The manufacturing method according to claim 1, wherein the resist mask has a thicker outer peripheral portion than the other portions.   The manufacturing method according to claim 5, wherein the resist mask is formed through a plurality of heat treatments. Forming an electrode on the surface of the semiconductor film;
Bonding the semiconductor film and the support substrate through the electrodes;
The method according to claim 1, further comprising a step of peeling the growth substrate from the semiconductor film. A first semiconductor layer having a first conductivity type, a second semiconductor layer having a second conductivity type different from the first conductivity type, and an activity formed between the first and second semiconductor layers A semiconductor light-emitting device comprising: a semiconductor film including a layer; and a protective film covering at least a part of a side surface of the semiconductor film,
The semiconductor film is characterized in that an inclination angle with respect to a main surface of the semiconductor film is changed on a side surface thereof, and the protective film terminates on an inclined surface with a relatively low inclination angle. Light emitting device.   9. The semiconductor light emitting device according to claim 8, wherein a projected dimension when a side surface of the semiconductor film is viewed from a main surface direction of the semiconductor film is 5 μm or more.   The semiconductor light-emitting device according to claim 8, wherein a side surface of the semiconductor film is a convex curved surface.

Images