CN104576310B - The preparation method for being aligned and turning on applied to semiconductor back surface - Google Patents

The preparation method for being aligned and turning on applied to semiconductor back surface Download PDF

Info

Publication number
CN104576310B
CN104576310B CN201310484907.5A CN201310484907A CN104576310B CN 104576310 B CN104576310 B CN 104576310B CN 201310484907 A CN201310484907 A CN 201310484907A CN 104576310 B CN104576310 B CN 104576310B
Authority
CN
China
Prior art keywords
semiconductor
light
film layer
etching
photo
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201310484907.5A
Other languages
Chinese (zh)
Other versions
CN104576310A (en
Inventor
李伟峰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Original Assignee
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huahong Grace Semiconductor Manufacturing Corp filed Critical Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority to CN201310484907.5A priority Critical patent/CN104576310B/en
Publication of CN104576310A publication Critical patent/CN104576310A/en
Application granted granted Critical
Publication of CN104576310B publication Critical patent/CN104576310B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Landscapes

  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention discloses a kind of preparation method for being aligned and turning on applied to semiconductor back surface, including:1)Light-transmissive film layer is grown in the semiconductor back surface of offer;2)In semiconductor front photo-etching mark is made with photoetching process;3)With etch process etch step 2)In photo-etching mark, until with step 1)The light-transmissive film layer of growth is as stop-layer, and etch away sections light-transmissive film layer, the photo-etching mark formed after etching;4)In photo-etching mark after etching, material filling is carried out, back side photo-etching mark is formed with this;5)Semiconductor front is surface-treated, adhering wafers carrier;6)Local process processing is carried out using back process, conductive photo-etching mark is opened;7)Metal material is filled in conductive photo-etching mark, surface metal material is handled, it is ensured that do not have metal residual on light-transmissive film layer overleaf.The present invention can effectively improve the register effects in back process, prevents back pollution, can also produce safe conductive through hole.

Description

The preparation method for being aligned and turning on applied to semiconductor back surface
Technical field
The present invention relates to the semiconductor making method in a kind of microelectronic chip manufacture field, more particularly to a kind of application The preparation method for being aligned and turning in semiconductor back surface.
Background technology
In the semiconductor fabrication of some special process, alignment issues are often a difficulty but have to improve The problem of, it is even more so in semiconductor back surface technique.
The existing back side is all directly to make photo-etching mark with photoetching process in the front of semiconductor with photo-etching mark;Then These photo-etching marks are directly cut through, or etching these photo-etching marks to certain depth, i.e., are not cut through;Secondly in these marks Certain material is filled in note;Then semiconductor front is surface-treated, adhering wafers carrier, then carries out follow-up back side work Skill.Wherein, the photo-etching mark cut through is used directly for the alignment of back process;Photo-etching mark is etched to certain depth, then Need to first pass through other techniques, etching or the technique such as sawing semiconductor back surface is carried out thinning with exposure as described in photoetching mark Note, is used further to the alignment of back process(Such as Figure 1A~Fig. 1 E).
However, although existing process improves the alignment issues of back process, but some other problem is also created simultaneously: Such as it is filled for the photo-etching mark cut through and goes back imperfection, the terminal part for also having these alignment marks is all directly exposed to In air, easily cause the pollution of product.
The content of the invention
The technical problem to be solved in the present invention is to provide a kind of preparation method for being aligned and turning on applied to semiconductor back surface. The problem of improving semiconductor back surface technique misregistration by this method, uses while being also used as conductive through hole.
In order to solve the above technical problems, the preparation method for being applied to semiconductor back surface alignment and conducting of the present invention, including Step:
1)A light-transmissive film layer is grown in the semiconductor back surface of offer;
2)In semiconductor front photo-etching mark is made with photoetching process;
3)With etch process etch step 2)In photo-etching mark, until with step 1)The light-transmissive film layer of growth is used as stopping Layer, and etch away sections light-transmissive film layer, the photo-etching mark formed after etching;
4)In step 3)In photo-etching mark after the etching of formation, material filling is carried out, the back of the body of the present invention is formed with this Face photo-etching mark;
5)Semiconductor front is surface-treated, adhering wafers carrier, to carry out follow-up back process;
6)Local process processing is carried out using back process, conductive photo-etching mark is opened;
7)Metal material is filled in conductive photo-etching mark, surface metal material is handled, it is ensured that printing opacity overleaf There is no metal residual in film layer.
The step 1)In, semiconductor includes:Single-chip, multichip semiconductor chip or the electronics member with semiconductor property Part;Wherein, the electronic component with semiconductor property includes:With semiconductor technology or semiconductor subassembly electronic component Deng;
The light-transmissive film layer is that to meet the etching rate and semiconductor of light-transmissive film layer material itself by one or more variant (Particularly there is larger difference)And the light-transmitting materials with preferable insulating properties are constituted(If light-transmissive film layer is by SiO2Film institute Constitute), the thickness of light-transmissive film layer can be more than 400 angstroms;Growing the method for a light-transmissive film layer includes:Precipitated using the back side, film is given birth to It is long or precipitated by the back side, the method that film growth is combined with grinding carries out growing a light-transmissive film layer.
The step 2)In, photo-etching mark includes:The alignment mark of the standard set for certain type board, some its His alignment mark(Alignment mark etc.)Or for doing the mark of conduction.
The step 3)In, the partial light permeability film layer etched away refers to after the substrate of semiconductor has been etched, and continues saturating Etch depth in light film layer, wherein, the etch depth in light-transmissive film layer can be 200 angstroms of thickness less than light-transmissive film layer Degree.
The step 4)In, it is the material for having larger difference with the substrate material of semiconductor to carry out the material in material filling Matter, including:The material of insulator, various metals or metal alloy etc.;Such as, the material in the carry out material filling can be by The material that one or more substrate materials with semiconductor have larger difference is constituted.
The step 5)In, surface treatment refers to deal with to having filled the semiconductor front after material, including:Return at quarter Reason, planarization process or surface cleaning processing etc., can use back the techniques such as quarter if desired for the original front pattern of guarantee, such as Ensure that with what is preferably planarized planarization technology can be used, also just like techniques such as surface cleaning;
In the adhering wafers carrier, carrier adhesive and chip carrier are generally comprised;The carrier adhesive can make Radiated and engaged with UV;The back process includes:Back side photoetching, etching, backside particulate injection, the long film in the back side and back side thinning Deng.
The step 6)In, local process processing includes:It is real by photoetching, etching technics or other micro- technique such as laser etc. The conducting of existing semiconductor back surface conduction photo-etching mark.
The step 7)In, metal material is made up of one or more metal materials, preferably positive with semiconductor Conducting metal identical metal is filled, has preferable conduction to meet both joints;The loading for filling metal material is big In or equal to the depth of conduction photo-etching mark opened;The method of processing surface metal material includes:Mechanical processing, change Learn mechanical treatment or return carving technology processing.
The present invention is to utilize some special materials(Such as the good material of light transmittance)And etching rate between unlike material Difference and propose it is a kind of can apply semiconductor back surface be aligned process.Offer semiconductor back surface precipitation or Grow certain thickness film layer, the film layer material need with good translucency and during growth planarization it is preferable, will also be with this Semiconductor rear substrate material has larger rate of etch poor, thus can using the film layer as next step etching stop-layer; Then photo-etching mark is made using photoetching process in semiconductor front, these marks include alignment mark and are used as conductive mark Note;These marks are etched with etch process, until using the film layer that grows before as stop-layer, and are etched into wherein certain Thickness is best;Then insert metal in the mark of these etchings or some other and Semiconductor substrate material has larger difference Different material, forms the back side photo-etching mark of the present invention with this;Then it is surface-treated in semiconductor front, adhering wafers Carrier, can carry out back process;Further, overleaf handled in technique by local process, open and fill conduction Mark, can be such that these marks are used as conductive through hole.It is described above, after tunic layer is added, at this partly During conductor back side photoetching process, because of described photo-etching mark, the alignment essence of back side photoetching process can be both substantially improved Degree(Light-transmitting materials), again can be using the film layer as the insulating barrier with positive surface semiconductor, these are all produced to whole back process Very big benefit, is even more to serve very big optimization to insulating properties, the security of whole device.
Therefore, the present invention can effectively improve the register effects in back process, prevents back pollution, can also produce safe Conductive through hole.
Brief description of the drawings
The present invention is further detailed explanation with embodiment below in conjunction with the accompanying drawings:
Figure 1A is the photo-etching mark schematic diagram in photoetching process;
Figure 1B -1,1B-2 are the photo-etching mark schematic diagrames in etching technics;
Fig. 1 C-1,1C-2 are to carry out the schematic diagram after material filling;
Fig. 1 D-1,1D-2 are the schematic diagrames after adhering wafers carrier;
Fig. 1 E are the schematic diagrames that mark is exposed through back side thinning;
Fig. 2 is that the back side of the present invention grows the schematic diagram of light-transmissive film layer;
Fig. 3 is the photo-etching mark schematic diagram in the photoetching process of the present invention;
Fig. 4 is the photo-etching mark schematic diagram in the etching technics of the present invention;
Fig. 5 is the schematic diagram after the carry out material filling of the present invention;
Fig. 6 is the schematic diagram after the adhering wafers carrier of the present invention;
Fig. 7 be the present invention back side photoetching and etching technics after schematic diagram;
Fig. 8 is the schematic diagram after the back side filling and surface treatment of the present invention.
Description of reference numerals is as follows in figure:
1 is Semiconductor substrate, and 2 be the first technique film layer, and 3 be the second technique film layer, and 4 be the 3rd technique film layer, and 5 be photoetching Glue, 6 be the photo-etching mark in photoetching process, and 7 be semiconductor subassembly, and 8 be the photo-etching mark in etching technics, and 9 be to be filled Material, 10 be adhesive, and 11 be chip carrier, 12 for exposure mark;
20 be semiconductor subassembly of the invention, and 21 be Semiconductor substrate, and 22 be the first technique film layer of the invention, and 23 be this Second technique film layer of invention, 24 be the 3rd technique film layer of the invention, and 25 be light-transmissive film layer, and 26 be photoresist of the invention, 27 be the photo-etching mark in the etching technics of the present invention, and 28 be the material being filled of the invention, and 29 be the carrier of the present invention Adhesive, 30 be chip carrier of the invention, 31 metal material to be filled.
Embodiment
The present invention's is applied to the preparation method that semiconductor back surface is aligned and turned on, including step:
1)A light-transmissive film layer 25 is grown in the semiconductor back surface of offer(As shown in Figure 2);
Wherein, semiconductor includes:Single-chip, multichip semiconductor chip or the electronic component with semiconductor property;Wherein, have The electronic component for having semiconductor property includes:With semiconductor technology or semiconductor subassembly electronic component etc.;Used in Fig. 2 Semiconductor be a kind of semiconductor subassembly 20;
Light-transmissive film layer 25 is that a kind of have preferable light-transmissive and the etching rate and semiconductor of film layer material itself has Difference(Particularly there is larger difference)And the film layer with preferable insulating properties, such as can be to meet light-transmissive film by one or more Itself material of the etching rate and semiconductor of layer is variant(Particularly there is larger difference)And the printing opacity material with preferable insulating properties What matter was constituted(If light-transmissive film layer 25 is the oxidation film commonly used in semiconductor manufacturing, such as SiO2Film is constituted, SiO2With saturating Good and larger with the rate of etch of the semiconductor back surface material benefit of photosensitiveness).
The thickness of light-transmissive film layer 25, it is impossible to too thin, otherwise can not play a part of stop-layer, such as can be more than 400 angstroms, excellent Elect 2000 angstroms as;
Growing the method for a light-transmissive film layer 25 includes:Precipitated using the back side, film grows or precipitated by the back side, film growth is with grinding Grind the method being combined and carry out one light-transmissive film layer 25 of growth, for example, using the planarization such as back side precipitation or film growth preferably side Method grows film layer, even and if or using back side precipitation or film growth of planarization bad method and combining the methods such as grinding and realizing The growing film layer method of planarization.
Step 1)In, by the way that there is larger rate of etch as principal character using light-transmissive and with Semiconductor substrate material Light-transmissive film layer, can effectively solve the problems, such as through hole filling imperfection and back pollution.
2)In semiconductor front photo-etching mark is made with photoetching process(As shown in Figure 3);
Wherein, photo-etching mark includes:The standard set for certain type board alignment mark (such as ASML, NIKON, The boards such as CANON), some other alignment marks(Alignment mark etc.)Or for doing the mark of conduction(Through leading for semiconductor Electric through-hole etc.).
3)With etch process etch step 2)In photo-etching mark, until with step 1)The light-transmissive film layer of growth is used as stopping Layer, and etch away sections light-transmissive film layer 25, the photo-etching mark 27 formed after etching(As shown in Figure 4);
Wherein, the partial light permeability film layer 25 etched away refers to after Semiconductor substrate 21 has been etched, and continues in light-transmissive film layer Etch depth in 25, wherein, the etch depth in light-transmissive film layer 25 can be 200 angstroms of thickness less than light-transmissive film layer 25 Degree.If total etch amount is 1000 angstroms.
4)In step 3)In photo-etching mark after the etching of formation, carry out material 28 and fill, form the present invention's with this Back side photo-etching mark or conductive through hole(As shown in Figure 5);
Wherein, material 28 is the material for having larger difference with the material of substrate 21 of semiconductor, including:The material of insulator (Such as oxide), various metals(Such as tungsten)Or metal alloy(Such as metallic compound)Deng;Such as, the material 28 can be by one kind Or the material that a variety of materials of substrate 21 with semiconductor have larger difference is constituted, such as material 28 is the material by insulator with leading Electric metal constitutes or is directly made up of a kind of metal or certain metal alloy(It is usually coated in photo-etching mark 27 i.e. first after etching The material of insulator, which is refilled, leads electric metal, also or directly fills a kind of metal or certain metal alloy).
5)Semiconductor front is surface-treated, adhering wafers carrier 30 as one kind, to carry out follow-up back process(Such as Fig. 6 It is shown);
Wherein, surface treatment refers to deal with to having filled the semiconductor front after material, including:Return quarter processing, plane Change processing or surface cleaning processing etc., can use back the techniques such as quarter if desired for the original front pattern of guarantee, such as to ensure tool There is what is preferably planarized can use planarization technology, also just like techniques such as surface cleaning;
In the adhering wafers carrier, carrier adhesive 29 and chip carrier 30 are generally comprised;The carrier adhesive 29 UV can be used to radiate and engage;The effect of the chip carrier 30 is:Play outside protection front pattern, mainly permit holding Row technique for manufacturing back;
The back process includes:Back side photoetching, etching, backside particulate injection, the long film in the back side and back side thinning etc..
6)Local process processing is carried out using back process, conductive photo-etching mark is opened(As shown in Figure 7), made with this Used for conductive through hole;
Wherein, local process processing refers to realize semiconductor by photoetching, etching technics or other micro- technique such as laser etc. The conducting of back side conduction photo-etching mark.
7)Metal material is filled in conductive photo-etching mark(Such as tungsten)31, by mechanically handling, at chemical machinery Reason returns the methods such as carving technology processing, handles surface metal material, it is ensured that do not have metal residual on light-transmissive film layer 25 overleaf, So as not to influence the alignment precision of follow-up back process(As shown in Figure 8).
Wherein, metal material 31 is made up of one or more metal materials, is preferably led with the positive filling of semiconductor Electric metal identical metal(Such as tungsten)(Such as step 4)In metal), have preferable conduction to meet both joints;Filling The loading of metal material 31 is more than or equal to the depth of opened conduction photo-etching mark.
The present invention in semiconductor back surface by growing a film layer(With good translucency), pass through positive photoetching and etching Technique directly etches into alignment mark in the film layer and fills material, and the back side photo-etching mark of the present invention is formed with this. Further, overleaf handled in technique by local process, open and fill metal material to some conductive photoetching Mark, can be such that these marks are used as conductive through hole.Therefore, the present invention can improve the alignment of semiconductor back surface technique not It is good, while being also prevented from back pollution, produce the conductive through hole of safety.

Claims (10)

1. a kind of preparation method for being aligned and turning on applied to semiconductor back surface, it is characterised in that including step:
1)A light-transmissive film layer is grown in the semiconductor back surface of offer;The light-transmissive film layer is a kind of with good light permeability and surface Planarization performance, and light-transmissive film layer etching rate and semiconductor material itself be variant and film layer with good insulation properties;
2)In semiconductor front photo-etching mark is made with photoetching process;
3)With etch process etch step 2)In photo-etching mark, until with step 1)The light-transmissive film layer of growth as stop-layer, And etch away sections light-transmissive film layer, the photo-etching mark formed after etching;
4)In step 3)In photo-etching mark after the etching of formation, material filling is carried out, back side photo-etching mark is formed with this;
5)Semiconductor front is surface-treated, adhering wafers carrier, to carry out follow-up back process;
6)Local process processing is carried out using back process, conductive photo-etching mark is opened;
7)Step 6)Conductive photo-etching mark in fill metal material, processing surface metal material, it is ensured that overleaf saturating There is no metal residual in light film layer.
2. the method as described in claim 1, it is characterised in that:The step 1)In, semiconductor includes:Single-chip, semiconductor Multi-wafer or the electronic component with semiconductor property;Wherein, the electronic component with semiconductor property includes:With semiconductor Technique or semiconductor subassembly electronic component;
The light-transmissive film layer is by one or more etching rates for meeting light-transmissive film layer and semiconductor material itself be variant and tool What the light-transmitting materials for having insulating properties were constituted;The thickness of light-transmissive film layer is more than 400 angstroms;
Growing the method for a light-transmissive film layer includes:Precipitated using the back side, film is grown or precipitated by the back side, film growth is mutually tied with grinding The method of conjunction carries out one light-transmissive film layer of growth.
3. method as claimed in claim 2, it is characterised in that:The light-transmissive film layer is by SiO2Film is constituted.
4. the method as described in claim 1, it is characterised in that:The step 2)In, photo-etching mark includes:Set for board Standard alignment mark, alignment mark or for do conduction mark.
5. the method as described in claim 1, it is characterised in that:The step 3)In, the partial light permeability film layer etched away refers to After the substrate of semiconductor has been etched, continue the etch depth in light-transmissive film layer, wherein, the etch depth in light-transmissive film layer For 200 angstroms of thickness less than light-transmissive film layer.
6. the method as described in claim 1, it is characterised in that:The step 4)In, carry out material filling in material be by What one or more discrepant materials of substrate material with semiconductor were constituted, including:Material, metal or the gold of insulator Belong to alloy.
7. the method as described in claim 1, it is characterised in that:The step 5)In, surface treatment refers to having filled material Semiconductor front afterwards is dealt with, including:Return quarter processing, planarization process or surface cleaning processing;
In the adhering wafers carrier, carrier adhesive and chip carrier are included;The carrier adhesive is radiated and connect using UV Close;
The back process includes:Back side photoetching, etching, backside particulate injection, the long film in the back side and back side thinning.
8. the method as described in claim 1, it is characterised in that:The step 6)In, local process processing includes:Pass through light Quarter, etching technics or laser realize the conducting of semiconductor back surface conduction photo-etching mark.
9. the method as described in claim 1, it is characterised in that:The step 7)In, metal material is by one or more gold Category material is constituted;
The loading for filling metal material is more than or equal to the depth of opened conduction photo-etching mark;
The method for handling surface metal material, including:Mechanical processing, chemical mechanical processing return carving technology processing.
10. method as claimed in claim 9, it is characterised in that:The metal material is conductive with the positive filling of semiconductor Metal identical metal.
CN201310484907.5A 2013-10-16 2013-10-16 The preparation method for being aligned and turning on applied to semiconductor back surface Active CN104576310B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310484907.5A CN104576310B (en) 2013-10-16 2013-10-16 The preparation method for being aligned and turning on applied to semiconductor back surface

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310484907.5A CN104576310B (en) 2013-10-16 2013-10-16 The preparation method for being aligned and turning on applied to semiconductor back surface

Publications (2)

Publication Number Publication Date
CN104576310A CN104576310A (en) 2015-04-29
CN104576310B true CN104576310B (en) 2017-08-08

Family

ID=53092101

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310484907.5A Active CN104576310B (en) 2013-10-16 2013-10-16 The preparation method for being aligned and turning on applied to semiconductor back surface

Country Status (1)

Country Link
CN (1) CN104576310B (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107658290B (en) * 2017-09-26 2020-07-31 上海华虹宏力半导体制造有限公司 Method for forming photoetching alignment mark
CN108899302A (en) * 2018-07-04 2018-11-27 南通沃特光电科技有限公司 A kind of back-illuminated type CMOS sensor singualtion method
CN109559981B (en) * 2018-09-26 2020-11-20 厦门市三安集成电路有限公司 Method for solving problem that high-transmittance wafer cannot be identified in photoetching alignment
CN109534283B (en) * 2018-11-15 2020-09-25 赛莱克斯微系统科技(北京)有限公司 Micro-electro-mechanical device preparation method and device
CN113295500A (en) * 2021-06-29 2021-08-24 上海华力微电子有限公司 Preparation method of transmission electron microscope planar sample

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5640053A (en) * 1994-07-01 1997-06-17 Cypress Semiconductor Corp. Inverse open frame alignment mark and method of fabrication
CN101034663A (en) * 2006-03-07 2007-09-12 国际商业机器公司 Method and structure for improved alignment in mram integration
CN103050480A (en) * 2012-08-14 2013-04-17 上海华虹Nec电子有限公司 Technical method for imaging rear side of silicon wafer
CN103165442A (en) * 2011-12-12 2013-06-19 上海华虹Nec电子有限公司 Back side graphical method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5640053A (en) * 1994-07-01 1997-06-17 Cypress Semiconductor Corp. Inverse open frame alignment mark and method of fabrication
CN101034663A (en) * 2006-03-07 2007-09-12 国际商业机器公司 Method and structure for improved alignment in mram integration
CN103165442A (en) * 2011-12-12 2013-06-19 上海华虹Nec电子有限公司 Back side graphical method
CN103050480A (en) * 2012-08-14 2013-04-17 上海华虹Nec电子有限公司 Technical method for imaging rear side of silicon wafer

Also Published As

Publication number Publication date
CN104576310A (en) 2015-04-29

Similar Documents

Publication Publication Date Title
CN104576310B (en) The preparation method for being aligned and turning on applied to semiconductor back surface
CN105849891B (en) Reduce the warpage in the structure with circuit
KR100743648B1 (en) Method of manufacturing wafer level system in packge
US10236273B2 (en) Packaging structure including interconnecs and packaging method thereof
CN104157749B (en) ITO film preparation method and LED chip preparation method
CA2406054A1 (en) Method of forming vias in silicon carbide and resulting devices and circuits
CN101252121A (en) Stack package and method of manufacturing the same
CN102709200A (en) Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief
KR102530758B1 (en) Semiconductor light emitting device package
CN109920757A (en) A kind of dorsal segment technique improving compound semiconductor device unfailing performance
TWI313912B (en) Method for separating package of wlp
WO2021093238A1 (en) Metal lead, semiconductor device and fabrication method therefor
CN104795481B (en) Light emitting diode and preparation method thereof
CN108470714A (en) Dual damascene process method
CN103854972A (en) Method for mitigating surface warpage of wafer
CN109545805A (en) A kind of semiconductor chip packaging method
CN111987195A (en) LED chip structure for enhancing eutectic thrust and manufacturing process thereof
CN107342256A (en) Semiconductor technology and semiconductor structure
CN107808853B (en) A kind of fingerprint chip-packaging structure and production method, terminal device
CN107093579A (en) Semiconductor wafer level packaging methods, device and encapsulation cutter
CN104752342B (en) The method for engaging semiconductor substrate
CN116053368A (en) Red light LED chip with ZnO sacrificial layer and manufacturing method thereof
CN104600027B (en) A kind of preparation technology of TSV through hole
CN107086177A (en) Semiconductor wafer level packaging methods and semiconductor wafer level packaging methods cutter
WO2005101494A3 (en) Three dimensional six surface conformal die coating

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant