CN109534283B - Micro-electro-mechanical device preparation method and device - Google Patents
Micro-electro-mechanical device preparation method and device Download PDFInfo
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- CN109534283B CN109534283B CN201811356928.8A CN201811356928A CN109534283B CN 109534283 B CN109534283 B CN 109534283B CN 201811356928 A CN201811356928 A CN 201811356928A CN 109534283 B CN109534283 B CN 109534283B
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- 238000004519 manufacturing process Methods 0.000 claims description 20
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- 238000001259 photo etching Methods 0.000 claims description 5
- 230000007306 turnover Effects 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000011049 filling Methods 0.000 claims description 2
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- 238000000708 deep reactive-ion etching Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
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- 230000004075 alteration Effects 0.000 description 1
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- 238000002347 injection Methods 0.000 description 1
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00134—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems comprising flexible or deformable structures
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00198—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems comprising elements which are movable in relation to each other, e.g. comprising slidable or rotatable elements
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
- B81C1/00238—Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
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Abstract
The invention discloses a method and a device for preparing a micro-electromechanical device, comprising the following steps: preparing an alignment mark on the back of a first wafer substrate; preparing a conductive channel on the back surface of the first wafer substrate by using the alignment mark as an alignment reference; turning over the first wafer substrate, and preparing an electrode window and a deflectable element on the front surface of the first wafer substrate by using a back-to-front alignment technology by using the alignment mark as an alignment reference; and turning the first wafer substrate, and preparing an electrode control circuit electrically connected with the conductive channel on the back surface of the first wafer substrate by using the alignment mark as an alignment reference. The scheme provided by the invention improves the technical problems that the processing of the two sides of the wafer in the prior art has larger alignment error, reduces the yield and brings hidden troubles to the quality and reliability of devices. The alignment precision can be effectively improved, and the yield and the device quality can be improved.
Description
Technical Field
The invention relates to the technical field of semiconductor processes, in particular to a preparation method and a device of a micro-electromechanical device.
Background
As semiconductor devices become more complex, semiconductor processes become more complex, and in order to control the size of the devices, some processes often require processing on both the back and front sides of the wafer. For example a sensor structure comprising a movable element.
The existing process is adopted to process the two sides of the wafer, so that large alignment errors often exist, the yield is reduced, and hidden dangers are brought to the quality and the reliability of devices.
Disclosure of Invention
The invention provides a method and a device for manufacturing a micro-electromechanical device, which solve the technical problems that in the prior art, when the two sides of a wafer are processed, the large alignment error exists, the yield is reduced, and hidden troubles are brought to the quality and the reliability of the device.
In one aspect, the invention provides a method for manufacturing a micro-electromechanical device, comprising:
preparing an alignment mark on the back of a first wafer substrate;
preparing a conductive channel on the back surface of the first wafer substrate by using the alignment mark as an alignment reference;
turning over the first wafer substrate, and preparing an electrode window and a deflectable element on the front surface of the first wafer substrate by using a back-to-front alignment technology by using the alignment mark as an alignment reference;
and turning the first wafer substrate, and preparing an electrode control circuit electrically connected with the conductive channel on the back surface of the first wafer substrate by using the alignment mark as an alignment reference.
Optionally, after the preparing the alignment mark on the back side of the first wafer substrate, the method further includes: and grinding and polishing the back surface of the first wafer substrate on the basis of keeping the alignment mark.
Optionally, the preparing the alignment mark on the back surface of the first wafer substrate includes: preparing an alignment mark with the depth of 600-1200 nm on the back of the first wafer substrate; the grinding and polishing of the back surface of the first wafer substrate comprises: and grinding and polishing the back surface of the first wafer substrate, wherein the depth of the alignment mark after grinding and polishing is 300-1100 nanometers.
Optionally, the turning over the first wafer substrate, using the alignment mark as an alignment reference, and using a back-to-front alignment technique to prepare an electrode window and a deflectable element on the front side of the first wafer substrate, includes: turning over the first wafer substrate, and preparing the electrode window in the top silicon layer and the buried oxide layer on the front surface of the first wafer substrate by using a back-to-front alignment technology, wherein the alignment mark is an alignment reference, and the electrode window is aligned with the conductive channel; placing a second wafer substrate on the front surface of the first wafer substrate, and bonding the first wafer substrate and the second wafer substrate; and photoetching the second wafer substrate by using a back-to-front alignment technology by using the alignment mark as an alignment reference to prepare the deflectable element.
Optionally, the placing the second wafer substrate on the front surface of the first wafer substrate includes: thinning the back surface of a second wafer substrate, inverting the second wafer substrate, and placing the second wafer substrate on the front surface of the first wafer substrate by contacting the front surface of the second wafer substrate with the front surface of the first wafer substrate, wherein the front surface of the second wafer substrate is provided with a top silicon layer and/or a buried oxide layer.
Optionally, the opening size of the electrode window is smaller than the cross-sectional size of the conductive channel.
Optionally, before preparing an electrode control circuit electrically connected to the through-silicon via conductive via on the back side of the first wafer substrate, the method further includes: a third wafer is placed on the deflectable element and the third wafer and the second wafer substrate are bonded.
Optionally, after preparing the electrode control circuit electrically connected to the conductive via on the back side of the first wafer substrate, the method further includes: and releasing the bonding of the third wafer and the second wafer substrate.
Optionally, the preparing a conductive channel on the back surface of the first wafer substrate by using the alignment mark as an alignment reference includes: photoetching and preparing an annular groove on the back surface of the first wafer substrate by using the alignment mark as an alignment reference; filling insulating medium into the annular groove; and carrying out ion implantation or doping diffusion on the silicon through hole surrounded by the annular groove to form a silicon through hole conductive channel.
In another aspect, there is provided a micro-electromechanical device manufacturing apparatus, including:
the alignment module is used for preparing an alignment mark on the back of the first wafer substrate;
the channel preparation module is used for preparing a conductive channel on the back surface of the first wafer substrate by using the alignment mark as an alignment reference;
a deflectable element preparation module, configured to turn over the first wafer substrate, and prepare an electrode window and a deflectable element on a front side of the first wafer substrate by using a back-to-front alignment technique with the alignment mark as an alignment reference;
and the circuit preparation module is used for overturning the first wafer substrate, preparing an electrode control circuit electrically connected with the conductive channel on the back surface of the first wafer substrate by using the alignment mark as an alignment reference.
One or more technical solutions provided in the embodiments of the present invention have at least the following technical effects or advantages:
1. according to the method and the device provided by the embodiment of the application, after the alignment mark is prepared on the back surface of the first wafer substrate, the alignment mark is firstly used as an alignment reference, and the conductive channel is prepared on the back surface of the first wafer substrate; turning over the first wafer substrate, and preparing an electrode window and a deflectable element on the front surface of the first wafer substrate by using the alignment mark as an alignment reference and adopting a back-to-front alignment technology; and finally, overturning the first wafer substrate, and preparing an electrode control circuit electrically connected with the conductive channel on the back surface of the first wafer substrate by using the alignment mark as an alignment reference. Therefore, when the electrode window, the deflectable element and the electrode control circuit are prepared, the alignment mark is not shielded, the alignment precision can be effectively improved, and the yield and the device quality are improved.
2. According to the method and the device provided by the embodiment of the application, on the basis of keeping the alignment mark, the back of the first wafer substrate is ground and polished, then the alignment mark is used as an alignment reference, and an electrode window and a deflectable element are prepared on the front of the first wafer substrate by adopting a back-to-front alignment technology, so that the alignment mark is not shielded, the flatness of the whole wafer on a wafer bearing table of exposure equipment is improved, and the alignment precision is further effectively improved.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
FIG. 1 is a flow chart of a method for fabricating a micro-electromechanical device in an embodiment of the present invention;
FIG. 2 is a first process diagram of a method of fabricating a micro-electromechanical device in accordance with an embodiment of the present invention;
FIG. 3 is a second process diagram of a method of fabricating a micro-electromechanical device in accordance with an embodiment of the present invention;
FIG. 4 is a third process diagram of a method of fabricating a micro-electromechanical device in accordance with an embodiment of the present invention;
FIG. 5 is a process diagram of a fourth method of fabricating a micro-electromechanical device in accordance with an embodiment of the present invention;
FIG. 6 is a process diagram of a method of fabricating a micro-electromechanical device in accordance with an embodiment of the present invention;
FIG. 7 is a schematic diagram of a device fabricated by a method of fabricating a microelectromechanical device in an embodiment of the present invention;
FIG. 8 is a schematic diagram of an apparatus for manufacturing a micro-electromechanical device according to an embodiment of the present invention.
Detailed Description
The embodiment of the application provides a method and a device for manufacturing a micro-electromechanical device, so that the technical problems that in the prior art, when two sides of a wafer are processed, a large alignment error exists, the rate of finished products is reduced, and hidden dangers are brought to the quality and the reliability of the device are solved. The alignment precision can be effectively improved, and the yield and the device quality can be improved.
The technical scheme in the embodiment of the application has the following general idea:
after an alignment mark is prepared on the back surface of a first wafer substrate, firstly, the alignment mark is used as an alignment reference, and a through silicon via conductive channel is prepared on the back surface of the first wafer substrate; turning over the first wafer substrate, and preparing an electrode window and a deflectable element on the front surface of the first wafer substrate by using the alignment mark as an alignment reference and adopting a back-to-front alignment technology; and finally, overturning the first wafer substrate, and preparing an electrode control circuit electrically connected with the through silicon via conductive channel on the back surface of the first wafer substrate by using the alignment mark as an alignment reference. Therefore, when the electrode window, the deflectable element and the electrode control circuit are prepared, the alignment mark is not shielded, the alignment precision can be effectively improved, and the yield and the device quality are improved.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example one
In this embodiment, a method for manufacturing a micro-electromechanical device is provided, as shown in fig. 1, including:
step S101, preparing an alignment mark on the back of a first wafer substrate;
step S102, preparing a conductive channel on the back of the first wafer substrate by using the alignment mark as an alignment reference;
step S103, turning over the first wafer substrate, using the alignment mark as an alignment reference, and adopting a back-to-front alignment technology to prepare an electrode window and a deflectable element on the front side of the first wafer substrate;
and step S104, overturning the first wafer substrate, and preparing an electrode control circuit electrically connected with the conductive channel on the back surface of the first wafer substrate by using the alignment mark as an alignment reference.
It should be noted that the method provided by the present embodiment can be applied to any double-sided stereo device with a deflectable element. By adopting the method provided by the embodiment, the alignment mark can be ensured not to be shielded when the through-silicon-via conductive channel and the electrode control circuit are prepared, and the alignment mark can be ensured not to be shielded when the electrode window and the deflectable element are prepared by adopting the back-to-front alignment technology, so that the alignment precision can be obviously improved.
The following describes a manufacturing method provided in an embodiment of the present application with reference to fig. 1 to 7, where fig. 2 to 7 are flowcharts of a manufacturing method of a micro-electromechanical device arranged in a process sequence order provided in this embodiment:
first, step S101 is performed to prepare an alignment mark 4 on the back surface of the first wafer substrate 1.
As shown in fig. 2, the front surface of the first wafer substrate 1 is provided with a buried oxide layer 2(BOX) and a top silicon layer 3, and the back surface of the first wafer substrate 1 is exposed.
In the embodiment of the present application, the first wafer substrate 1 may be an SOI wafer, and may also be glass, ceramic, SU-8, or the like. And the method can be extended to any semiconductor substrate material, and can also be extended to any processing material required by a micro-mechanical system or a microelectronic system to be processed, and is not limited herein.
In the embodiment of the present application, the alignment mark may be formed by photolithography and plasma dry etching, or by photolithography and color injection. The shape of the alignment mark is not limited. The depth of the alignment mark is 600 nm to 1200 nm.
Then, step S102 is executed to prepare a conductive via on the back side of the first wafer substrate 1 by using the alignment mark 4 as an alignment reference.
Specifically, the method for preparing the conductive channel comprises the following steps: firstly, as shown in fig. 2, by using the alignment mark 4 as an alignment reference, coating a photoresist 5, and adopting a deep reactive ion etching process, etching is stopped at a position just contacting the buried oxide layer 2, so as to prepare an annular groove 6 on the back surface of the first wafer substrate 1 by photoetching; then, as shown in fig. 3, the annular trench 6 is filled with an insulating medium, and the part surrounded by the annular trench in an insulating way is the through silicon via 7; and then, carrying out ion implantation or doping diffusion on the silicon through hole 7 surrounded by the annular groove 6 to enable the silicon through hole to have conductive performance so as to form a conductive channel.
In the embodiments of the present application, the conductive path is not limited to the through-silicon via 7, but may be a metal via, i.e. a metal conductive path surrounded by an insulating material, i.e. the form and structure of the conductive path are various and will not be discussed in detail herein.
Preferably, after the through-silicon via conductive via is prepared, the back surface of the first wafer substrate 1 is ground and polished, i.e., fine masking is performed, while the alignment mark 4 is remained, and the grinding process is controlled by the process and cannot damage or grind down the manufactured alignment mark. The depth of the alignment mark left after the fine grinding process needs to be controlled to be between 300 nanometers and 1100 nanometers, and particularly, the fine grinding process or the CMP process technology can be adopted to realize the control.
Of course, the back side of the first wafer substrate 1 may also be ground and polished after the alignment mark 4 is prepared and before the through-silicon via conductive via is prepared, which is not limited herein. However, the back surface of the first wafer substrate 1 is ground and polished after the through-silicon-via conductive channel is prepared, so that the influence of the prepared through-silicon-via conductive channel on the back surface of the first wafer substrate 1 is avoided, the flatness of the back surface after the wafer is subsequently turned can be ensured, and the alignment precision can be improved.
Next, step S103 is executed to flip the first wafer substrate 1 on the wafer receiving platform 12, and prepare an electrode window (including the actuation-side protection layer window 10 and the braking electrode window 11) and a deflectable element 17 on the front side of the first wafer substrate 1 by using the alignment mark 4 as an alignment reference and using a back-to-front alignment technique.
Specifically, the electrode control circuit 8 electrically connected to the through-silicon via is not formed on the exposed back bottom surface of the first wafer substrate 1. Instead, the finely ground backing bottom of the first wafer substrate 1 is placed downward to prepare the electrode window and the deflectable element 17, so that the electrode control circuit 8 can be prevented from shielding the alignment mark 4 and affecting the alignment accuracy.
In a specific implementation, the back-to-front alignment technique may be a back-to-front alignment technique of ASML. Or other alignment techniques. Compared with the method that after the through silicon via 7 is manufactured, the back surface of the first wafer substrate 1 is not subjected to fine polishing, and the electrode control circuit is continuously manufactured on the surface where the alignment mark 4 is manufactured, because the electrode control circuit does not shield and stack the alignment mark, the exposed surface of the back surface after the through silicon via 7 is manufactured is also subjected to fine grinding, so that the flatness of the whole wafer on a wafer bearing table of exposure equipment is improved, therefore, the alignment precision from the back surface to the front surface is greatly improved, and the original alignment error of 0.15 micrometer is improved to 0.02 micrometer, namely 20 nanometers.
Specifically, the method of preparing the electrode window and the deflectable elements 17 on the front side of the first wafer substrate 1 comprises:
first, as shown in fig. 4, the first wafer substrate 1 is turned over, the alignment mark 4 is used as an alignment reference, and the electrode window is prepared in the top silicon layer 3 and the buried oxide layer 2 on the front surface of the first wafer substrate 1 by using a back-to-front alignment technique, and the electrode window is aligned with the through-silicon via conductive channel.
Specifically, a photoresist may be coated on the front surface of the first wafer substrate 1, and then an electrode window is aligned with the position of the photolithography from the back surface to the front surface by the alignment mark 4, and a deep reactive ion etching process is employed to manufacture a top electrode window embedded on the front surface of the first wafer substrate 1 and facing the through-silicon-via 7, where the electrode window is located in the buried oxide layer 2 and the top silicon 3 of the first wafer substrate 1, and the opening size of the electrode window is smaller than the cross-sectional size of the conductive channel of the through-silicon-via 7, so as to shield and protect a part of the top end of the through-silicon-via 7.
Then, a second wafer substrate 14 is placed on the front surface of the first wafer substrate 1, and the first wafer substrate 1 and the second wafer substrate 14 are bonded. Specifically, the back surface of the second wafer substrate 14 is thinned, the second wafer substrate 14 is inverted, the front surface of the second wafer substrate 14 contacts the front surface of the first wafer substrate 1, and the second wafer substrate 14 is placed on the front surface of the first wafer substrate 1, wherein the front surface of the second wafer substrate 14 is provided with a top silicon layer and/or a buried oxide layer, and the back surface is exposed.
Next, the second wafer substrate 14 is photo-etched using the alignment mark 4 as an alignment reference and a back-to-front alignment technique, thereby preparing the deflectable element 17.
Specifically, as shown in fig. 5, the method for manufacturing the deflectable element 17 includes performing photolithography and deep reactive ion etching on the second photoresist 15 to form a hinge 18 or a groove of the pillar structure of the deflectable element 17, and preparing a movable cavity 19 of the deflectable element 17, where the hinge 18 is a top silicon layer and/or a buried oxide layer. The processed second wafer substrate 14 is then aligned back side up, with the grooves and hinges 18 or posts facing down, and permanently bonded to the first wafer substrate 1. After the bonding process is finished, the first wafer substrate 1 and the second wafer substrate 14 are combined into a whole by the processed wafers. Above the through-silicon vias of the first wafer substrate 1 are the electrode windows of the through-silicon vias in the buried oxide layer and the top silicon layer of the first wafer substrate 1, and above them are the thinned backing bottom of the second wafer substrate 14 (the backing bottom of the second wafer substrate 14 can also be completely removed), the buried oxide layer and the top silicon layer. The recess, hinge 18 or post formed in the second wafer substrate 14 structure is the cavity 19 for placing the deflectable element 17 and its hinge or post. The movable element 17 is fabricated by placing the first wafer substrate 1 with its back surface facing down and the second wafer substrate 14 with its back surface facing up, and continuing the photolithography process step and the deep reactive ion etching process step after the etching step 16.
Next, step S104 is executed to turn over the first wafer substrate 1, and with the alignment mark 4 as an alignment reference, an electrode control circuit 8 electrically connected to the conductive channel is prepared on the back surface of the first wafer substrate 1.
Preferably, as shown in fig. 6, before the electrode control circuit 8 electrically connected to the through-silicon via conductive via is prepared on the back side of the first wafer substrate 1, the third wafer 20 may be placed on the deflectable element 17, and the third wafer 20 and the second wafer substrate 14 may be bonded, that is, temporary bonding is performed for protection, so as to protect the deflectable element 17 from being damaged in the subsequent processing process. And then, the whole of the three wafers after the two times of bonding is inverted, namely the back surface of the first wafer substrate 1 faces upwards, the temporarily bonded third wafer 20 for protecting the movable element 17 faces downwards, a dielectric layer 9 where a circuit is located is formed, and the manufacturing process of the electrode control circuit 8 is carried out on the dielectric layer 9. The completed electrode control circuit 8 has good electrical interconnection with the through silicon vias 7 on the first wafer substrate 1, and the electrode control circuit 8 can control or sense the movement of the deflectable element 17.
Then, the third wafer 20 is released from bonding with the second wafer substrate 14. The fabrication of the micro-electromechanical device shown in fig. 7 is completed.
Specifically, in the embodiment, the material of the back alignment mark to be referred to for back alignment is subjected to surface treatment and fine grinding/polishing, so that the flatness of the back of the wafer is improved, the degree of fine grinding/polishing is controlled, the back alignment mark is protected, and the optical resolution of the line is not affected. And a preparation procedure is set to prevent the back side alignment mark from being stacked and covered under the multilayer material where the electrode control circuit is located, so that the alignment precision from the back side to the front side is improved, and finally the alignment precision between the electrode window and the deflectable element is improved.
In the process flow of the prior art, each time the back-to-front alignment is performed, taking an ASML stepper as an example, the alignment error is not less than 0.15 μm. After the method of this embodiment is adopted, taking an ASML stepper as an example, alignment error is improved to a higher precision level not less than 0.02 μm each time alignment from the back side to the front side is performed.
Based on the same inventive concept, the application also provides a device corresponding to the method of the first embodiment, which is detailed in the second embodiment.
Example two
The embodiment provides a micro-electromechanical device manufacturing apparatus, as shown in fig. 8, including:
an alignment module 801, configured to prepare an alignment mark on a back side of a first wafer substrate;
a channel preparation module 802, configured to prepare a conductive channel on the back side of the first wafer substrate by using the alignment mark as an alignment reference;
a deflectable element preparation module 803, configured to flip the first wafer substrate, and prepare an electrode window and a deflectable element on the front side of the first wafer substrate by using a back-to-front alignment technique with the alignment mark as an alignment reference;
and a circuit preparation module 804, configured to turn over the first wafer substrate, and prepare an electrode control circuit electrically connected to the conductive via on the back side of the first wafer substrate by using the alignment mark as an alignment reference.
Since the apparatus described in the second embodiment of the present invention is an apparatus used for implementing the method of the first embodiment of the present invention, based on the method described in the first embodiment of the present invention, a person skilled in the art can understand the specific structure and the deformation of the apparatus, and thus the details are not described herein. All the devices adopted in the method of the first embodiment of the present invention belong to the protection scope of the present invention.
The technical scheme provided in the embodiment of the application at least has the following technical effects or advantages:
1. according to the method and the device provided by the embodiment of the application, after the alignment mark is prepared on the back surface of the first wafer substrate, the alignment mark is firstly used as an alignment reference, and the conductive channel is prepared on the back surface of the first wafer substrate; turning over the first wafer substrate, and preparing an electrode window and a deflectable element on the front surface of the first wafer substrate by using the alignment mark as an alignment reference and adopting a back-to-front alignment technology; and finally, overturning the first wafer substrate, and preparing an electrode control circuit electrically connected with the conductive channel on the back surface of the first wafer substrate by using the alignment mark as an alignment reference. Therefore, when the electrode window, the deflectable element and the electrode control circuit are prepared, the alignment mark is not shielded, the alignment precision can be effectively improved, and the yield and the device quality are improved.
2. According to the method and the device provided by the embodiment of the application, on the basis of keeping the alignment mark, the back of the first wafer substrate is ground and polished, then the alignment mark is used as an alignment reference, and an electrode window and a deflectable element are prepared on the front of the first wafer substrate by adopting a back-to-front alignment technology, so that the alignment mark is not shielded, the flatness of the whole wafer on a wafer bearing table of exposure equipment is improved, and the alignment precision is further effectively improved.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made in the embodiments of the present invention without departing from the spirit or scope of the embodiments of the invention. Thus, if such modifications and variations of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to encompass such modifications and variations.
Claims (10)
1. A method for preparing a micro-electromechanical device is characterized by comprising the following steps:
preparing an alignment mark on the back of a first wafer substrate;
preparing a conductive channel on the back surface of the first wafer substrate by using the alignment mark as an alignment reference;
turning over the first wafer substrate, and preparing an electrode window and a deflectable element on the front surface of the first wafer substrate by using a back-to-front alignment technology by using the alignment mark as an alignment reference;
and turning the first wafer substrate, and preparing an electrode control circuit electrically connected with the conductive channel on the back surface of the first wafer substrate by using the alignment mark as an alignment reference.
2. The method of claim 1, wherein after preparing the alignment mark on the back side of the first wafer substrate, further comprising:
and grinding and polishing the back surface of the first wafer substrate on the basis of keeping the alignment mark.
3. The method of claim 2,
the preparation of the alignment mark on the back surface of the first wafer substrate comprises the following steps: preparing an alignment mark with the depth of 600-1200 nm on the back of the first wafer substrate;
the grinding and polishing of the back surface of the first wafer substrate comprises: and grinding and polishing the back surface of the first wafer substrate, wherein the depth of the alignment mark after grinding and polishing is 300-1100 nanometers.
4. The method of claim 1, wherein said flipping said first wafer substrate with said alignment marks as an alignment reference and using a back-to-front alignment technique to fabricate an electrode window and a deflectable element on a front side of said first wafer substrate comprises:
turning over the first wafer substrate, and preparing the electrode window in the top silicon layer and the buried oxide layer on the front surface of the first wafer substrate by using a back-to-front alignment technology, wherein the alignment mark is an alignment reference, and the electrode window is aligned with the conductive channel;
placing a second wafer substrate on the front surface of the first wafer substrate, and bonding the first wafer substrate and the second wafer substrate;
and photoetching the second wafer substrate by using a back-to-front alignment technology by using the alignment mark as an alignment reference to prepare the deflectable element.
5. The method of claim 4, wherein said placing a second wafer substrate on the front side of the first wafer substrate comprises:
thinning the back surface of a second wafer substrate, inverting the second wafer substrate, and placing the second wafer substrate on the front surface of the first wafer substrate by contacting the front surface of the second wafer substrate with the front surface of the first wafer substrate
And the front surface of the second wafer substrate is provided with a top silicon layer and/or a buried oxide layer.
6. The method of claim 4, wherein the opening size of the electrode window is smaller than the cross-sectional dimension of the conductive via.
7. The method of claim 4, wherein before preparing electrode control circuitry on the back side of the first wafer substrate in electrical connection with the conductive vias, further comprising:
a third wafer is placed on the deflectable element and the third wafer and the second wafer substrate are bonded.
8. The method of claim 7, wherein after preparing electrode control circuitry on the back side of the first wafer substrate in electrical connection with the conductive vias, further comprising:
and releasing the bonding of the third wafer and the second wafer substrate.
9. The method of claim 1, wherein the preparing conductive vias in the first wafer substrate backside with the alignment marks as alignment references comprises:
photoetching and preparing an annular groove on the back surface of the first wafer substrate by using the alignment mark as an alignment reference;
filling insulating medium into the annular groove;
and carrying out ion implantation or doping diffusion on the silicon through hole surrounded by the annular groove to form a silicon through hole conductive channel.
10. A micro-electromechanical device manufacturing apparatus, comprising:
the alignment module is used for preparing an alignment mark on the back of the first wafer substrate;
the channel preparation module is used for preparing a conductive channel on the back surface of the first wafer substrate by using the alignment mark as an alignment reference;
a deflectable element preparation module, configured to turn over the first wafer substrate, and prepare an electrode window and a deflectable element on a front side of the first wafer substrate by using a back-to-front alignment technique with the alignment mark as an alignment reference;
and the circuit preparation module is used for overturning the first wafer substrate, preparing an electrode control circuit electrically connected with the conductive channel on the back surface of the first wafer substrate by using the alignment mark as an alignment reference.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103165442A (en) * | 2011-12-12 | 2013-06-19 | 上海华虹Nec电子有限公司 | Back side graphical method |
| CN104576310A (en) * | 2013-10-16 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for alignment and conduction of back surface of semi-conductor |
| CN105502284A (en) * | 2015-12-10 | 2016-04-20 | 上海集成电路研发中心有限公司 | Technology integration method for wafer back alignment |
| CN105502280A (en) * | 2014-09-24 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | MEMS device forming method |
| CN105819395A (en) * | 2015-01-09 | 2016-08-03 | 中国科学院微电子研究所 | Method for producing semiconductor device |
| CN107634027A (en) * | 2017-08-25 | 2018-01-26 | 上海微阱电子科技有限公司 | A kind of lithography alignment method for three-dimensionally integrated technique |
| JP6298723B2 (en) * | 2014-06-13 | 2018-03-20 | 株式会社ディスコ | Bonded wafer forming method |
| US10109474B1 (en) * | 2017-05-23 | 2018-10-23 | United Microelectronics Corp. | Method for fabricating handling wafer |
-
2018
- 2018-11-15 CN CN201811356928.8A patent/CN109534283B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103165442A (en) * | 2011-12-12 | 2013-06-19 | 上海华虹Nec电子有限公司 | Back side graphical method |
| CN104576310A (en) * | 2013-10-16 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for alignment and conduction of back surface of semi-conductor |
| JP6298723B2 (en) * | 2014-06-13 | 2018-03-20 | 株式会社ディスコ | Bonded wafer forming method |
| CN105502280A (en) * | 2014-09-24 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | MEMS device forming method |
| CN105819395A (en) * | 2015-01-09 | 2016-08-03 | 中国科学院微电子研究所 | Method for producing semiconductor device |
| CN105502284A (en) * | 2015-12-10 | 2016-04-20 | 上海集成电路研发中心有限公司 | Technology integration method for wafer back alignment |
| US10109474B1 (en) * | 2017-05-23 | 2018-10-23 | United Microelectronics Corp. | Method for fabricating handling wafer |
| CN107634027A (en) * | 2017-08-25 | 2018-01-26 | 上海微阱电子科技有限公司 | A kind of lithography alignment method for three-dimensionally integrated technique |
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