CN106681951B - Equipment and system for communication between MVB network card and PCI bus interface - Google Patents
Equipment and system for communication between MVB network card and PCI bus interface Download PDFInfo
- Publication number
- CN106681951B CN106681951B CN201510765572.3A CN201510765572A CN106681951B CN 106681951 B CN106681951 B CN 106681951B CN 201510765572 A CN201510765572 A CN 201510765572A CN 106681951 B CN106681951 B CN 106681951B
- Authority
- CN
- China
- Prior art keywords
- pci
- bus
- interface
- interface module
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4009—Coupling between buses with data restructuring
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Abstract
The invention provides a device for communication between a multifunctional vehicle bus MVB network card and an external component interconnection PCI bus interface, which is realized by adopting a field programmable gate array and comprises the following components: the PCI interface module, the PCI bus analysis module and the PC104 interface module are sequentially in communication connection; the PCI interface module is used for being connected with a PCI bus interface; the PC104 interface module is used for being connected with a PC104 bus interface of the MVB network card; the PCI bus analysis module is used for converting the PCT protocol data from the PCI interface module into PC104 protocol data and sending the PC104 protocol data to the PC104 interface module; and converting the PC104 protocol data from the PC104 interface module into PCI protocol data, and sending the PCI protocol data to the PCI interface module.
Description
Technical Field
The embodiment of the invention relates to an electronic technology, in particular to a device for communication between a multifunctional vehicle bus MVB network card and an external component interconnection PCI bus interface.
Background
In order to realize the communication between a Multifunctional Vehicle Bus (MVB) communication network card and various functional components of a computer, the MVB communication network card conforming to IEC-61375 based on the PC104 Bus technology has been widely applied in the rail transit industry.
With the continuous advancement of scientific technology, Peripheral Component Interconnect (PCI) bus is gradually replacing PC/104 bus technology. Compared with the PC/104 bus technology, the PCI bus has more advantages in cost control in occasions with low communication speed requirements. Therefore, compared with the MVB network card based on the PC/104 bus technology, the MVB network card based on the PCI bus technology has more advantages. In order to enable the existing MVB network card based on the PC104 bus technology to communicate with the device based on the PCI bus technology, the prior art generally employs a bridge chip to bridge between the MVB network card and the PCI bus interface.
However, in the prior art, a bridge chip mode is adopted to establish communication between the MVB network card and the PCI bus interface based on the PC104 bus technology, which occupies more space resources on a circuit board and increases the design cost.
Disclosure of Invention
The invention provides equipment for communication between a multifunctional vehicle bus MVB network card and an external component interconnection PCI bus interface, which is used for solving the problems that a bridge chip in the prior art occupies space resources of a circuit board and increases design cost.
The embodiment of the invention provides equipment for communication between a multifunctional vehicle bus MVB network card and an external component interconnection PCI bus interface, which is realized by adopting a Field Programmable Gate Array (FPGA), and comprises the following components:
the external components which are sequentially connected in a communication manner are connected with the PCI interface module, the PCI bus analysis module and the PC104 interface module in a communication manner;
the PCI interface module is used for being connected with a PCI bus interface and carrying out communication interaction based on a PCI protocol with the PCI bus interface;
the PC104 interface module is used for being connected with a PC104 bus interface of the MVB network card and carrying out communication interaction based on a PC104 bus protocol with the MVB network card;
the PCI bus analysis module is used for converting the PCT protocol data from the PCI interface module into PC104 protocol data and sending the PC104 protocol data to the PC104 interface module; and converting the PC104 protocol data from the PC104 interface module into PCI protocol data, and sending the PCI protocol data to the PCI interface module.
Optionally, a first signal input/output channel is arranged between the PCI interface module and the PCI bus analysis module; a second signal input/output channel is arranged between the PCI bus analysis module and the PC104 interface module;
the PCI interface module is used for sending an MVB read-write request to the PCI bus analysis module through the first signal input/output channel and receiving an MVB read-write response sent by the PCI bus analysis module through the first signal input/output channel;
accordingly, the method can be used for solving the problems that,
the PC104 interface module is configured to receive, through the second signal input/output channel, the MVB read-write request sent by the PCI bus analysis module, and send, through the second signal input/output channel, an MVB read-write response to the PCI bus analysis module.
Optionally, an address and data bus is arranged between the PCI interface module and the PCI bus resolution module,
the PCI interface module is used for writing an access address effective range into the PCI bus analysis module through the address and data bus and sending a PCI access address to the PCI bus analysis module through the address and data bus;
and the PCI analysis module is used for determining whether the PCI access address is valid according to the effective range of the PCI access address.
Optionally, a PCI bus command and byte enable control channel and an address transmission channel are arranged between the PCI interface module and the PC104 interface module, signals of the PCI bus command and byte enable control channel are used for indicating read, write or byte enable control states,
the PCI interface module is used for sending a PCI read-write request or a byte enabling command to the PC104 interface module through the PCI bus command and a byte enabling control channel; and is used for sending PCI access address to the PC104 interface module through the address transmission channel when the PCI bus command and byte enable control channel sends PCI read-write request;
and the PC104 interface module is used for determining the read-write address of the PC104 bus interface according to the PCI access address, the PCI bus command and the specific value of the byte enable command of the byte enable control channel.
Optionally, a PCI bus state setting channel, a PCI bus command and byte enable control channel are arranged between the PC104 interface module and the PCI interface module;
and the PC104 interface module is used for setting the state of the PCI bus interface through the signal of the PCI bus state setting channel.
Optionally, the PC104 interface module further comprises a bus address latch enable signal pin,
the PC104 interface module is used for confirming whether the write address of the PC104 bus interface is valid according to the signal of the bus address latch enabling signal pin,
and the cache is used for caching write operation data from the PCI bus interface when the PCI bus interface is in a waiting state and a write address of the PC104 bus interface is valid.
Optionally, the PC104 interface module is further provided with a PC104 bus interface write enable signal pin,
the PC104 interface module is configured to write the cached write operation data into the PC104 bus interface when a signal of a write enable signal pin of the PC104 bus interface is valid.
Optionally, the PC104 interface module is further provided with a bus address latch enable signal pin and a PC104 bus interface read enable signal pin,
the PC104 interface module is used for confirming whether the read address of the PC104 bus interface is valid according to the signal of the bus address latch enable signal pin; the PCI bus interface is in a waiting state, the read address of the PC104 bus interface is effective, and the signal of the PC104 bus interface read enable signal pin is effective, the data is read from the PC104 bus interface and cached;
the PCI interface module is further configured to, when the PCI bus interface is in a retry state, read data cached in the PC104 interface module.
The embodiment of the invention also provides a communication system which comprises the multifunctional vehicle bus MVB network card with the PC104 bus interface, the external component interconnection PCI bus interface and any one of the devices.
The device and the system for realizing the communication between the MVB network card and the PCI bus interface provided by the embodiment of the invention are connected with a device with the PCI bus interface through the PCI interface module, connected with the MVB network card with the PC104 bus interface through the PC104 interface module, and used for realizing the conversion between the PCI protocol data and the PC104 protocol data through the PCI bus analysis module, so that the MVB network card with the PC104 bus interface can be communicated with the device with the PCI bus interface, and the device is realized by adopting the FPGA, thereby improving the space utilization rate of a circuit board and saving the cost.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic diagram of a frame structure of a device for implementing communication between an MVB network card and a PCI bus interface, the PCI bus interface, and a PC104 bus interface according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the specific circuit configuration of FIG. 1;
FIG. 3 is a diagram of a finite state machine of a PC104 bus interface module according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a communication system according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides equipment for realizing the communication between a multifunctional vehicle bus MVB network card and an external component interconnection PCI bus interface. The existing MVB network card based on the PC104 bus communication technology can be compatible with the equipment based on the PCI bus communication technology.
Fig. 1 is a schematic diagram of a frame structure of a device for implementing communication between an MVB network card and a PCI bus interface, the PCI bus interface, and a PC104 bus interface according to an embodiment of the present invention.
Referring to fig. 1, an apparatus 10 for implementing communication between an MVB network card and a PCI bus interface according to an embodiment of the present invention is implemented by a Field Programmable Gate Array (FPGA), and the apparatus includes:
the external components are connected with the PCI interface module 110, the PCI bus analysis module 120 and the PC104 interface module 130 in a communication mode in sequence;
the PCI interface module 110 is configured to be connected to a PCI bus interface 20, and perform communication interaction based on a PCI protocol with the PCI bus interface 20;
the PC104 interface module 130 is configured to connect with the PC104 bus interface 30 of the MVB network card, and perform communication interaction based on a PC104 bus protocol with the MVB network card (not shown);
the PCI bus parsing module 120 is configured to convert PCT protocol data from the PCI interface module 10 into PC104 protocol data, and send the PC104 protocol data to the PC104 interface module 30; and converting the PC104 protocol data from the PC104 interface module 30 into PCI protocol data, and transmitting the PCI protocol data to the PCI interface module 10.
The device for realizing the communication between the MVB network card and the PCI bus interface provided by the embodiment of the invention is connected with the device with the PCI bus interface through the PCI interface module, is connected with the MVB network card with the PC104 bus interface through the PC104 interface module, and realizes the conversion between the PCI protocol data and the PC104 protocol data through the PCI bus analysis module, so that the MVB network card with the PC104 bus interface can communicate with the device with the PCI bus interface, and the device is realized by adopting FPGE (field programmable gate array), thereby improving the space utilization rate of a circuit board and saving the cost.
Fig. 2 is a schematic diagram of the specific circuit structure of fig. 1.
Referring to fig. 2, further, a first signal input/output channel is disposed between the PCI interface module 110 and the PCI bus parsing module 120; a second signal input/output channel is arranged between the PCI bus analysis module 120 and the PC104 interface module 130;
the PCI interface module 110 is configured to send an MVB read-write request to the PCI bus analysis module 120 through the first signal input/output channel, and receive an MVB read-write response sent by the PCI bus analysis module 120 through the first signal input/output channel; or, the PCI read-write request sent by the PCI bus analysis module 120 is received through the first signal input/output channel, and a PCI read-write response is sent to the PCI bus analysis module 120 through the first signal input/output channel;
accordingly, the method can be used for solving the problems that,
the PC104 interface module 130 is configured to send a PCI read-write request to the PCI bus analysis module 120 through the second signal input/output channel, and receive a PCI read-write response sent by the PCI bus analysis module 120 through the second signal input/output channel; or, receive, through the second signal input/output channel, the MVB read-write request sent by the PCI bus analysis module 120, and send, through the second signal input/output channel, an MVB read-write response to the PCI bus analysis module 120.
The first signal input-output channels include time-division multiplexed address and data buses ADIO _ IN [31:0] and ADIO _ OUT [31:0] and the second signal input-output channel comprises a data bus PCI _ IN [31:0] and PCI _ OUT [31:0 ].
The PCI interface module 110 may use an intellectual property core (IP core) of Xilinx to complete the function of configuring PCI by a Central Processing Unit (CPU). The configuration space of the PCI bus device is designed for configuration, initialization, and catastrophic error handling functions. For example, the configuration of the header area of the PCI interface module 110 can be as shown in table 1:
TABLE 1
The PC104 interface module 130 is used to implement the read/write function of the PCI bus interface 20 to the PC104 bus interface 30.
Further, in order to ensure that the PCI access address given by the CPU is valid, i.e. can be matched with the read/write address of the PC104 bus interface, an address and data bus ADIO _ OUT [31:0],
the PCI interface module 110 is configured to transmit, via the address and data bus ADIO _ OUT [31:0] write access address valid range to the PCI bus resolution module 120 and for reading data from the PCI bus through the address and data bus ADIO _ OUT [31:0] sending the PCI access address to the PCI bus resolution module 120;
the PCI resolution module 120 is configured to determine whether the PCI access address is valid according to the valid range of the access address. Specifically, a bus address selected control channel ADDR _ VLD, a first PCI bus command, and a byte enable control channel S _ CBE are provided between the PCI interface module 110 and the PCI bus parsing module 120 [ 3: 0]. A read ENABLE control channel bar _ RD _ CS, a write ENABLE control channel bar _ WR _ CS, and an address switch control channel PCI _ ENABLE are provided between the PCI bus resolution module 120 and the PC104 interface module 130.
For an address bus, there is a limit to the effective address range that the PCI bus interface 20 can access the PC104 bus interface 30. When the CPU issues an instruction to access the PCI bus interface 20, the signal of the control channel ADDR _ VLD selected by the bus address is valid in one clock cycle, and at this time, the first PCI bus command and byte enable control channel S _ CBE [ 3: signal command of 0] is read and written for space configuration. The CPU sends the command over the address and data bus ADIO _ IN [31:0] configure the address range. The specific method comprises the following steps: the CPU configures register ADDR [31:0] write the start address (starting address), end address (ending address) and translation offset (translation offset) data, and judge whether the access address of the PCI bus interface 20 is valid or not according to the data in these three registers. The specific mapping relationship is shown in table 2:
TABLE 2
Then the effective address range for the PCI bus interface 20 to access the PC104 bus interface 30 is start address: end address. The PCI bus parsing module 120 determines the PCI access address, and determines that the PCI access address is valid when the PCI access address is determined to be within the valid address range. The PCI bus resolution module 120 may assert the address switch control signal PCI _ ENABLE, indicating that the PCI interface module 110 may read and write data from/to the PC104 interface module 130.
Further, in order to determine the read/write address of the PC104 bus interface before performing the read/write operation and ensure the position of the written data and the correctness of the read data, a second PCI bus command and byte enable control channel and an address transmission channel S _ CBE [ 3: 0], the second PCI bus command and byte enable control channel S _ CBE [ 3: 0] is used to indicate the read, write, or byte enable control state,
the PCI interface module 110 is configured to enable a control channel S _ CBE [ 3: 0] sending a PCI read-write request or byte enable command to the PC104 interface module 130; and for transmitting a command and byte enable control signal when the second PCI bus command and byte enable control channel S _ CBE [ 3: 0] when sending a PCI read-write request, sending a PCI access address to the PC104 interface module 130 through the address transmission channel;
the PC104 interface module 130 is configured to, according to the PCI access address, the second PCI bus command, and a byte enable control channel S _ CBE [ 3: 0] determines the read and write address of the PC104 bus interface 30.
Specifically, when the bus address selects the control channel ADDR _ VLD to become low after being valid for one clock cycle, at this time, the PCI bus command and byte enable control channel S _ CBE [ 3: 0] may be read, write, or byte enable control. When the PCI bus command and byte enable control channel S _ CBE [ 3: 0], the PCI bus parsing module 120 parses the command signal to generate the read enable control signal BARO _ RD _ CS; when the PCI bus command and byte enable control channel S _ CBE [ 3: 0], the PCI bus parsing module 120 parses the command signal to generate the read enable control signal BARO _ WR _ CS; when the PCI bus command and byte enable control channel S _ CBE [ 3: when the command signal of 0] is byte enable control, the valid bit of the data bus obtained by the analysis of the PCI bus analysis module 120 may be determined according to S _ CBE [ 3: 0 is determined at a specific value in the byte command valid period.
The PC104 interface module 130 adds the PCI access address to the translation offset value in the register OTOFL0 to obtain the first 18 bits of the address of the PC104 bus interface 30, and according to the second PCI bus command and the byte enable control channel S _ CBE [ 3: the specific value of the byte enable command of 0] determines the second 2 bits of the address of the PC104 bus interface 30, and the read-write address of the PC104 bus interface 30 can be obtained by combining the first 18-bit address and the second 2-bit address.
Further, in order to ensure the correctness of the data reading and writing process, a PCI bus state setting channel, a PCI bus command and byte enable control channel are arranged between the PC104 interface module and the PCI interface module;
and the PC104 interface module is used for setting the state of the PCI bus interface through the signal of the PCI bus state setting channel.
Specifically, the PCI bus status setting channel includes a first control channel S _ TREM and a second control channel S _ READY. When the values of the first control channel S _ TREM and the second control channel S _ READY are both low, the PCI bus interface 20 is in a waiting state; when the value of the first control channel S _ TREM is low and the value of the second control channel S _ READY is high, the PCI bus interface 20 is in a RETRY (RETRY) state.
Further, in order to enable the PCI bus interface 30 to recognize the read/write address of the PC104 bus interface, the PC104 interface module 130 further includes a bus address latch enable signal pin BALE. The PC104 interface module 130 is configured to determine whether a write address of the PC104 bus interface is valid according to a signal of the bus address latch enable signal pin BALE, and buffer write operation data from the PCI bus interface 20 into a register of the PC104 interface module 130 when the PCI bus interface 20 is in a wait state and the write address of the PC104 bus interface 30 is valid.
Specifically, when the signal of the bus address latch enable signal pin BALE is at a high level, the PC104 interface module 130 confirms that the write address of the PC104 bus interface is valid.
Further, the PC104 interface module 130 is further provided with a PC104 bus interface write enable signal pin IOW. The PC104 interface module 130 is configured to write the cached write operation data into the PC104 bus interface 30 when the signal of the PC104 bus interface write enable signal pin IOW is valid. Specifically, the signal on the write enable signal pin IOW of the PC104 bus interface is active when the signal is at a high level.
Further, the PC104 interface module 130 is further provided with a PC104 bus interface read enable signal pin IOR. The PC104 interface module 130 is configured to determine whether a read address of the PC104 bus interface 30 is valid according to a signal of the bus address latch enable signal pin IOW; and is further configured to, when the PCI bus interface 20 is in a waiting state, the read address of the PC104 bus interface is valid, and the signal of the PC104 bus interface read enable signal pin IOR is valid, read data from the PC104 bus interface and perform caching.
The PCI interface module 110 is further configured to, when the PCI bus interface is in a retry state, read data cached in the PC104 interface module 130.
Specifically, the read/write function of the PCI bus interface 20 to the PC104 bus interface 30 can be implemented by a finite state machine of the PC104 interface module 130.
FIG. 3 is a diagram of a finite state machine of the PC104 bus interface module according to an embodiment of the present invention. Referring to FIG. 3, the write function of the PCI bus interface 20 to the PC104 bus interface 30 is implemented by the states S0-S3 of the finite state machine. The states of S0-S3 are described in detail below in conjunction with FIG. 3.
S0: and in an idle state, giving all signals an initial value.
S1: when the PC104 interface module 130 receives a write request from the CPU, it enters S1 state, sets the BALE signal high and gives the write address of the PC104 interface module 30 to send to the PC104 bus interface 30, and sets both the S _ TERM and S _ READY signals low, so that the PCI bus interface 20 is in a waiting state.
S2: unconditionally entering into an S2 state, keeping the BALE signal in a high level state, completing the PCI data writing operation of the PCI bus interface, and latching the PCI data into a register in the PC104 interface module.
S3: unconditionally enters the S3 state, pulling the BALE signal and IOW signal low, initiating a write request to the PC104 bus interface 30.
The PCI104 interface module 130 is provided with a timer which is initialized in the S0 state and starts counting down from the S0 state. Specifically, the initial value may be 16, for example, and may count down to 0, indicating that the write operation must complete in 16 clock cycles. After the PC104 interface module 130 enters the state S3, when the countdown value of the timer is 3, the write operation is completed, and the state transitions to the state S0 to wait for the next operation command issued by the CPU.
The total of 3 clock cycles from the S0 state to the S3 state, 13 for the timer value at the S3 state, and 10 clock cycles, i.e., 300ns, for the countdown value of 3 from the S3 state to the timer. As can be seen by the protocol, the write status of the PC104 bus interface 30 needs to be maintained for at least 200ns, so that the period of time from the state S3 to the countdown value of 3 for the timer is sufficient for the PC/104 bus to complete the write operation.
When the write function of the PCI bus interface 20 to the PC104 bus interface 30 is implemented, this is accomplished by the states S0 and S4-S8 of the finite state machine. The states of S4-S8 are described in detail below in conjunction with FIG. 3.
S4: when the PC104 interface module 130 receives a read request from the CPU, it enters S4 state, sets the BALE signal high and gives the read address of the PC104 interface module 30 to send to the PC104 bus interface 30, and sets both S _ TERM and S _ READY low to make the PCI bus interface 20 in a waiting state;
s5: unconditionally entering into the S5 state, wherein the S5 state is a wait state, and the purpose of holding the high level of two clocks for the BALE signal is to ensure that the PC104 interface module 30 can detect the high level, i.e. to confirm that the read address of the PC104 interface module 30 is valid;
s6: unconditionally entering an S6 state, setting the BALE signal and the IOR signal to be low level at the same time, and initiating a read request to the PC104 bus interface 30;
s7: when the countdown value of the timer is 6, entering an S7 state, completing the read operation of the PC104 bus interface 30, latching the data read from the PC104 bus interface into a register of the PC104 interface module 130, and setting the S _ TERM signal to a low level and the S _ READY signal to a high level to make the PCI bus interface 20 in a retry (retry) state; it is known from the protocol that the PC104 bus interface 30 can place data on the bus at the latest 130ns after the IOR signal is low, and seven clock cycles, i.e., 210ns, elapse from state S6 to state S7 (countdown values from 13 to 7) in total, the time being sufficient to complete the read operation of the PC104 bus interface 30.
S8: when the PCI bus interface 20 completes the retry state, the PC104 interface module 130 clears the retry flag retry.
It is understood that the initial countdown value of the timer may be other values, and the countdown value set from the S3 state to the S0 state and the countdown value from the S6 state to the S7 state may be other values as long as the time between the state transitions is guaranteed to be sufficient for the PCI bus interface 20 to complete the write and read operations to the PC104 bus interface 30.
The embodiment of the invention also provides a communication system. Fig. 4 is a schematic structural diagram of a communication system according to an embodiment of the present invention, please refer to fig. 4, where the system includes a multifunctional vehicle bus MVB network card 50 having the PC104 bus interface 30, the external component interconnect PCI bus interface 20, and the device 10 for communication between the MVB network card and the PCI bus interface according to any of the embodiments.
To facilitate understanding of the present invention, the signal path and pin functions of the apparatus and system are illustrated by table 3:
TABLE 3
Those of ordinary skill in the art will understand that: all or a portion of the steps of implementing the above-described method embodiments may be performed by hardware associated with program instructions. The program may be stored in a computer-readable storage medium. When executed, the program performs steps comprising the method embodiments described above; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (5)
1. An apparatus for communication between a multifunction vehicle bus MVB network card and an external component interconnect PCI bus interface, the apparatus being implemented using a field programmable gate array FPGA, the apparatus comprising:
the external components which are sequentially connected in a communication manner are connected with the PCI interface module, the PCI bus analysis module and the PC104 interface module in a communication manner;
the PCI interface module is used for being connected with a PCI bus interface and carrying out communication interaction based on a PCI protocol with the PCI bus interface;
the PC104 interface module is used for being connected with a PC104 bus interface of the MVB network card and carrying out communication interaction based on a PC104 bus protocol with the MVB network card;
the PCI bus analysis module is used for converting the PCI protocol data from the PCI interface module into PC104 protocol data and sending the PC104 protocol data to the PC104 interface module; converting the PC104 protocol data from the PC104 interface module into PCI protocol data, and sending the PCI protocol data to the PCI interface module;
a PCI bus state setting channel, a PCI bus command and byte enabling control channel are arranged between the PC104 interface module and the PCI interface module;
the PC104 interface module is used for setting the state of the PCI bus interface through the signal of the PCI bus state setting channel;
an address and data bus is arranged between the PCI interface module and the PCI bus analysis module;
the PCI interface module is used for writing an access address effective range into the PCI bus analysis module through the address and data bus and sending a PCI access address to the PCI bus analysis module through the address and data bus;
the PCI bus analysis module is used for determining whether the PCI access address is valid according to the effective range of the PCI access address;
the PC104 interface module also comprises a bus address latch enabling signal pin and a PC104 bus interface write enabling signal pin;
the PC104 interface module is used for confirming whether the write address of the PC104 bus interface is valid according to the signal of the bus address latch enable signal pin;
the device is used for caching write operation data from the PCI bus interface when the PCI bus interface is in a waiting state and a write address of the PC104 bus interface is valid;
and the data processing unit is used for writing the cached write operation data into the PC104 bus interface when the signal of the write enable signal pin of the PC104 bus interface is valid.
2. The apparatus according to claim 1, wherein a first signal input/output channel is provided between the PCI interface module and the PCI bus parsing module; a second signal input/output channel is arranged between the PCI bus analysis module and the PC104 interface module;
the PCI interface module is used for sending an MVB read-write request to the PCI bus analysis module through the first signal input/output channel and receiving an MVB read-write response sent by the PCI bus analysis module through the first signal input/output channel;
the PC104 interface module is configured to receive, through the second signal input/output channel, the MVB read-write request sent by the PCI bus analysis module, and send, through the second signal input/output channel, an MVB read-write response to the PCI bus analysis module.
3. The device of claim 1, wherein an address transmission channel is provided between the PCI interface module and the PC104 interface module, the PCI bus command and byte enable control channel signal is used to indicate read, write, or byte enable control status,
the PCI interface module is used for sending a PCI read-write request or a byte enabling command to the PC104 interface module through the PCI bus command and a byte enabling control channel; and is used for sending PCI access address to the PC104 interface module through the address transmission channel when the PCI bus command and byte enable control channel sends PCI read-write request;
and the PC104 interface module is used for determining the read-write address of the PC104 bus interface according to the PCI access address, the PCI bus command and the specific value of the byte enable command of the byte enable control channel.
4. The apparatus of claim 1, wherein the PC104 interface module further comprises a bus address latch enable signal pin and a PC104 bus interface read enable signal pin,
the PC104 interface module is used for confirming whether the read address of the PC104 bus interface is valid according to the signal of the bus address latch enable signal pin; the PCI bus interface is in a waiting state, the read address of the PC104 bus interface is effective, and the signal of the PC104 bus interface read enable signal pin is effective, the data is read from the PC104 bus interface and cached;
the PCI interface module is further configured to, when the PCI bus interface is in a retry state, read data cached in the PC104 interface module.
5. A communication system, characterized by: comprising a multifunction vehicle bus MVB network card with a PC104 bus interface, an external component interconnect (PCI) bus interface and a device according to any one of claims 1 to 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510765572.3A CN106681951B (en) | 2015-11-11 | 2015-11-11 | Equipment and system for communication between MVB network card and PCI bus interface |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510765572.3A CN106681951B (en) | 2015-11-11 | 2015-11-11 | Equipment and system for communication between MVB network card and PCI bus interface |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106681951A CN106681951A (en) | 2017-05-17 |
| CN106681951B true CN106681951B (en) | 2020-08-25 |
Family
ID=58865231
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510765572.3A Active CN106681951B (en) | 2015-11-11 | 2015-11-11 | Equipment and system for communication between MVB network card and PCI bus interface |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106681951B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107181657B (en) * | 2017-05-31 | 2020-07-17 | 中车信息技术有限公司 | WTB link layer interface adapter and implementation method thereof |
| CN108052468A (en) * | 2017-12-04 | 2018-05-18 | 北京控制与电子技术研究所 | A kind of autonomous controllable pci bus controller based on FPGA |
| CN112241385B (en) * | 2020-10-30 | 2022-09-09 | 中车大连电力牵引研发中心有限公司 | MVB communication network card based on PCIE bus and protocol conversion method |
| CN114064548B (en) * | 2021-11-18 | 2024-05-24 | 中车大连电力牵引研发中心有限公司 | Bus bridge device for realizing EXMC and VME communication |
| CN113810257A (en) * | 2021-11-19 | 2021-12-17 | 成都申威科技有限责任公司 | MVB communication control device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101969389A (en) * | 2010-09-21 | 2011-02-09 | 中国北车股份有限公司大连电力牵引研发中心 | MVB network-based data record analyzer and working method thereof |
| CN102307162A (en) * | 2011-09-08 | 2012-01-04 | 中国北车股份有限公司大连电力牵引研发中心 | Gateway based on MVB (multifunction vehicle bus) network |
| CN104579885A (en) * | 2015-02-05 | 2015-04-29 | 青岛四方车辆研究所有限公司 | Protocol converter and conversion method of CPCI bus and ISA bus |
-
2015
- 2015-11-11 CN CN201510765572.3A patent/CN106681951B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101969389A (en) * | 2010-09-21 | 2011-02-09 | 中国北车股份有限公司大连电力牵引研发中心 | MVB network-based data record analyzer and working method thereof |
| CN102307162A (en) * | 2011-09-08 | 2012-01-04 | 中国北车股份有限公司大连电力牵引研发中心 | Gateway based on MVB (multifunction vehicle bus) network |
| CN104579885A (en) * | 2015-02-05 | 2015-04-29 | 青岛四方车辆研究所有限公司 | Protocol converter and conversion method of CPCI bus and ISA bus |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106681951A (en) | 2017-05-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106681951B (en) | Equipment and system for communication between MVB network card and PCI bus interface | |
| CN106951388B (en) | PCIe-based DMA data transmission method and system | |
| CN110471872B (en) | System and method for realizing M-LVDS bus data interaction based on ZYNQ chip | |
| KR101911059B1 (en) | Test method for UFS interface and memory device testing by the same method | |
| CN108255776B (en) | I3C master device compatible with APB bus, master-slave system and communication method | |
| US20150212959A1 (en) | Inter-component communication including slave component initiated transaction | |
| CN108052750B (en) | SPI FLASH controller based on FPGA and design method thereof | |
| US20170242813A1 (en) | Bus bridge for translating requests between a module bus and an axi bus | |
| Liu et al. | A flexible hardware architecture for slave device of i2c bus | |
| US20120331194A1 (en) | Interface extender for portable electronic devices | |
| CN104714907A (en) | Design method for converting PCI bus into ISA bus or APB bus | |
| KR20100083395A (en) | Method of parallel interfacing and devices using the same | |
| CN115499505B (en) | USB network card and communication method | |
| CN109522251A (en) | A kind of high-speed synchronous serial port board and its working method based on PXIe bus | |
| CN116414767A (en) | Reordering method and system for AXI protocol-based out-of-order response | |
| US11169947B2 (en) | Data transmission system capable of transmitting a great amount of data | |
| RU175049U9 (en) | COMMUNICATION INTERFACE DEVICE SpaceWire | |
| CN214311726U (en) | A adapter plate for prototype is verified | |
| CN104360977A (en) | Method and system for managing high-speed serial transmission interface | |
| CN108228517A (en) | I3C circuit arrangements, system and communication means | |
| CN109614359B (en) | AXI bus-based data transmission method, device and storage medium | |
| CN112398877A (en) | Control signal conversion circuit, intellectual property core and system-level chip | |
| CN112416843A (en) | Backboard communication equipment, control method thereof and storage medium | |
| CN107391406B (en) | Microprocessor for protocol processing and protocol processing method | |
| CN110389919B (en) | RISC-V processor based asynchronous transceiver peripheral and system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB03 | Change of inventor or designer information | ||
| CB03 | Change of inventor or designer information |
Inventor after: Liu Chenxi Inventor after: Jin Xiaoyu Inventor after: Lv Yanwen Inventor after: Zhou Da Inventor before: Zhou Da |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |