CN107181657B

CN107181657B - WTB link layer interface adapter and implementation method thereof

Info

Publication number: CN107181657B
Application number: CN201710398260.2A
Authority: CN
Inventors: 王欢; 万海; 赵曦滨
Original assignee: Tsinghua University; CRRC Qingdao Sifang Rolling Stock Research Institute Co Ltd; CRRC Information Technology Co Ltd
Current assignee: Tsinghua University; CRRC Qingdao Sifang Rolling Stock Research Institute Co Ltd; CRRC Information Technology Co Ltd
Priority date: 2017-05-31
Filing date: 2017-05-31
Publication date: 2020-07-17
Anticipated expiration: 2037-05-31
Also published as: CN107181657A

Abstract

The invention relates to a WTB link layer interface adapter and an implementation method thereof, wherein when a user interacts data through a CPU device where an upper computer adaptation module is positioned, the upper computer adaptation module actively initiates a transmission data packet and receives a data packet through a user virtual interface respectively; data interaction is carried out on the related interface of the FPGA logic layer of the down-link network adapter module through a link layer interface; the WTB network card adaptation module interacts with an Adapter layer of the WTB network card adaptation module upwards through the FPGA logic layer to acquire data, and drives a parallel bus and an upper computer adaptation module to interact and buffer the data downwards; an Adapter layer of the WTB network card adapting module interacts with the FPGA logic layer downwards to acquire data and provides related parameters for a WTB functional interface of a WTB link interface layer upwards. The invention can enable the user to directly call the link layer function interface of the WTB through the CPU where the upper computer is positioned.

Description

WTB link layer interface adapter and implementation method thereof

Technical Field

The invention relates to a device for remotely calling an interface based on bus connection, in particular to a WTB link layer interface adapter and an implementation method thereof.

Background

At present, a WTB (twisted wire train bus) network is a communication bus network for rolling stock, is a serial data communication bus, is used for a large number of reconnection vehicles which are frequently connected and disconnected at home and abroad, has high reliability and flexibility, and is an important component of the IEC61375-1 standard. The IEC61375-1 standard specifies the functional interfaces of the WTB link layer, which include a monitor data interface, a process data interface, and a message data interface. These functional interfaces of the WTB link layer are exposed on the ARM processor. The function of the WTB network card is realized by calling each functional interface exposed by the WTB link layer by a user.

In general, a CPU device board running an application program is separated from a WTB device board, and an upper computer program used by a user is not on the same platform as an actual WTB link layer, so that a user interface exposed by the upper computer cannot actually directly call a function of a functional interface of the WTB link layer.

Disclosure of Invention

The invention aims to solve the problems in the prior art and provides a WTB link layer interface adapter which can assist a user in completing the work of calling a real WTB link layer functional interface from a user interface of an upper computer.

The purpose of the invention is realized by the following technical scheme:

the invention provides a WTB link layer interface adapter, which comprises:

the system comprises an upper computer adaptation module and a WTB network card adaptation module;

the WTB network card adaptation module comprises three layers of architectures, which are respectively: the system comprises a WTB link interface layer, an Adapter layer and an FPGA logic layer; the WTB link interface layer of the WTB network card adapting module provides a WTB functional interface; an Adapter layer of the WTB network card adapting module provides related calling parameters for a WTB functional interface upwards and interacts with an FPGA logic layer downwards to acquire related data; the FPGA logic layer interacts with an Adapter layer of the WTB network card Adapter module upwards to acquire related data, and drives a parallel bus and an upper computer Adapter module to interact and buffer the data downwards;

the upper computer adaptation module comprises a two-layer framework: a WTB link interface layer and an Adapter layer; the WTB link interface layer of the upper computer adaptation module provides a virtual interface of an upper computer user; the Adapter layer of the upper computer adaptation module provides a parameter transmission function for a WTB link interface layer user of the upper computer adaptation module upwards and performs data interaction with a related interface of an FPGA logic layer of the WTB network card adaptation module downwards.

More preferably, the function of the Adapter layer of the WTB network card Adapter module is completed by an ARM chip responsible for logical operations.

More preferably, the function of the FPGA logic layer of the WTB network card adaptation module is implemented by a field programmable gate array FPGA chip responsible for controlling physical and mechanical signals.

The invention also provides a method for realizing the WTB link layer interface adapter, which comprises the following steps:

when a user interacts data through the CPU equipment where the upper computer adaptation module is located, the upper computer adaptation module actively initiates a transmission data packet and a reception data packet through a user virtual interface respectively; data interaction is carried out on the related interface of the FPGA logic layer of the WTB network card adapting module through a link layer interface;

the WTB network card adaptation module interacts with an Adapter layer of the WTB network card adaptation module upwards through an FPGA logic layer to acquire related data, and drives a parallel bus and an upper computer adaptation module to interact and buffer the data downwards; the Adapter layer of the WTB network card adapting module interacts with the FPGA logic layer downwards to acquire related data and provides related parameters for a WTB functional interface of a WTB link interface layer upwards.

More preferably, after the user calls the link layer function interface of the WTB to request data transmission, when the upper computer adaptation module automatically calls the interface to request data transmission to the WTB network card adaptation module, the implementation method includes:

step S101, an upper computer adaptation module acquires data of a link layer functional interface for a user to call WTB through a user virtual interface, and encapsulates the data through an Adapter layer of the upper computer adaptation module;

step S102, an Adapter layer of an upper computer adaptation module adopts a sub-packet transmission mechanism to divide the data of the packaged data buffer into data packets with fixed length;

step S103, an Adapter layer of the upper computer adaptation module sends all divided data packets to an FPGA layer of the WTB network card adaptation module through the FPGA interface in sequence, and confirms the sending result according to the feedback result of the WTB network card adaptation module;

step S104, an Adapter layer of the WTB network card adaptation module receives a data packet in an FPGA layer of the WTB network card adaptation module based on an Adapter state machine;

step S105, after the WTB network card adaptation module receives all the data packets, the WTB link interface layer of the WTB network card adaptation module executes the WTB link layer interface function;

and S106, the upper computer adaptation module waits for the return of the calling result and outputs the return result after receiving the return result.

More preferably, the process of step S103 includes:

aiming at each data packet, an Adapter layer of the upper computer adaptation module sends the data packet to a WTB network card adaptation module through an FPGA interface;

after the upper computer adaptation module receives RST confirmation data sent by the WTB network card adaptation module through the FPGA interface, an Adapter layer of the upper computer adaptation module judges whether the packet sending is successful according to the content of the RST confirmation data, and returns the result to a WTB link interface layer of the upper computer adaptation module.

More preferably, in step S103, the process of sending each data packet to the WTB network card adapting module by the upper computer adapting module through the FPGA interface includes:

the adapter layer of the upper computer adapter module checks whether data can be written into the FPGA interface or not, if the data cannot be written, the query is repeated until the query times reach a certain upper limit value, the occurrence of an overtime error is considered, and the upper computer adapter module directly returns the error; if the data can be written, firstly sending a data writing command, then writing the data length and writing the data into an FPGA chip positioned on an FPGA logic layer of the WTB network card adaptation module according to bytes sequentially through an FPGA receiving register; after the FPGA chip acquires the data, the data is written into a specific position of a shared memory, an upper computer adaptation module is sent to send data interruption to an ARM chip of an Adapter layer of a WTB network card adaptation module, and the ARM chip is informed that a new data packet arrives; after the ARM chip processes the interrupt, the shared memory is accessed in the main cycle, and the data is read out.

More preferably, the adapter state machine in step S104 has the following three states:

RECV _ ARG _ HEAD state, RECV _ ARG state, and SEND _ RESU L T state;

RECV _ ARG _ HEAD state: under the default condition, the adapter state machine is in the state, and continuously polls whether the upper computer in the FPGA sends or not data packets; if the polling error err indicates that no data packet exists; if the data packet is not the head packet or the data packet has wrong format, returning to the state for re-polling according to the err condition; only when the correct head packet is polled, the state machine enters an RECV _ ARG state according to an ok condition and continues to receive other possible data packets;

the RECV _ ARG state is that the adapter state machine judges whether all data are received completely or not, if the current receiving is correct and not, other data packets are continuously received under the state, if any data packet receiving is wrong, the adapter state machine returns to the RECV _ ARG _ HEAD state according to the err condition to restart waiting for the next interface calling, if the receiving is correct, the adapter state machine calls the corresponding link layer interface function by using the received parameters, and enters the SEND _ RESU L T state to return the execution result after the execution is finished and the execution result is obtained;

and a SEND _ RESU L T state, in which the adapter state machine divides the encapsulated execution result into data packets and sequentially SENDs the data packets to the upper computer adaptation module in sequence, if the transmission is wrong or finished, the adapter state machine returns to the RECV _ ARG _ HEAD state to restart, otherwise, the adapter state machine continues to SEND the data packets in the state.

More preferably, after the user calls the link layer function interface of the WTB to request data transmission, when the upper computer adaptation module automatically calls the interface to request to receive the return data of the execution result of the WTB network card adaptation module, the implementation method includes:

step S201, an upper computer adaptation module sends a data receiving request, receives a data request transmission packet through an Adapter layer structure of the upper computer adaptation module, and sends the data request transmission packet to a WTB network card adaptation module through an FPGA interface;

step S202, after receiving a data receiving request of the upper computer adaptation module, the WTB network card adaptation module encapsulates effective result data into data packets, and returns all the data packets to the upper computer adaptation module in sequence through the FPGA logical layer according to a sub-packet transmission mechanism;

step S203, the upper computer adaptation module acquires the data packet returned by the WTB network card adaptation module from the FPGA layer, analyzes the data packet to acquire result data, and transmits the result data to the upper WTB link interface layer.

More preferably, the process of the WTB network card adaptation module sending each data packet through the FPGA logic layer in step S202 includes:

the upper computer adaptation module checks whether data exist or not by polling whether the FPGA interface state is readable or not; after an ARM chip of an adaptation layer of a WTB network card adaptation module prepares data, the data is written into a specific position of a data area of a shared memory, and then a 'set readable' Request command and a corresponding parameter value are written into the specific position of a command area; after the FPGA chip of the FPGA logic layer of the WTB network card adaptation module inquires a command, setting an FPGA interface to be readable and writable; when the upper computer adaptation module acquires valid data during polling, writing a read command word; then the upper computer adaptation module reads out the data length and reads out each byte of the data in sequence according to the length; after the upper computer adaptation module reads all data in the data packet, the FPGA chip sets the FPGA interface of the upper computer adaptation module to be unreadable, and transmission of the data packet from the WTB network card adaptation module to the upper computer adaptation module is completed.

The technical scheme of the invention can show that the invention has the following technical effects:

1. because the invention comprises the upper computer adaptation module where the CPU board card is located and the WTB network card adaptation module where the WTB board card is located, a user can directly call the link layer function interface of the WTB through the CPU equipment where the upper computer is located, the remote call (RPC) function of the link layer interface of the WTB is realized, and the invention is completely transparent to a user program.

2. Because the invention operates an adapter state machine at the WTB network card adaptation module end, the state machine ensures that no matter which party has errors, data receiving and sending can not be trapped in busy waiting to cause false death of programs, thereby greatly ensuring the availability and stability of the WTB link layer interface adapter of the invention.

Drawings

FIG. 1 is a block diagram of a WTB link layer adapter according to the present invention;

fig. 2 is a timing diagram of the implementation method of the WTB link layer adapter according to the present invention after the upper computer adapter module requests the WTB network card adapter module to send data;

fig. 3 is a flowchart illustrating an implementation of the method for implementing the WTB link layer adapter according to the present invention after the upper computer adapter module requests the WTB network card adapter module to send data;

FIG. 4 is a flow diagram of the packetization transport mechanism of the adapter communication protocol in accordance with the present invention;

FIG. 5 is a format diagram of a header packet according to the present invention;

FIG. 6 is a format diagram of a non-header packet according to the present invention;

fig. 7 is a flow chart of a data transmission mechanism followed when the upper computer adaptation module sends each data packet to the WTB network card adaptation module;

fig. 8 is a timing diagram of the implementation method of the WTB link layer interface adapter according to the present invention after the upper computer adapter module requests the WTB network card adapter module to receive data;

fig. 9 is a flowchart illustrating an implementation of the method for implementing the WTB link layer adapter according to the present invention after the upper computer adapter module requests the WTB network card adapter module to receive data;

fig. 10 is a flow chart of a data transmission mechanism followed by the WTB network card adaptation module of the present invention when sending each data packet to the upper computer adaptation module after the upper computer adaptation module requests the WTB network card adaptation module to receive data.

Detailed Description

The technical solution of the present invention will be further described in detail with reference to the accompanying drawings.

Example one

The invention provides a WTB network card link layer interface adapter, the structure of which is shown in figure 1, and can be seen as follows:

the WTB network card link layer interface adapter is transversely mainly divided into two parts: the upper computer adaptation module where the CPU board card is located and the WTB network card adaptation module where the WTB board card is located.

Wherein the WTB network card adaptation module comprises three layers of architectures which are respectively as follows: the system comprises a WTB link interface layer, an Adapter layer and an FPGA logic layer. The WTB link interface layer provides a WTB functional interface. The Adapter layer functions as: providing related parameters for the WTB functional interface upwards, and interacting with the FPGA logic layer downwards to acquire related data; the Adapter layer is completed by an ARM chip which is responsible for complex logic operation. The function of the FPGA logic layer is as follows: the interaction with an Adapter layer is required upwards to acquire related data; and the downward driving parallel bus interacts with the upper computer and buffers data. These functions of the FPGA logic layer are performed by an FPGA (Field-Programmable gate array) chip that is responsible for controlling physical and mechanical signals. The FPGA chip and the ARM chip can be connected through a parallel bus interface.

The upper computer adaptation module comprises a two-layer framework: a WTB link interface layer and an Adapter layer. The WTB link interface layer provides a virtual interface of a host computer user; the Adapter layer provides a link layer interface for users of the WTB link interface layer upwards, and needs to perform data interaction with a related interface of the FPGA chip downwards. The upper computer adaptation module is directly connected with the FPGA chip of the WTB network card adaptation module through a parallel bus, so that the FPGA chip has an FPGA interface logic which corresponds to the transmission logic of the bottom layer of the adapter of the upper computer. And the program interaction between the FPGA and the ARM is realized through a shared memory and interrupt of an FPGA chip. Meanwhile, the FPGA interface logic interacts with the communication logic of the ARM chip to realize the related functions of the communication protocols of the upper computer adaptation module and the WTB network card adaptation module.

And the upper computer adaptation module and the WTB network card adaptation module transmit physical signals and data through the FPGA logical layer. The communication protocol of the adapter is divided into three layers, namely a data encapsulation and analysis layer, a data packetization and receiving layer and a data packet (byte stream) sending and receiving layer. In order to realize the RPC function, the adapter communication protocol needs to encapsulate the interface number of the call interface, the RPC related parameters, and the like, and correctly resolve the interface number and the RPC related parameters at the other end. After the interface is called, the calling result also needs to be packaged and transmitted to the caller for analysis.

Example two

The invention also provides a method for realizing the WTB link layer interface adapter, wherein the process that a user calls the link layer functional interface interaction data of the WTB through the CPU equipment where the upper computer adaptation module is located comprises two conditions: one is the case of requesting data transmission, and the other is the case of requesting data reception. In any case, the upper computer adaptation module is always the master of communication, and the FPGA chip is controlled to complete the data receiving and transmitting function by sending a command to the FPGA chip. After the upper computer adaptation module initiatively initiates a communication request, the data is finally transmitted and received by the bottom layer and the FPGA chip of the WTB network card adaptation module through the processing of the Adapter layer. When the upper computer adaptation module initiatively initiates a communication request, the upper computer adaptation module can generate two stages, namely a sending stage and a receiving stage, through one-time interface calling. In the sending stage, an Adapter layer of the upper computer adaptation module is responsible for packaging calling parameters and the like, dividing the calling parameters into a plurality of data packets and sending the data packets to the WTB network card adaptation module in sequence; in the receiving stage, the Adapter layer of the upper computer is responsible for splicing the execution result returned by the WTB network card Adapter module into correct data again and returning the analyzed data to the WTB link interface layer. Therefore, the method for implementing the WTB link layer interface adapter provided by the present invention includes the following two processing procedures: after a user calls a link layer functional interface of the WTB to request data transmission, the upper computer adaptation module requests a processing process of data transmission to the WTB network card adaptation module; and after the user calls the link layer functional interface of the WTB to request to receive the data, the upper computer adaptation module requests the WTB network card adaptation module to receive the processing procedure of the data. And the upper computer adaptation module in each processing process has a sending stage and a receiving stage.

These two processes are described in detail below with reference to fig. 2-10, respectively:

first, the upper computer adaptation module requests the WTB network card adaptation module to transmit data

And the upper computer adaptation module executes the process of sending data to the ATM platform by the upper computer adaptation module after the user calls the link layer functional interface of the WTB to request for data transmission. The process of sending data by the upper computer is completed by a Send stage and a Recv stage, and data sending and result sending confirmation are respectively completed. The data sending request is initiated by the upper computer, and after the upper computer adaptation module initiates the data sending request, the sending stage is firstly entered, and data packaging, sub-packaging and sending are carried out; when the ATM returns the execution result, the Recv phase is entered. In this case, a timing chart of the implementation method of the WTB link layer interface adapter of the present invention is shown in fig. 2:

in the Send stage, the data encapsulated by the upper computer adaptation module is divided into data packets, and then the data packets (byte streams) are sent. And the data packet (byte stream) sending layer sends all the divided data packets to the WTB network card adaptation module in sequence. Before each data packet is sent, data encapsulation is carried out firstly, then the upper computer adaptation module transmits the packet, and the data packet is sent to the WTB network card adaptation module end.

After the WTB network card adaptation module receives the packet, the WTB network card adaptation module needs to notify the upper computer terminal of whether the packet is successfully sent or not by using one byte of confirmation data (such as RST confirmation). For example, when the packet content has an error, the confirmation data RST is 0 xFF. When the packet is successfully received, the data RST is confirmed to be 0x 01.

In the Recv stage, after the upper computer receives the confirmation data, whether the packet sending is successful is judged according to the content of the confirmation data, and the result is returned to the upper layer. And when the transmission of one data packet is finished, other data packet transmission and other operations can be carried out.

In this case, a specific implementation procedure of the method for implementing a WTB link layer interface adapter according to the present invention is shown in fig. 3, and includes the following procedures from step S101 to step S105:

and S101, packaging data by the upper computer adaptation module.

When a user calls a link layer functional interface of the WTB to request data transmission, the upper computer adaptation module acquires an interface number and parameters of the link layer functional interface of the WTB called by the user and packages the interface number and the parameters.

At one end of the upper computer adaptation module, when a user calls a link layer interface, an Adapter layer of the upper computer adaptation module needs to receive and acquire an interface number and parameters of a link layer functional interface of the WTB called by the user, and encapsulates the interface number and the parameters. When data is packaged, firstly, 4 bytes of interface numbers (function serial numbers) are put into a parameter buffer area; then, for each interface parameter value, sequentially packaging the interface parameter value into a parameter buffer area according to the sequence of the interface parameter value in the interface declaration; and finally, adding a CRC (cyclic redundancy check) value of 4 bytes, and sending the CRC value to the next layer by calling a trans _ Send () interface.

And step S102, data subpackaging.

In this step, the upper computer adaptation module is responsible for dividing the data of the packaged data buffer into data packets with fixed length so as to send all the data packets to the WTB network card adaptation module in the following process.

For some link layer interface calls, the call parameter and return value data lengths may be on the order of kilobytes. Packaged data of this magnitude are prone to errors if transmitted through hardware at one time, and it is difficult for the FPGA to partition into enough buffers to store the data. In addition, if an interrupt is sent during data transmission, a packet transmission mechanism is needed to ensure that both ends of the adapter return to a normal state to restart, and simultaneously, the problem of data crosstalk when other interfaces are called again after the interrupt is avoided.

The sub-packet transmission mechanism is shown in fig. 4, the left side is a data sub-packet and packet receiving layer of the upper computer adaptation module, and the right side is a data sub-packet and packet receiving layer of the WTB network card adaptation module. By the sub-packet transmission mechanism, the data encapsulated by the upper layer is divided into data packets with fixed length and then sequentially transmitted.

When data is packaged, the upper computer adaptation module divides the data packet into a head packet format and a non-head packet format, wherein the first data packet is in the head packet format, and other data packets conform to the non-head packet format. And then calling a gp _ command _ p () interface to send each data packet to the next layer for transmission.

The header format is shown in fig. 5, and the non-header format is shown in fig. 6. The length of both the header packet and the non-header packet is 122 bytes at maximum. For the head packet and the non-head packet, the first byte is divided into three parts, namely a head packet mark of the highest bit, a callback mark of the second highest bit and a serial number SN field consisting of the other six bits.

The header flag is 1 to indicate that the packet is a header packet, and 0 to indicate a non-header packet.

If the callback mark is 1, it indicates that some event occurs in the WTB link layer, and the upper computer end needs to be notified to perform callback.

The SN field indicates the sequence number of the packet, and in the process of one adapter interface call, the SN of the packet of the transmission parameter and the reception result is consistent. Once the inconsistency occurs, the adapter knows that the last transmission has been interrupted and should start an interface call for a new SN, thus avoiding call interruption and data crosstalk. After the execution of one call, SN will add 1 and start to prepare for the next call. When the maximum value 63 is reached, the SN returns to a value of 0 for continued use.

One special field of the header packet is that 4 bytes after the first byte represent the total length of data, which is the total length of data to be transmitted by the current interface call and is stored in a big end form. The non-header packet has no field, and the data part is added directly after the first byte. Thus, the data portion of the header packet is 117 bytes at the maximum, and the data portion of the non-header packet is 121 bytes at the maximum. If the total data length required to be transmitted does not exceed 117 bytes, one header packet can be transmitted. Otherwise, after the head packet is sent, a plurality of non-head packets are sent according to the rest data length.

In step S103, a packet (byte stream) is transmitted.

And the data packet (byte stream) sending layer is responsible for sequentially sending all the divided data packets to the WTB network card adaptation module, and the data packaged by the upper computer adaptation module is divided into a plurality of data packets and then delivered to the data packet (byte stream) sending layer for sending. And the data packet (byte stream) sending layer sends all the divided data packets to the WTB network card adaptation module in sequence. And the upper computer sends the data packet to a WTB network card adaptation module end through the FPGA interface. And after receiving the confirmation data of the WTB network card adaptation module end, the upper computer adaptation module judges whether the packet is successfully sent or not according to the content of the confirmation data, and returns the result to the upper layer. And when the transmission of one data packet is finished, other data packet transmission and other operations can be carried out.

For each data packet, the upper computer adaptation module follows a data transmission mechanism when sending to the WTB network card adaptation module, as shown in fig. 7, where the arrow direction in the figure indicates the data direction. As can be seen in fig. 7, each packet is sent through 6 steps:

firstly, an adapter of an upper computer adapter module checks whether data can be written into an FPGA interface, if the data can not be written, the data are repeatedly inquired until the inquiry times reach a certain upper limit value, an overtime error is considered to occur, and the upper computer adapter directly returns an error; if the data can be written, firstly sending a data writing command, then writing the data length, and writing the data into the FPGA chip through the FPGA receiving register according to the bytes in sequence. After the FPGA chip acquires the data, the data is written into a specific position of the shared memory, an upper computer sends a data interrupt to the ARM chip, and the ARM chip is informed that a new data packet arrives. At this time, after the ARM chip processes the interrupt, the shared memory is accessed in the main cycle, and the data is read out.

Step S104, the WTB network card adaptation module receives the data packet.

As shown in the right side of fig. 4, the adapter end of the WTB network adapter module runs a state machine of a communication protocol, and the state machine has three states, namely, RECV _ ARG _ HEAD state, RECV _ ARG state and SEND _ RESU L T state, which respectively implement the receiving and sending of the data packet of the WTB network adapter module.

Firstly, the state machine enters an RECV _ ARG state after receiving a correct header packet in a default RECV _ ARG _ HEAD state; in the RECV _ ARG state, other non-header packet data is received. The ARM end analyzes the data packet at the moment and obtains the length of the packet header and the command word information. And then the ARM sends the two fields and the packet data to an upper layer data encapsulation and analysis layer of the protocol for processing, the layer firstly judges whether the length is legal or not, then checks whether the command word is 'P', analyzes the content of the data packet, acquires the information of a head packet and SN, and jointly judges whether the packet is effective or not.

The following describes tasks executed in three states of the communication protocol state machine operated by the WTB network card adaptation module and migration conditions.

RECV _ ARG _ HEAD state: and under the default condition, the state machine is in the state, and continuously polls the upper computer in the FPGA to send or not send data packets. If the polling error err indicates that no data packet exists; if there is a data packet, but the data packet is not a header packet, or the format of the data packet itself is wrong, the status is returned to the state for re-polling according to the err condition. The state machine therefore enters the RECV _ ARG state in ok condition only when the correct header packet is polled, continuing to receive other possible data packets. The purpose of this state is mainly to intercept the impact of erroneous packets. Ensuring that each time a correct adapter interface call is made.

If the current reception is correct AND NOT completed, the other data packets are continuously received under the state according to an ok AND NOT fin condition, if any data packet reception is wrong, the data packets are returned to the RECV _ ARG _ HEAD state according to an err condition to restart waiting for the next interface call, if the data packets are correctly received, the corresponding link layer interface function is called by using the received parameters, AND after the execution is completed AND the execution result is obtained, the data packets enter a SEND _ RESU L T state according to the ok AND fin condition to return the execution result.

AND a SEND _ RESU L T state, in which the state machine also divides the encapsulated execution result into data packets AND sequentially SENDs the data packets to the host computer end in sequence.

Step S105, after the WTB network card adapting module receives all the data packets, the WTB network card adapting module executes the WTB link layer interface function.

In the state machine RECV _ ARG state, after receiving all data packets, performing data analysis on an Adapter layer of a WTB network card adaptation module, checking whether crc check is correct or not, then acquiring an interface number and parameters, calling a real interface function executed by a WTB link layer interface, and after execution is finished, entering a SEND _ RESU L T state to wait for packaging an execution result and sending the execution result to an upper computer adaptation module.

And when the upper computer adaptation module sends all the data packets completely, the data packets enter a Recv receiving stage, an Adapter layer of the upper computer adaptation module waits for the return of the calling result, and when the return result is received, the upper computer adaptation module outputs the return result.

Therefore, remote calling and execution of the WTB link layer interface function are realized.

Secondly, the upper computer adaptation module requests the WTB network card adaptation module to receive data

After the user calls the link layer functional interface of the WTB to request to receive data, the upper computer adaptation module completes the process of receiving a data packet by the upper computer through a Send stage and a Recv stage, and the process corresponds to the data receiving request stage and the data packet replying stage respectively. The data receiving request is initiated by the upper computer automatically, and after the upper computer adaptation module initiates the data receiving request, the sending Send stage is started first to carry out data packaging, sub-packaging and sending; when the ATM returns the execution result, the Recv phase is entered. In this case, a timing chart of the implementation method of the WTB link layer interface adapter of the present invention is shown in fig. 8:

the left side is an upper computer adaptation module, and the right side is a WTB network card adaptation module. The process that the host computer enters the Send phase and sends and receives the data packet of the data request command is similar to the process of the Send phase in the step S101, except that the data packet is sent by calling the gp _ command _ g () interface. When the upper computer enters the recv stage, a transmission packet header is firstly constructed according to data fed back by the WTB network card adaptation module, and the format of the transmission packet header is the same as that described in the Send stage and is also two bytes. The first byte is 0, indicating no data transfer. The second byte is a command character 'g', which indicates that the data transmission is to acquire data from the ARM, and no other data exists after the header. And then the upper computer adaptation module transmits the data.

In this case, a specific implementation procedure of the method for implementing a WTB link layer interface adapter according to the present invention is shown in fig. 9, and includes the following procedures from step S201 to step S203:

step S201, the upper computer adaptation module sends a data receiving request.

The upper computer actively initiates a data receiving request, receives a data request data packet through the Adapter layer structure, performs data encapsulation and sub-packaging, and sends the data request data packet to the WTB network card adaptation module through the FPGA interface, which is the same as the process of the Send stage in the step S101, except that the gp _ command _ g () interface is called to actively initiate a data receiving request.

Step S202, the WTB network card adaptation module returns the executed result data.

The WTB network card adaptation module analyzes the received data, judges whether the length is legal or not, then checks whether the command character is 'g' or not to judge whether a data packet is valid or not, if the data packet is invalid, does not reply any data, if the data packet is valid, the result data is also subjected to data packaging, sub-packaging and transmission, and the execution result is transmitted back to the upper computer adaptation module through the FPGA layer through the SEND _ RESU L T state in a state machine in the WTB network card adaptation module adapter protocol.

For the sending of each data packet, the WTB network card adaptation module adopts the data transmission mechanism shown in fig. 10 to the upper computer adaptation module, and the arrow in the figure indicates the data transmission direction.

In a data transmission mechanism used in the process of sending data to the upper computer adaptation module by the WTB network card adaptation module, the upper computer adaptation module checks whether data exists or not by polling the readable mode of the FPGA interface state because the FPGA chip cannot directly inform the upper computer that new data arrives; after the ARM chip prepares data, the data is written into a specific position of a data area of the shared memory, and then a 'set readable' Request command and a corresponding parameter value are written into a specific position of a command area. After the FPGA chip inquires the command, the FPGA interface is set to be readable and writable. And at the moment, the upper computer adaptation module acquires valid data during polling, and writes the read command word in. And then the upper computer adaptation module reads out the data length and sequentially reads out each byte of the data according to the length. After the upper computer adaptation module reads all data in the data packet, the FPGA chip sets the FPGA interface of the upper computer adaptation module to be unreadable, and the data packet is transmitted from the WTB network card adaptation module to the upper computer adaptation module.

And step S203, the upper computer adaptation module receives the result data and transmits the result data.

The upper computer adaptation module calls the gp _ command _ g () interface in step S201 and simultaneously acquires the data packet returned by the WTB network card adaptation module from the FPGA layer. First, a header packet is obtained, the size of the whole data is calculated, and then the data of the non-header packet is continuously received. And after all the data packets are received, analyzing the result, analyzing the crc check code of 4 bytes, then carrying out the execution result label of 1 byte, then carrying out the return data of a plurality of bytes, and transmitting the result data to the upper layer.

And at this point, completing one remote call of the WTB link layer interface function and returning an execution result.

The technical scheme of the invention can ensure that the data packet can be correctly transmitted through the processing of each data packet in the sending stage and the receiving stage, and both sides can know the result of one-time data packet sending, thereby informing the upper layer to carry out corresponding processing. In addition, the logic of sending and receiving the data packet by the upper computer adaptation module is practically unified, namely two stages of sending a command and a parameter and obtaining a return result are realized, so that the complexity of FPGA logic processing is simplified, and the realization is convenient.

Although the present invention has been described in terms of the preferred embodiment, it is not intended that the invention be limited to the embodiment. Any equivalent changes or modifications made without departing from the spirit and scope of the present invention also belong to the protection scope of the present invention. The scope of the invention should therefore be determined with reference to the appended claims.

Claims

1. A WTB link layer interface adapter, wherein the WTB link layer interface adapter comprises:

the upper computer adaptation module consists of a two-layer framework of a WTB link interface layer and an Adapter layer; the WTB link interface layer of the upper computer adaptation module provides a virtual interface of an upper computer user; the Adapter layer of the upper computer adaptation module provides a parameter transmission function for a WTB link interface layer user of the upper computer adaptation module upwards, and performs data interaction with a related interface of an FPGA logic layer of the WTB network card adaptation module downwards;

when a user calls a link layer functional interface of the WTB for data interaction through the CPU equipment where the upper computer adaptation module is located, the upper computer adaptation module actively initiates a communication request and realizes data sending and receiving through one-time interface calling; in the data sending stage, an Adapter layer of the upper computer adaptation module is responsible for packaging the calling parameters, dividing the calling parameters into a plurality of data packets and sending the data packets to the WTB network card adaptation module in sequence; in the data receiving stage, the Adapter layer of the upper computer is responsible for splicing the execution result returned by the WTB network card Adapter module into correct data again, and returning the analyzed data to the WTB link interface layer.

2. The WTB link layer interface Adapter according to claim 1, wherein the Adapter layer of the WTB network card Adapter module is implemented by an ARM chip responsible for logic operations.

3. The WTB link layer interface adapter according to claim 1, wherein the function of the FPGA logic layer of the WTB network card adapter module is performed by a FPGA chip in charge of controlling physical and mechanical signals.

4. The method for implementing a WTB link layer interface adapter according to any of claims 1 to 3, wherein the method for implementing the WTB link layer interface adapter comprises the following steps:

5. The method according to claim 4, wherein the upper computer adaptation module automatically calls the interface to request data transmission to the WTB network card adaptation module after the user calls the link layer function interface of the WTB to request data transmission, the method comprises:

step S103, an Adapter layer of the upper computer adaptation module sends all the divided data packets to an FPGA logic layer of the WTB network card adaptation module through an FPGA interface in sequence, and confirms the sending result according to the feedback result of the WTB network card adaptation module;

step S104, an Adapter layer of the WTB network card adaptation module receives a data packet in an FPGA logic layer of the WTB network card adaptation module based on an Adapter state machine;

6. The method for implementing a WTB link layer interface adapter according to claim 5, wherein said step S103 comprises:

7. The method according to claim 5, wherein in step S103, the process of the upper computer adapter module sending each data packet to the WTB network card adapter module through the FPGA interface includes:

the adapter layer of the upper computer adapter module checks whether data can be written into the FPGA interface or not, if the data cannot be written, the query is repeated until the query times reach a certain upper limit value, the occurrence of an overtime error is considered, and the upper computer adapter module directly returns the error; if the data can be written, firstly sending a data writing command, then writing the data length and writing the data into an FPGA chip positioned on an FPGA logic layer of the WTB network card adaptation module according to bytes through an FPGA interface receiving register in sequence; after the FPGA chip acquires the data, the data is written into a specific position of a shared memory, an upper computer adaptation module is sent to send data interruption to an ARM chip of an Adapter layer of a WTB network card adaptation module, and the ARM chip is informed that a new data packet arrives; after the ARM chip processes the interrupt, the shared memory is accessed in the main cycle, and the data is read out.

8. The method for implementing a WTB link layer interface adapter according to claim 5, wherein the adapter state machine in step S104 has three states:

RECV _ ARG _ HEAD state, RECV _ ARG state, and SEND _ RESU L T state;

RECV _ ARG _ HEAD state: under the default condition, the adapter state machine is in the state, and continuously polls whether the upper computer in the FPGA interface sends or not data packets; if the polling error err indicates that no data packet exists; if the data packet is not the head packet or the data packet has wrong format, returning to the state for re-polling according to the err condition; only when the correct head packet is polled, the state machine enters an RECV _ ARG state according to an ok condition and continues to receive other possible data packets;

9. The method according to claim 4, wherein the upper computer adaptation module automatically calls the interface to request to receive the return data of the execution result of the WTB network card adaptation module after the user calls the link layer function interface of the WTB to request the transmission of data, the method comprises:

10. The method according to claim 9, wherein the step S202 of sending each data packet by the WTB network card adapter module through the FPGA logic layer includes: