CN107181657A - A kind of WTB link layer interfaces adapter and its implementation - Google Patents
A kind of WTB link layer interfaces adapter and its implementation Download PDFInfo
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- CN107181657A CN107181657A CN201710398260.2A CN201710398260A CN107181657A CN 107181657 A CN107181657 A CN 107181657A CN 201710398260 A CN201710398260 A CN 201710398260A CN 107181657 A CN107181657 A CN 107181657A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40032—Details regarding a bus interface enhancer
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/02—Details
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/40267—Bus for use in transportation systems
- H04L2012/40293—Bus for use in transportation systems the transportation system being a train
Abstract
The present invention relates to a kind of WTB link layer interfaces adapter and its implementation, wherein when user is by CPU device interaction data where host computer adaptation module, host computer adaptation module actively initiates transmission packet and received data packet respectively by user's virtual interface；And the relevant interface by link layer interface downwards with the fpga logic layer of WTB network card adaptation module carries out data interaction；WTB network card adaptation module is interacted to obtain data with Adapter layers of the adapter of WTB network card adaptation module upwards by fpga logic layer, and downward driving parallel bus is interacted with host computer adaptation module, buffered data；Adapter layers of the adapter of WTB network card adaptation module interacts to obtain data with fpga logic layer downwards, and the WTB functional interfaces for WTB LI(link interface)s layer provide relevant parameter upwards.The present invention can make user directly invoke WTB link layer functionality interface by CPU where host computer.
Description
Technical field
The present invention relates to the device of the far call interface connected based on bus, more particularly to a kind of WTB link layer interfaces
Adapter and its implementation.
Background technology
At present, WTB (wired train bus) network is a kind of communication bus network for rolling stock, and it is a kind of
Serial data communications busses, are at home and abroad largely used to often mutually interconnection and hang on the vehicle of connection again that reconciliation connects, possessing height can at present
It is an important component of IEC61375-1 standards by property and flexibility.Work(of the IEC61375-1 standards to WTB link layers
Energy interface is made that specified in more detail, and the functional interface of WTB link layers includes monitoring data-interface, process data interface and message count
According to interface.These functional interfaces of WTB link layers are on arm processor.The function of WTB network card is user by calling
Each functional interface that WTB link layers are exposed is realized.
Under normal circumstances, the CPU device plate of operation application program is separated with WTB device boards, on user is used
Position machine program and actual WTB link layers be not in identical platform, therefore the user interface that host computer is exposed is actually simultaneously
The function of WTB link layer functionality interfaces can not be directly invoked.
The content of the invention
The purpose of the present invention is that there is provided a kind of WTB link layer interfaces adapter, its energy the problem of presence for prior art
User is enough assisted to complete to call the work of real WTB link layer functionalities interface from the user interface of host computer.
The purpose of the present invention is achieved through the following technical solutions：
The present invention provides a kind of WTB link layer interfaces adapter, and it includes：
Host computer adaptation module and WTB network card adaptation module；
The WTB network card adaptation module includes three-tier architecture, is respectively：WTB LI(link interface)s layer, Adapter layers of adapter
With fpga logic layer；The WTB LI(link interface)s layer of the WTB network card adaptation module provides WTB functional interfaces；The WTB network card is fitted
Adapter layers of the adapter with module provides the call parameters of correlation for WTB functional interfaces upwards, enters with fpga logic layer downwards
Interaction is gone to obtain related data；Adapter layers of the adapter of the fpga logic layer upwards with the WTB network card adaptation module
Interact to obtain related data, downward driving parallel bus is interacted with host computer adaptation module, buffered data；
Host computer adaptation module includes two-tiered structure：Adapter layers of WTB LI(link interface)s layer and adapter；The host computer
The WTB LI(link interface)s layer of adaptation module provides host computer user's virtual interface；The adapter of the host computer adaptation module
Adapter layers provide parameter transmitting functions to the WTB LI(link interface)s layer user of the host computer adaptation module upwards, downwards then with
The relevant interface of the FPGA logical layers of the WTB network card adaptation module carries out data interaction.
It is highly preferred that the function of Adapter layers of the adapter of the WTB network card adaptation module is by being responsible for logical operation
ARM chips are completed.
It is highly preferred that the function of the fpga logic layer of the WTB network card adaptation module is believed by being responsible for control physics and machinery
Number on-site programmable gate array FPGA chip complete.
The present invention also provides a kind of implementation method of WTB link layer interfaces adapter, and it includes：
When user is by CPU device interaction data where host computer adaptation module, host computer adaptation module by using
Family virtual interface actively initiates transmission packet and received data packet respectively；And by link layer interface downwards with the WTB nets
The relevant interface of the fpga logic layer of card adaptation module carries out data interaction；
Adapter of the WTB network card adaptation module by fpga logic layer upwards with the WTB network card adaptation module
Adapter layers are interacted to obtain related data, and downward driving parallel bus is interacted with host computer adaptation module, buffer number
According to；Adapter layers of the adapter of the WTB network card adaptation module interacts to obtain dependency number with fpga logic layer downwards
According to the WTB functional interfaces for WTB LI(link interface)s layer provide the parameter of correlation upwards.
It is highly preferred that host computer adaptation module is after user calls WTB link layer functionality interface requests to transmit data, when
When the automatic calling interface request data transfer of host computer adaptation module is to WTB network card adaptation module, the implementation method includes：
Step S101, host computer adaptation module obtains user by user's virtual interface and calls WTB link layer functionality to connect
The data of mouth, by its adapter, Adapter layers are packaged the data；
Step S102, Adapter layers of the adapter of host computer adaptation module uses divided stator frame mechanism, by packaged number
The packet of regular length is divided into according to the data of buffering area；
Step S103, Adapter layers of the adapter of host computer adaptation module passes sequentially through all packets after segmentation
FPGA interface is sent to the FPGA layers of WTB network card adaptation module, and is transmitted according to the feedback result of WTB network card adaptation module
As a result confirmation；
Step S104, Adapter layers of the adapter of WTB network card adaptation module is suitable to WTB network card based on adapter state machine
Packet in FPGA layers with module is received；
Step S105, after WTB network card adaptation module has received all packets, the WTB chains of WTB network card adaptation module
Road interface layer performs WTB link layer interface functions；
Step S106, host computer adaptation module waits the return of call result, and after returning result is received, will return
As a result export.
It is highly preferred that the process of the step S103 includes：
For each packet, Adapter layers of the adapter of host computer adaptation module is by FPGA interface by the packet
It is sent to WTB network card adaptation module；
Host computer adaptation module is received after the RST confirmation data that WTB network card adaptation module is sent by FPGA interface, on
Adapter layers of the adapter of position machine adaptation module confirms that the content of data judges that this is given out a contract for a project and whether succeeded according to the RST, and will
As a result the WTB LI(link interface)s layer of host computer adaptation module is returned to.
It is highly preferred that in the step S103, host computer adaptation module sends each packet to WTB by FPGA interface
The process of network interface card adaptation module includes：
The adapter layer of host computer adaptation module, which is checked whether, to write data to FPGA interface, if not writeable, repeatedly
Inquiry, until when inquiry times reach certain higher limit, then it is assumed that time-out error occurs, host computer adaptor module is directly returned
Mistake；If writeable, send one first and write data command, data length is write afterwards and data are passed sequentially through into FPGA by byte
Receiving register write-in is in the fpga chip of the fpga logic layer of WTB network card adaptation module；Fpga chip gets data
Afterwards, it is written into the ad-hoc location of shared drive, and sends a host computer adaptation module and sends data outage to WTB network card
The ARM chips of Adapter layers of the adapter of adaptation module, notify ARM chips to have new data packets arrival；The processing of ARM chips
After complete interruption, shared drive is accessed in major cycle, and by data read-out.
It is highly preferred that the adapter state machine in the step S104 has following three state：
RECV_ARG_HEAD states, RECV_ARG states and SEND_RESULT states；
RECV_ARG_HEAD states：Adapter state machine is under the state under default situations, and does not stop poll FPGA
Middle host computer whether there is hair packet；No data bag is represented if plooing fault err；If having packet and packet being non-head bag,
Or packet form itself is wrong, then still poll again is returned under the state by err conditions；Only when being polled to correct head bag
When, state machine enters RECV_ARG states by ok conditions, continues to other possible packets；
RECV_ARG states：In this condition, adapter state machine judges whether to finish all data receivers；If
It is current to receive correct and do not receive, then continue to receive other packets in this case；If any one data
Bag reception makes a mistake, then returning to RECV_ARG_HEAD states by err conditions restarts to wait interface next time to adjust
With；Finished if being properly received, use the corresponding link layer interface function of the parameter call received；It is finished and obtains and holds
After row result, enter SEND_RESULT states and return to implementing result；
SEND_RESULT states：In this condition, the implementing result after encapsulation is divided into data by adapter state machine
Bag, and it is sent to host computer adaptation module successively in order；If certain sends mistake or is sent, RECV_ is returned to
ARG_HEAD states restart；Otherwise continue to send in this case.
It is highly preferred that host computer adaptation module is after user calls WTB link layer functionality interface requests to transmit data, when
When the automatic calling interface request of host computer adaptation module receives WTB network card adaptation module implementing result returned data, the realization
Method includes：
Step S201, host computer adaptation module transmitting and receiving data request, is connect by Adapter layers of construction of its adapter
Request of data transmission bag is received, WTB network card adaptation module is sent to by FPGA interface；
Step S202, WTB network card adaptation module is received after the reception request of data of host computer adaptation module, will effectively be tied
Fruit data are encapsulated into packet, are returned to all packets successively by fpga logic layer according to divided stator frame mechanism upper
Machine adaptation module；
Step S203, host computer adaptation module obtains the packet of WTB network card adaptation module return from FPGA layers, and solves
Result data is obtained after analysis, the result data is transferred to the WTB LI(link interface)s layer on upper strata.
It is highly preferred that WTB network card adaptation module sends the process of each packet by fpga logic layer in step S202
Including：
By poll FPGA interface state, whether readable manner checks whether there is data to host computer adaptation module；WTB nets
The ARM chips of the adaptation layer of card adaptation module are ready to after data, are written into the data field ad-hoc location of shared drive, then
Request orders and correspondence parameter value to the ad-hoc location write-in " setting readable " of command area；WTB network card adaptation module
The FPGA chips of fpga logic layer are inquired after order, FPGA interface are set to readable and writable；Host computer adaptation module poll
When know valid data, then write read command word；Host computer adaptation module reads data length afterwards, and is sequential read out by length
Each byte of data；After host computer adaptation module has read all data in the packet, fpga chip is by host computer
The FPGA interface of adaptation module be set to it is unreadable, complete the packet from WTB network card adaptation module to host computer adaptation module
Transmission.
The present invention has the following technical effect that it can be seen from the technical scheme of the invention described above：
1st, because the present invention includes the host computer adaptation module where CPU board card and the adaptation of the WTB network card where WTB boards
Module so that user can directly invoke WTB link layer functionality interface by CPU device where host computer, is realized pair
Far call (RPC) function of WTB link layer interfaces, and it is fully transparent to user program.
2nd, because the present invention at WTB network card adaptation module end runs an adapter state machine, the state machine ensure that
No matter which side makes a mistake, and data transmit-receive will not be absorbed in busy waiting and cause program seemingly-dead, greatly ensure that the present invention
WTB link layer interface adapters availability and stability.
Brief description of the drawings
Fig. 1 is the structure chart of WTB link layer adaptations device of the present invention；
Fig. 2 is that host computer adaptation module asks to send WTB link layers of the invention after data to WTB network card adaptation module
The timing diagram of the implementation method of adapter；
Fig. 3 is that host computer adaptation module asks to send WTB link layers of the invention after data to WTB network card adaptation module
The implementing procedure figure of the implementation method of adapter；
Fig. 4 is the flow chart of the divided stator frame mechanism of adapter communications agreement in the present invention；
Fig. 5 is the format chart of head bag of the present invention；
Fig. 6 is the format chart of non-head bag of the invention；
Fig. 7 is the data-set followed when host computer adaptation module sends each packet to WTB network card adaptation module
Flow chart processed；
Fig. 8 is that host computer adaptation module asks to receive WTB link layers of the invention after data to WTB network card adaptation module
The timing diagram of the implementation method of interface adapter；
Fig. 9 is that host computer adaptation module asks to receive WTB link layers of the invention after data to WTB network card adaptation module
The implementing procedure figure of the implementation method of adapter；
Figure 10 is that host computer adaptation module asks WTB network card of the invention after reception data to be fitted to WTB network card adaptation module
The data transmission mechanism flow chart followed when sending each packet to host computer adaptation module with module.
Embodiment
Technical scheme is described in further details below with reference to accompanying drawing.
Embodiment one
The present invention provides a kind of WTB network card link layer interface adapter, the structure of the WTB network card link layer interface adapter
As shown in Figure 1, it can be seen that：
The WTB network card link layer interface adapter is laterally broadly divided into two parts：Host computer adaptation where CPU board card
WTB network card adaptation module where module and WTB boards.
Wherein WTB network card adaptation module includes three-tier architecture, is respectively：WTB LI(link interface)s layer, Adapter layers of adapter
With fpga logic layer.WTB LI(link interface)s layer provides WTB functional interfaces.The function that Adapter layers of adapter is：It is WTB work(upwards
Energy interface provides related parameter, needs downwards and fpga logic layer interacts to obtain related data；Adapter Adapter
The function of layer is completed by the ARM chips for being responsible for complex logic computing.Fpga logic layer function be：Need upwards and adapter
Adapter layers interact to obtain related data；Downward driving parallel bus is interacted with host computer, buffered data.FPGA
These functions of logical layer control physics and FPGA (the Field-Programmable Gate of mechanical signal by being responsible for
Array, field programmable gate array) chip completes.Parallel bus interface can be passed through between fpga chip and ARM chips
Connection.
Host computer adaptation module includes two-tiered structure：Adapter layers of WTB LI(link interface)s layer and adapter.WTB links connect
Mouth layer provides host computer user's virtual interface；Adapter layers of adapter provides link to the user of WTB LI(link interface)s layer upwards
Layer interface, and then need the relevant interface with fpga chip to carry out data interaction downwards.Host computer adaptation module is fitted with WTB network card
Fpga chip with module is joined directly together by parallel bus, therefore has one piece of FPGA interface logic in fpga chip, and upper
The adapter bottom transmission logic of machine is corresponding.And the program interaction between FPGA and ARM is shared by one piece of fpga chip
Internal memory is realized with interrupting.Meanwhile, the communication logic interaction of FPGA interface logical sum ARM chips, for realizing host computer
The correlation function of the communication protocol of adaptation module and WTB network card adaptation module.
Physical signalling and data are carried out by fpga logic layer between host computer adaptation module and WTB network card adaptation module
Transmission.Therebetween an adapter communications agreement is used in conjunction with, the communication protocol of the adapter is divided into three levels, is respectively
Data are encapsulated and analytic sheaf, data subpackage and packet receiving layer, packet (byte stream) send and receive layer.In order to realize RPC functions,
The adapter communications agreement needs the interface index of calling interface, RPC relevant parameters etc. being packaged, and correct in the other end
Parse.After interface interchange, in addition it is also necessary to which call result is packaged, and it is transferred to called side parsing.
Embodiment two
The present invention is also provided in a kind of implementation method of above-mentioned WTB link layer interfaces adapter, the implementation method, Yong Hutong
CPU device where crossing host computer adaptation module calls the process of WTB link layer functionality interactive interfacing data to include two kinds of feelings
Condition：One is the situation of request data transmission, the second is the situation that request data is received.Regardless of whether which kind of situation, host computer is fitted
It is always the masters of communication with module, data transmit-receive work(is completed by sending commands to control fpga chip to fpga chip
Energy.After host computer adaptation module actively initiates communication request, by Adapter layers of processing of adapter, bottom is eventually arrived at
With the stage of the fpga chip transceiving data of WTB network card adaptation module.When host computer adaptation module actively initiates communication request, on
Position machine adaptation module can produce two stages, i.e. transmission phase by an interface interchange and receive the stage.In transmission phase, on
Adapter layers of the adapter of position machine adaptation module is responsible for that call parameters etc. are packaged, and is divided into several packets, and
It is sent to WTB network card adaptation module successively；In the stage of reception, Adapter layers of the adapter of host computer is responsible for WTB network card
The implementing result that adaptation module is returned is assembled into correct data again, and the data after parsing are returned into WTB LI(link interface)s
Layer.It can be seen that, the implementation method for the WTB link layer interface adapters that the present invention is provided includes the following two kinds processing procedure：In user
WTB link layer functionality interface requests are called to transmit after data, host computer adaptation module asks to transmit to WTB network card adaptation module
The processing procedure of data；And, after user calls WTB link layer functionality interface requests to receive data, host computer adaptation mould
Block asks to receive the processing procedure of the processing procedure of data to WTB network card adaptation module.And host computer in every kind of processing procedure
Transmission phase and reception stage can all occur in adaptation module.
Fig. 2-Figure 10 is combined separately below, and both processing procedures are described in detail：
First, processing procedure from host computer adaptation module to WTB network card adaptation module request data transfer
Host computer adaptation module performs host computer after user calls WTB link layer functionality interface requests to transmit data
Adaptation module sends the process of data to ATM platforms.Host computer send the processes of data by Send stages and Recv stages this two
The individual stage completes, and is respectively completed data and sends and send results verification.Request of data is sent actively to be initiated by host computer, it is upper
Machine adaptation module is initiated to send after request of data, initially enters the transmission Send stages, carries out data encapsulation, subpackage and transmission；When
ATM is returned after implementing result, into the Recv stages.In this case the realization of a kind of WTB link layer interfaces adapter of the invention
The timing diagram of method is as shown in Figure 2：
In the Send stages, the packaged data of host computer adaptation module are divided into after packet, give packet (byte
Stream) send.Packet (byte stream) sends layer and all packets after segmentation is sent in sequence into WTB network card adaptation module.
Before each packet is sent, first have to carry out data encapsulation, then host computer adaptation module transmission bag, is delivered a packet to
WTB network card adaptation module end.
After harvesting bag at WTB network card adaptation module end, WTB network card adaptation module needs the confirmation data with a byte
(such as RST confirmations) notifies whether the upper computer end bag sends success.Such as, when mistake occurs in bag content, confirm that data RST is
0xFF.And after work(reception processing is bundled into, then it is 0x01 to confirm data RST.
In the Recv stages, whether host computer is received after confirmation data, judge that this is given out a contract for a project according to its content and succeed, and will knot
Fruit returns to upper strata.So far a packet is sent, and can carry out the operation such as other packet transmissions.
In this case specific implementation procedure such as Fig. 3 of the implementation method of a kind of WTB link layer interfaces adapter of the invention
It is shown, comprise the following steps S101 to step S105 process：
Step S101, host computer adaptation module carries out data encapsulation.
Host computer adaptation module is when user calls WTB link layer functionality interface requests to transmit data, host computer adaptation
Module acquisition user calls the interface index and parameter of WTB link layer functionality interface, and the interface index and parameter are entered
Row encapsulation.
In host computer adaptation module one end, when user calls link layer interface, the adapter of host computer adaptation module
Adapter layers need receiving and get the interface index and parameter of the link layer functionality interface for the WTB that user calls, and will
It is encapsulated.When data are encapsulated, the interface index (sequence of function number) of 4 bytes is put into parameter buffer first；Then for
Each interface parameters value, is encapsulated into parameter buffer successively according to its order in interface statement；It is eventually adding 4 bytes
CRC check value, by calling trans_Send () interface to be sent to next layer.
Step S102, data subpackage.
In this step, host computer adaptation module is responsible for the data of packaged data buffer zone being divided into regular length
Packet, so as to which its whole subsequently is sent into WTB network card adaptation module.
Called for some link layer interfaces, its call parameters and return value data length can reach the magnitude of kilobytes.
If the encapsulation of data of the magnitude is disposable easily to there is mistake by hardware transport, and FPGA also be difficult to mark off it is enough
Buffering area carrys out data storage.Interrupted in addition, if being sent in data transmission procedure, then need a kind of divided stator frame mechanism
Restart to ensure that adapter two ends can all return to normal condition, while when ensureing to call other interfaces again after avoidance breakout
The problem of generation data-crosstalk.
The divided stator frame mechanism as shown in figure 4, in Fig. 4, left side for host computer adaptation module data subpackage and packet receiving layer,
Right side is data subpackage and the packet receiving layer of WTB network card adaptation module.By the divided stator frame mechanism, the data after upper strata is encapsulated
It is divided into the packet of regular length then to send successively again.
During data subpackage, packet is divided into two kinds of forms of head bag and non-head bag, first data by host computer adaptation module
Bao Weitou bag forms, and other packets then meet the form of non-head bag.Then call gp_command_p () interface will be every
One packet is sent to next level and is transmitted.
Head bag form is as shown in figure 5, non-head bag form is as shown in Figure 6.Head bag and non-head wrap the length of both packets
Most long is 122 bytes.For head bag and non-head bag, its first character section is divided into the head bag mark, secondary of three parts, i.e. highest order
The sequence number SN field of high-order callback mark and remaining six compositions.
It is head bag that head bag, which is masked as the 1 expression packet, is the non-head bag of 0 expression.
If callback mark 1 represents that WTB link layers there occurs some events, it is necessary to notify upper computer end to be adjusted back.
Sequence number SN field then represents the sequence number of the packet, during an adaptor interface is called, and sends
Parameter is consistent with the SN for the packet for receiving result.Once generation is inconsistent, then adapter has understood last transmission
Interrupt, new SN interface interchange should be started, occur data-crosstalk this avoid interruption is called.Perform and once called
Afterwards, SN can add 1, begin preparing for calling next time.When reaching maximum 63, SN returns to 0 value and is continuing with.
One special field of head bag is 4 byte representation total length of data after first byte, and the length is exactly this
The interface interchange total length of data to be transmitted, and to hold form to store greatly.Rather than head Bao Zewu this field, directly in lead-in
Interpolation data part after section.Therefore, the data division of head bag up to 117 bytes, rather than head bag data part up to 121 words
Section.If desired the total data length sent is no more than 117 bytes, then a head bag can be sent.Otherwise sent in head bag
After complete, some non-head bags are sent according to remaining data length.
Step S103, packet (byte stream) is sent.
Packet (byte stream), which sends layer, to be responsible for all packets after segmentation being sent in sequence to WTB network interface cards adaptation mould
Block, the packaged data of host computer adaptation module are divided into after several packets, give packet (byte stream) to send layer
To send.Packet (byte stream) sends layer and all packets after segmentation is sent in sequence into WTB network card adaptation module.It is upper
Machine delivers a packet to WTB network card adaptation module end by FPGA interface.Host computer adaptation module receives WTB network card adaptation mould
After the confirmation data at block end, judge that this is given out a contract for a project according to its content and whether succeed, and return result to upper strata.So far a number
It is sent according to bag, the operation such as other packet transmissions can be carried out.
For the transmission of each packet, host computer adaptation module follows one when being sent to WTB network card adaptation module
Data transmission mechanism, as shown in fig. 7, the direction of arrow represents data direction in figure.As can be seen that the hair of each packet in Fig. 7
Sending will be by 6 step：
Whether the adapter check of host computer adaptation module can write data to FPGA interface first, if not writeable, instead
Check is ask, until when inquiry times reach certain higher limit, then it is assumed that time-out error occurs, and host computer adapter directly returns to mistake
By mistake；If writeable, send one first and write data command, data length is write afterwards and data are passed sequentially through into FPGA by byte connect
Receive in register write-in FPGA chips.Fpga chip is got after data, is written into the ad-hoc location of shared drive, and
Send a host computer transmission data outage and give ARM chips, notify ARM chips to have new data packets arrival.Now ARM chips
Handle after interruption, accessed shared drive in major cycle, and by data read-out.
Step S104, WTB network card adaptation module packet is received.
Shown on the right side of Fig. 4, WTB network card adaptation module adapter end runs the state machine of a communication protocol, the shape
State machine has three states：That is RECV_ARG_HEAD states, RECV_ARG states and SEND_RESULT states, are realized respectively
The reception and transmission of the packet of WTB network card adaptation module.
The state machine first is received after correct head bag, into RECV_ARG in the RECV_ARG_HEAD states of acquiescence
State；Under RECV_ARG states, other non-head bag datas are received.ARM ends now parse the packet, and obtain packet header
Length and command word information.ARM gives the two fields and bag data at the encapsulation of agreement upper layer data and analytic sheaf afterwards
Reason, the layer first determines whether whether length is legal, then checks whether command word is ' P ', and packet content is parsed, and obtains
Head bag and SN information are taken, judges whether the bag is effective jointly.
Under three states of the state of communication protocols machine run below to WTB network card adaptation module performed task and
Transition condition is illustrated.
RECV_ARG_HEAD states：State machine is under the state under default situations, and does not stop upper in poll FPGA
Machine whether there is hair packet.No data bag is represented if plooing fault err；If there is packet, but packet is non-head bag, or
Packet form itself is wrong, then still returns under the state poll again by err conditions.Therefore only when being polled to correct head bag
When, state machine enters RECV_ARG states by ok conditions, continues to other possible packets.The purpose of the state is mainly
For intercepting the influence that wrong data bag is caused.Guarantee is that a correct adaptor interface is called every time.
RECV_ARG states：In this condition, state machine determines whether to finish all data receivers.If current
Receive correct and do not receive, then continue to receive other data in this case by ok AND NOT fin conditions
Bag.Made a mistake if any one packet is received, returning to RECV_ARG_HEAD states by err conditions restarts
Treat interface interchange next time.Finished if being properly received, use the corresponding link layer interface function of the parameter call received.
It is finished and obtains after implementing result, entering SEND_RESULT states by ok AND fin conditions returns to implementing result.
SEND_RESULT states：In this condition, the implementing result after encapsulation is equally divided into packet by state machine,
And it is sent to upper computer end successively in order.If certain sends mistake or is sent, RECV_ is returned to by err OR fin
ARG_HEAD states restart.Otherwise continue to send in this case by ok AND NOT fin conditions.
Step S105, after WTB network card adaptation module has received all packets, WTB network card adaptation module performs WTB
Link layer interface function.
In state machine RECV_ARG states, after all packets have been received, in the adapter of WTB network card adaptation module
Adapter layers of progress data parsing, check whether crc verifications are correct.Then interface index and parameter are obtained, and calls WTB chains
The function for the real interface that road layer interface is performed.After being finished, enter the wait of SEND_RESULT states and seal implementing result
Dress is sent to host computer adaptation module.
Step S106, host computer adaptation module waits the return of call result, and after returning result is received, will return
As a result export.
Enter the Recv stages that receive, host computer adaptation mould after all packets are sent by host computer adaptation module
The return of the Adapter layers of wait call result of adapter of block, and after returning result is received, host computer adaptation module will be returned
Return result output.
So far, the far call for realizing WTB link layer interface functions is performed.
2nd, host computer adaptation module asks to receive the processing procedure of data to WTB network card adaptation module
Host computer adaptation module is after user calls WTB link layer functionality interface requests to receive data, and host computer is received
The process of one packet is equally completed by Send stages and the two stages in Recv stages, corresponds to receive request of data respectively
And packet recovery stage.Receive request of data same by host computer actively initiation, host computer adaptation module is initiated to receive data
After request, the transmission Send stages are initially entered, data encapsulation, subpackage and transmission is carried out；After ATM returns to implementing result, enter
The Recv stages.In this case a kind of timing diagram of the implementation method of WTB link layer interfaces adapter of the invention is as shown in Figure 8：
Left side is host computer adaptation module, and right side is WTB network card adaptation module.Host computer enters the Send stages, and transmission connects
The process data packet for receiving data request command is similar with the process in the Send stages in previous step S101, is adjusted the difference is that passing through
Packet is sent with gp_command_g () interface.After host computer is into the recv stages, for WTB network card adaptation module
The data of feedback, construct a transmission packet header, it is identical that its form and Send stages above describe, and is equally two words first
Section.First character section is 0, represents no data transmission.Second byte is command character ' g ', represent this data transfer be from
ARM is obtained behind data, packet header without other data.Host computer adaptation module goes out data transfer afterwards.
In this case specific implementation procedure such as Fig. 9 of the implementation method of a kind of WTB link layer interfaces adapter of the invention
It is shown, comprise the following steps S201 to step S203 process：
Step S201, the request of host computer adaptation module transmitting and receiving data.
Host computer is actively initiated to receive request of data, and data request data is received by Adapter layers of construction of its adapter
Bag, and data encapsulation, subpackage are carried out, and it is sent to this process of WTB network card adaptation module and previous step by FPGA interface
The process in the Send stages in S101 is identical, the difference is that by calling gp_command_g () interface to initiate to receive come active
Request of data.
Step S202, WTB network card adaptation module returns to the result data performed.
WTB network card adaptation module is received after the reception request of data of host computer adaptation module, will be effective by FPGA layers
Implementing result returns to host computer adaptation module.The detailed process of this step：WTB network card adaptation module enters the data received
Row parsing, judges whether length is legal, then checks whether command character is ' g ', to judge whether packet is effective.If invalid
Do not reply any data then, effectively then by result data similarly by data encapsulation, subpackage, transmission, be adapted to by WTB network card
SEND_RESULT states are passed implementing result back host computer by FPGA layers and are adapted in state machine in module adapter agreement
Module.
For the transmission of each packet, WTB network card adaptation module is used as shown in Figure 10 to host computer adaptation module
Arrow illustrates the transmission direction of data in data transmission mechanism, figure.
Passed as can be seen that WTB network card adaptation module sends data used in the process of data to host computer adaptation module
In defeated mechanism, because fpga chip can not directly notify host computer to have new data arrival, therefore host computer adaptation module passes through wheel
Asking FPGA interface state, whether readable manner checks whether there is data；ARM chips are ready to after data, are written into shared
The data field ad-hoc location deposited, then writes the Request orders of " setting readable " to the ad-hoc location of command area and correspondence is joined
Numerical value.Fpga chip is inquired after order, FPGA interface is set to readable and writable.Now during host computer adaptation module poll
Know valid data, then write read command word.Host computer adaptation module reads data length afterwards, and sequential reads out number by length
According to each byte.After host computer adaptation module has read all data in the packet, fpga chip fits host computer
FPGA interface with module be set to it is unreadable, so far complete the packet from WTB network card adaptation module to host computer be adapted to mould
The transmission of block.
Step S203, host computer adaptation module receives result data, and the result data is transferred out.
Host computer adaptation module is called can be obtained while gp_command_g () interface from FPGA layers in step s 201
The packet for taking WTB network card adaptation module to return.Head bag is obtained first, the size of whole data is calculated, and is then constantly received
The data of negated head bag.After all packets are received, result parsing is carried out, the crc check codes of 4 bytes are parsed, so
It is the implementing result label of 1 byte afterwards, is the returned data of some bytes afterwards, the result data is transferred to upper strata.
So far, complete the far call of a WTB link layer interface function and return to implementing result.
It can be seen from the technical scheme of the invention described above by transmission phase and in the reception stage each packet place
Reason, you can ensure that packet can be transmitted correctly, and both sides understand the result that a packet is sent, so as to logical
Know that upper strata carries out respective handling.The logic that other host computer adaptation module sends and receives packet is actually unification, i.e.,
It is transmission order and parameter, acquisition two stages of returning result, real which simplify the complexity of fpga logic processing, and conveniently
It is existing.
Although the present invention is disclosed as above with preferred embodiment, embodiment does not limit the present invention.This hair is not being departed from
Any equivalence changes done in bright spirit and scope or retouching, also belong to the protection domain of the present invention.Therefore it is of the invention
The content that should be defined using claims hereof of protection domain as standard.
Claims (10)
1. a kind of WTB link layer interfaces adapter, it is characterised in that the WTB link layer interfaces adapter includes：
Host computer adaptation module and WTB network card adaptation module；
The WTB network card adaptation module includes three-tier architecture, is respectively：WTB LI(link interface)s layer, Adapter layer of adapter and
Fpga logic layer；The WTB LI(link interface)s layer of the WTB network card adaptation module provides WTB functional interfaces；The WTB network card adaptation
Adapter layers of the adapter of module provides the call parameters of correlation for WTB functional interfaces upwards, is carried out with fpga logic layer downwards
Interact to obtain related data；Adapter Adapter layer of the fpga logic layer upwards with the WTB network card adaptation module enters
Go interaction to obtain related data, downward driving parallel bus is interacted with host computer adaptation module, buffered data；
Host computer adaptation module includes two-tiered structure：Adapter layers of WTB LI(link interface)s layer and adapter；The host computer adaptation
The WTB LI(link interface)s layer of module provides host computer user's virtual interface；Adapter layers of the adapter of the host computer adaptation module
Parameter transmitting function is provided to the WTB LI(link interface)s layer user of the host computer adaptation module upwards, downwards then with the WTB nets
The relevant interface of the fpga logic layer of card adaptation module carries out data interaction.
2. a kind of WTB link layer interfaces adapter according to claim 1, it is characterised in that the WTB network card is adapted to mould
The function of Adapter layers of the adapter of block is completed by the ARM chips for being responsible for logical operation.
3. a kind of WTB link layer interfaces adapter according to claim 1, it is characterised in that the WTB network card is adapted to mould
The function of the fpga logic layer of block is completed by the on-site programmable gate array FPGA chip for being responsible for control physics and mechanical signal.
4. a kind of implementation method of WTB link layer interfaces adapter according to claims 1 to 3 any one, its feature
It is, the implementation method includes：
When user is by CPU device interaction data where host computer adaptation module, it is empty that host computer adaptation module passes through user
Intend interface and actively initiate transmission packet and received data packet respectively；And it is suitable with the WTB network card downwards by link layer interface
The relevant interface of fpga logic layer with module carries out data interaction；
Adapter Adapter of the WTB network card adaptation module by fpga logic layer upwards with the WTB network card adaptation module
Layer is interacted to obtain related data, and downward driving parallel bus is interacted with host computer adaptation module, buffered data；It is described
Adapter layers of the adapter of WTB network card adaptation module interacts to obtain related data with fpga logic layer downwards, is upwards
The WTB functional interfaces of WTB LI(link interface)s layer provide related parameter.
5. a kind of implementation method of WTB link layer interfaces adapter according to claim 4, it is characterised in that host computer
Adaptation module is after user calls WTB link layer functionality interface requests to transmit data, when host computer adaptation module is called automatically
When interface requests transmit data to WTB network card adaptation module, the implementation method includes：
Step S101, host computer adaptation module calls WTB link layer functionality interface by user's virtual interface acquisition user
Data, by its adapter, Adapter layers are packaged the data；
Step S102, Adapter layers of the adapter of host computer adaptation module uses divided stator frame mechanism, and packaged data are delayed
The data for rushing area are divided into the packet of regular length；
All packets after segmentation are passed sequentially through FPGA by step S103, Adapter layers of the adapter of host computer adaptation module
Interface is sent to the FPGA layers of WTB network card adaptation module, and is transmitted result according to the feedback result of WTB network card adaptation module
Confirmation；
Step S104, Adapter layers of the adapter of WTB network card adaptation module is adapted to mould based on adapter state machine to WTB network card
Packet in the FPGA layers of block is received；
Step S105, after WTB network card adaptation module has received all packets, the WTB links of WTB network card adaptation module connect
Mouth layer performs WTB link layer interface functions；
Step S106, host computer adaptation module waits the return of call result, and after returning result is received, by returning result
Output.
6. a kind of implementation method of WTB link layer interfaces adapter according to claim 5, it is characterised in that the step
Rapid S103 process includes：
For each packet, Adapter layers of the adapter of host computer adaptation module is sent the packet by FPGA interface
Give WTB network card adaptation module；
Host computer adaptation module is received after the RST confirmation data that WTB network card adaptation module is sent by FPGA interface, and host computer is fitted
Adapter layers of the adapter with module confirms that the content of data judges that this is given out a contract for a project and whether succeeded according to the RST, and result is returned
Back to the WTB LI(link interface)s layer of host computer adaptation module.
7. a kind of implementation method of WTB link layer interfaces adapter according to claim 5, it is characterised in that the step
In rapid S103, host computer adaptation module sends each packet by FPGA interface to be included to the process of WTB network card adaptation module：
The adapter layer of host computer adaptation module, which is checked whether, to write data to FPGA interface, if not writeable, inquired about repeatedly,
Until when inquiry times reach certain higher limit, then it is assumed that time-out error occurs, host computer adaptor module directly returns to mistake；
If writeable, send one first and write data command, data length is write afterwards and data are passed sequentially through into FPGA receptions by byte
Register write-in is in the fpga chip of the fpga logic layer of WTB network card adaptation module；Fpga chip is got after data, will
It is write in the ad-hoc location of shared drive, and is sent host computer adaptation module and sent data outage and give WTB network card adaptation
The ARM chips of Adapter layers of the adapter of module, notify ARM chips to have new data packets arrival；During ARM chips have been handled
Have no progeny, access shared drive in major cycle, and by data read-out.
8. a kind of implementation method of WTB link layer interfaces adapter according to claim 5, it is characterised in that the step
Adapter state machine in rapid S104 has following three state：
RECV_ARG_HEAD states, RECV_ARG states and SEND_RESULT states；
RECV_ARG_HEAD states：Adapter state machine is under the state under default situations, and is not stopped in poll FPGA
Position machine whether there is hair packet；No data bag is represented if plooing fault err；If there is packet and packet is non-head bag, or
Packet form itself is wrong, then still returns under the state poll again by err conditions；Only when being polled to correct head bag,
State machine enters RECV_ARG states by ok conditions, continues to other possible packets；
RECV_ARG states：In this condition, adapter state machine judges whether to finish all data receivers；If current
Receive correct and do not receive, then continue to receive other packets in this case；If any one time packet connects
Receipts make a mistake, then returning to RECV_ARG_HEAD states by err conditions restarts to wait interface interchange next time；If
It is properly received and finishes, then using the corresponding link layer interface function of the parameter call received；It is finished and obtains and performs knot
After fruit, enter SEND_RESULT states and return to implementing result；
SEND_RESULT states：In this condition, the implementing result after encapsulation is divided into packet by adapter state machine, and
It is sent to host computer adaptation module successively in order；If certain sends mistake or is sent, RECV_ARG_HEAD is returned to
State restarts；Otherwise continue to send in this case.
9. a kind of implementation method of WTB link layer interfaces adapter according to claim 4, it is characterised in that host computer
Adaptation module is after user calls WTB link layer functionality interface requests to transmit data, when host computer adaptation module is called automatically
When interface requests receive WTB network card adaptation module implementing result returned data, the implementation method includes：
Step S201, host computer adaptation module transmitting and receiving data request receives data by Adapter layers of construction of its adapter
Request transmission bag, WTB network card adaptation module is sent to by FPGA interface；
Step S202, WTB network card adaptation module is received after the reception request of data of host computer adaptation module, by effective number of results
According to being encapsulated into packet, all packets are returned to by host computer by fpga logic layer successively according to divided stator frame mechanism and fitted
With module；
Step S203, host computer adaptation module is obtained from FPGA layers after the packet of WTB network card adaptation module return, and parsing
Result data is obtained, the result data is transferred to the WTB LI(link interface)s layer on upper strata.
10. a kind of implementation method of WTB link layer interfaces adapter according to claim 9, it is characterised in that step
The process that WTB network card adaptation module sends each packet by fpga logic layer in S202 includes：
By poll FPGA interface state, whether readable manner checks whether there is data to host computer adaptation module；WTB network card is fitted
The ARM chips of adaptation layer with module are ready to after data, the data field ad-hoc location of shared drive are written into, then to life
The ad-hoc location in area is made to write Request orders and the correspondence parameter value of " setting readable "；The FPGA of WTB network card adaptation module is patrolled
The fpga chip for collecting layer is inquired after order, FPGA interface is set to readable and writable；Know during host computer adaptation module poll
Valid data, then write read command word；Host computer adaptation module reads data length afterwards, and sequential reads out data by length
Each byte；After host computer adaptation module has read all data in the packet, host computer is adapted to mould by fpga chip
The FPGA interface of block be set to it is unreadable, complete the packet from WTB network card adaptation module to the transmission of host computer adaptation module.
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