CN106653719B - Wafer level packaging structure and packaging method - Google Patents
Wafer level packaging structure and packaging method Download PDFInfo
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- CN106653719B CN106653719B CN201611264360.8A CN201611264360A CN106653719B CN 106653719 B CN106653719 B CN 106653719B CN 201611264360 A CN201611264360 A CN 201611264360A CN 106653719 B CN106653719 B CN 106653719B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H01L2224/13006—Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
Abstract
The invention discloses a wafer level packaging structure which comprises a wafer body, at least one metal terminal arranged on the front surface of the wafer body, a passivation layer arranged on the front surface of the wafer body along the periphery of the metal terminal, a mask layer arranged on the metal terminal and the passivation layer, a metal layer arranged on the mask layer and interconnected with the metal terminal, and a bump arranged on the metal layer and interconnected with the metal terminal through the metal layer, wherein a plurality of meshes are arranged on the part, located on the surface of the metal terminal, of the mask layer, and the metal layer penetrates and is completely filled in the meshes so as to be interconnected with the metal terminal. Through the mode, the mask layer of the wafer level packaging structure is provided with the meshes, the metal layer can be interconnected with the metal terminal after penetrating through the meshes, the process flow is saved, and the mask layer can improve the interlayer bonding force between the metal layer and the metal terminal, so that the structure is firmer.
Description
Technical Field
The present invention relates to the field of semiconductor packaging, and more particularly, to wafer level packaging structures and methods.
Background
In recent years, as the micro-circuit fabrication of chips is advanced toward high integration, the chip package is also advanced toward high power, high density, light weight and miniaturization. The chip packaging is that after the chip is manufactured, the chip is packaged in plastic or ceramic materials to protect the chip from external water vapor and mechanical damage. The main functions of the chip package include Power Distribution (Power Distribution), Signal Distribution (Signal Distribution), Heat Dissipation (Heat Distribution), and Protection and Support (Protection and Support).
Since the requirements of electronic products are light, thin, short, and high integration, the integrated circuit is miniaturized, the number of logic circuits included in the Chip is increased, and the number of I/O (input/output) pins of the Chip is further increased, and many different packaging methods are generated to meet the requirements, such as Ball Grid Array (BGA), Chip Scale Package (CSP), Multi-Chip module Package (MCM Package), Flip Chip Package (Flip Chip Package), Tape Carrier Package (TCP), and Wafer Level Package (WLP).
Regardless of the type of packaging method, most packaging methods are processes in which a wafer is separated into individual chips and then packaged. The wafer level package is a trend in semiconductor packaging methods, and the wafer level package uses a whole wafer as a packaging object, so that the packaging and the testing are completed before the wafer is not cut, and the wafer level package is a highly integrated packaging technology, so that the manufacturing processes of glue filling, assembling, die bonding, wire bonding and the like can be saved, the labor cost can be greatly reduced, and the manufacturing time can be shortened. However, the conventional wafer level package has the problems of complex structure and low bonding force between the metal layer and the metal terminal.
Disclosure of Invention
The invention mainly solves the technical problems of reducing the complexity of a wafer level packaging structure and improving the binding force between a metal layer and a metal terminal.
In order to solve the technical problems, the invention adopts the technical scheme that a wafer level packaging structure is provided, and the wafer level packaging structure comprises a wafer body, at least one metal terminal arranged on the front surface of the wafer body, a passivation layer laid on the front surface of the wafer body along the periphery of the metal terminal, a mask layer laid on the metal terminal and the passivation layer, a metal layer arranged on the mask layer and interconnected with the metal terminal, and a bump arranged on the metal layer and interconnected with the metal terminal through the metal layer, wherein a part of the mask layer positioned on the surface of the metal terminal is provided with a plurality of meshes, and the metal layer penetrates and is completely filled in the meshes so as to be interconnected with the metal terminal.
The mask layer is made of photosensitive materials, and the thickness of the mask layer is 3-5 microns.
Wherein the thickness of the metal layer is 7-10 microns.
Wherein, the mesh is a round hole with the diameter of 5-15 microns.
Wherein the meshes are polygonal holes.
The wafer body is characterized by further comprising a protective layer arranged on the back face of the wafer body, and the protective layer is made of metal materials or gum resin.
The invention also provides a manufacturing method of the wafer level packaging structure, which is characterized by comprising the following steps:
providing a wafer: the wafer comprises a wafer body, a passivation layer arranged on the surface of the wafer body and a plurality of metal terminals distributed on the front surface of the wafer body, wherein the passivation layer is partially exposed on the surface of each metal terminal;
laying a mask layer: forming a mask layer on the front surface of the wafer, wherein the mask layer is firmly combined with the passivation layer and covers the surface of the metal terminal;
photoetching and developing: carrying out photoetching development on the wafer to form a plurality of meshes on the surface of the metal terminal;
laying a metal layer: forming a metal layer on the surface of the metal terminal with a plurality of meshes, wherein the metal layer penetrates into the meshes and is interconnected with the metal terminal;
manufacturing a bump: forming a bump on the surface of the metal layer, wherein the bump is interconnected with the metal terminal through the metal layer;
laying a protective layer: and forming a protective layer on the back surface of the wafer.
The mask layer is made of photosensitive materials, the thickness of the mask layer is 3-5 microns, and the protective layer is made of metal materials or gum resin.
The manufacturing process of the metal layer is a seed layer sputtering process and an electroplating process or the manufacturing process of the metal layer is an evaporation process, and the thickness of the metal layer is 7-10 micrometers.
Wherein the meshes are round holes or polygonal holes.
The invention has the beneficial effects that: different from the situation of the prior art, the mask layer of the wafer level packaging structure has meshes, the metal layer can be interconnected with the metal terminal after penetrating through the meshes, the process flow is saved, and the mask layer can improve the interlayer bonding force between the metal layer and the metal terminal, so that the structure is firmer.
Drawings
FIG. 1 is a process flow diagram of a wafer level packaging method of the present invention;
fig. 2 to 8 are schematic structural views corresponding to the manufacturing steps of the packaging method of fig. 1;
fig. 9 to 14 are schematic structural views corresponding to respective manufacturing steps in another embodiment of the packaging method of fig. 1;
Detailed Description
Fig. 1 is a flowchart of a wafer level packaging method of the present invention, fig. 2 to 8 are schematic structural diagrams corresponding to respective steps, and specific steps of the packaging method of the present invention will be specifically described below with reference to fig. 1 to 8:
s1: providing a wafer, as shown in fig. 2, wherein the wafer 100 includes a wafer body 110, a passivation layer 120 disposed on a front surface of the wafer body 110, and a plurality of metal terminals 130, and a surface portion of the metal terminals exposes the passivation layer;
s2: laying a mask layer, as shown in fig. 3, coating a layer of photosensitive material on the passivation layer 120 of the wafer 100 to form a mask layer 140, wherein the mask layer 140 covers the surface of the metal terminal 130, the mask layer 140 can be in large-area contact with the passivation layer 130 and firmly combined to form a stable interface, and the thickness of the mask layer 140 is 3-5 micrometers;
s3: performing photolithography development, referring to fig. 4, placing the wafer 100 with the mask layer 140 in a photolithography machine, performing photolithography development on the wafer 100, and forming a plurality of meshes 150 on the surface of the metal terminal 130; as shown in FIG. 5, in the present embodiment, the mesh holes 150 are circular holes having a diameter of 5 to 15 μm, and in other embodiments, the mesh holes 150 may be other polygonal holes such as rectangular holes and rhombic holes.
S4: laying a metal layer, referring to fig. 6, forming a metal layer 160 on the surface of the metal terminal 130 having the plurality of meshes 150 by using a seed layer sputtering process and an electroplating process, wherein the metal layer 160 penetrates into the meshes 150 and is interconnected with the metal terminal 130, and the thickness of the metal layer 130 is about 7-10 μm; in other embodiments, the manufacturing process of the metal layer 130 may be other processes such as evaporation;
s5: making a bump, referring to fig. 7, forming a bump 170 on the surface of the metal layer 160 by ball-planting, solder printing or electroplating, wherein the bump 170 is interconnected with the metal terminal 130 through the metal layer 160; the bump 170 is used for connecting with electronic elements such as a PCB (printed circuit board) and the like;
s6: and laying a protective layer, and forming a protective layer 180 on the back surface of the wafer 100, wherein the protective layer 100 can be used for back surface metallization of the MOSFET, or can be back adhesive resin formed by printing or film pasting.
Referring to fig. 9, the metal terminal on the wafer is separated by the passivation layer 140 in addition to the metal terminal 130 shown in fig. 1, and two unit terminals 230 of the bottom circuit related to each other and having the same function are formed, and the surface of the separated metal terminal 200 can also be packaged by the wafer level packaging method, which is different from the foregoing method in that the two unit metal terminals 230 related to each other are regarded as the same metal terminal for packaging, rather than the single unit metal terminal, and referring to fig. 10 to 14, the packaging steps of another embodiment of the packaging method of the present invention are as follows:
s1: providing a wafer, wherein the wafer 100 comprises a wafer body 110, a passivation layer 120 arranged on the front surface of the wafer body 110, and a plurality of metal terminals 200, the metal terminals 200 comprise two first single bodies 230 and two second single bodies 232 which are separated from each other, the first single bodies 230 and the second single bodies 232 are separated by the passivation layer 120, and the passivation layer 120 is partially exposed on the surfaces of the first single bodies 230 and the second single bodies 232;
s2: laying a mask layer, coating a layer of photosensitive material on the surface of the passivation layer 120 to form a mask layer 140, and covering the mask layer 140 on the surfaces of the first monomer 230 and the second monomer 232, wherein the mask layer 140 can be in large-area contact with the passivation layer 120 and is firmly combined to form a stable interface, and the thickness of the mask layer 140 is 3-5 micrometers;
s3: photoetching and developing, namely placing the wafer 100 with the mask layer 140 in a photoetching machine, and photoetching and developing the wafer 100 to form a plurality of meshes 150 on the surfaces of the first monomer 230 and the second monomer 232; in the present embodiment, the mesh holes 150 are circular holes with a diameter of 5 to 15 micrometers, and in other embodiments, the mesh holes 150 may also be other polygonal holes such as rectangular holes, rhombic holes, and the like.
S4: laying a metal layer, forming a metal layer 160 on the surfaces of the first monomer 230 and the second monomer 232 with a plurality of meshes by adopting a seed layer sputtering process and an electroplating process, wherein the metal layer 160 penetrates into the meshes of the first monomer 230 and the second monomer 232 and is interconnected with the first monomer 230 and the second monomer 232, and the thickness of the metal layer 160 is about 7-10 microns; in other embodiments, the manufacturing process of the metal layer 160 may be other processes such as vapor deposition;
s5: making a bump, forming a bump 170 on the surface of the metal layer 160 by ball-planting, solder printing or electroplating, wherein the bump 170 is interconnected with the first unit 230 and the second unit 232 through the metal layer 160; the bump 170 is used for connecting with electronic elements such as a PCB (printed circuit board) and the like;
s6: a protective layer 180 is formed on the back surface of the wafer 100 by applying a protective layer, and the protective layer 180 may be used for back surface metallization of the MOSFET or may be a back adhesive resin formed by printing or film bonding.
The invention also provides a wafer level packaging structure manufactured by the packaging method, which comprises a wafer body 100, at least one metal terminal 130 arranged on the front surface of the wafer body, a passivation layer 120 laid on the front surface of the wafer body along the periphery of the metal terminal, a mask layer 140 laid on the metal terminal 130 and the passivation layer 120, a metal layer 160 arranged on the mask layer 140 and interconnected with the metal terminal, and a bump 170 arranged on the metal layer 160 and interconnected with the metal terminal through the metal layer, wherein a part of the mask layer 140 on the surface of the metal terminal 130 is provided with a plurality of meshes 150, and the metal layer 160 penetrates and is completely filled in the meshes 150 to be interconnected with the metal terminal 130.
Different from the situation of the prior art, the mask layer of the wafer level packaging structure provided by the invention is provided with meshes, the metal layer can be interconnected with the metal terminal after penetrating through the meshes, the process flow is saved, and the mask layer can improve the interlayer bonding force between the metal layer and the metal terminal, so that the structure is firmer.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A wafer level packaging structure is characterized by comprising a wafer body, at least one metal terminal, a passivation layer, a mask layer, a metal layer and a protruding block, wherein the metal terminal is arranged on the front face of the wafer body and directly electrically connected with the wafer body, the passivation layer is arranged on the front face of the wafer body along the periphery of the metal terminal, the mask layer is arranged on the metal terminal and the passivation layer, the metal layer is arranged on the mask layer and interconnected with the metal terminal, the protruding block is arranged on the metal layer and is interconnected with the metal terminal through the metal layer, the metal terminal comprises a first monomer and a second monomer which are separated by the passivation layer, the passivation layer is partially exposed out of the surface of the first monomer and the surface of the second monomer, a plurality of meshes are arranged on the surface of the first monomer and the surface of the second monomer, and the metal layer penetrates and is completely filled in the meshes and then is interconnected with the first monomer and the second monomer, and the meshes comprise meshes with narrow lower parts and wide upper parts so as to improve the interlayer bonding force between the metal layer and the metal terminal.
2. The wafer level package structure of claim 1, wherein the mask layer is made of a photosensitive material, and the thickness of the mask layer is 3-5 μm.
3. The wafer level package structure of claim 1, wherein the metal layer has a thickness of 7-10 μm.
4. The wafer level package structure of claim 1, wherein the mesh holes are circular holes with a diameter of 5-15 μm.
5. The wafer level package structure of claim 1, wherein the mesh openings are polygonal holes.
6. The wafer level package structure of claim 1, further comprising a protection layer disposed on the backside of the wafer body, wherein the protection layer is made of metal or resin.
7. A manufacturing method of a wafer level packaging structure is characterized by comprising the following steps:
providing a wafer: the wafer comprises a wafer body, a passivation layer arranged on the surface of the wafer body and a plurality of metal terminals which are distributed on the front surface of the wafer body and are directly electrically connected with the wafer body, wherein the metal terminals comprise a first monomer and a second monomer which are separated by the passivation layer, and the passivation layer is partially exposed on the surfaces of the first monomer and the second monomer;
laying a mask layer: forming a mask layer on the front surface of the wafer, wherein the mask layer is firmly combined with the passivation layer and covers the surfaces of the first monomer and the second monomer;
photoetching and developing: photoetching and developing the wafer to form a plurality of meshes on the surfaces of the second monomer and the second monomer;
laying a metal layer: forming metal layers on the surfaces of the first monomer and the second monomer with a plurality of meshes, wherein the metal layers penetrate into the meshes and are interconnected with the first monomer and the second monomer, and the meshes comprise meshes with narrow lower parts and wide upper parts so as to improve the interlayer bonding force between the metal layers and the metal terminals;
manufacturing a bump: forming a bump on the surface of the metal layer, wherein the bump is interconnected with the metal terminal through the metal layer;
laying a protective layer: and forming a protective layer on the back surface of the wafer.
8. The method for manufacturing a wafer level package structure according to claim 7, wherein the mask layer is made of a photosensitive material, the thickness of the mask layer is 3-5 μm, and the protection layer is made of a metal material or a back adhesive resin.
9. The method for manufacturing the wafer level package structure of claim 7, wherein the metal layer manufacturing process is a seed layer sputtering process and an electroplating process or an evaporation process, and the thickness of the metal layer is 7-10 μm.
10. The method as claimed in claim 7, wherein the mesh holes are circular holes or polygonal holes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611264360.8A CN106653719B (en) | 2016-12-30 | 2016-12-30 | Wafer level packaging structure and packaging method |
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| CN201611264360.8A CN106653719B (en) | 2016-12-30 | 2016-12-30 | Wafer level packaging structure and packaging method |
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| CN106653719A CN106653719A (en) | 2017-05-10 |
| CN106653719B true CN106653719B (en) | 2020-01-17 |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1635634A (en) * | 2003-12-30 | 2005-07-06 | 中芯国际集成电路制造(上海)有限公司 | Method and apparatus for producing welding pad for chip level packaging |
| CN101728347A (en) * | 2008-10-22 | 2010-06-09 | 中芯国际集成电路制造(上海)有限公司 | Package structure and manufacture method thereof |
| CN102222629A (en) * | 2010-04-16 | 2011-10-19 | 台湾积体电路制造股份有限公司 | Semiconductor device and manufacturing method thereof |
| CN103474402A (en) * | 2013-09-29 | 2013-12-25 | 南通富士通微电子股份有限公司 | Semiconductor package structure |
| CN103489803A (en) * | 2013-09-29 | 2014-01-01 | 南通富士通微电子股份有限公司 | Method for forming semiconductor packaging structure |
| CN103779246A (en) * | 2014-02-21 | 2014-05-07 | 江阴长电先进封装有限公司 | High-reliability copper cylinder bump packaging method and packaging structure |
| CN103871908A (en) * | 2014-03-28 | 2014-06-18 | 江阴长电先进封装有限公司 | Method for encapsulating copper pillar bump |
| CN103928417A (en) * | 2014-04-18 | 2014-07-16 | 江阴长电先进封装有限公司 | Low-cost wafer-level CSP method and structure |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7364998B2 (en) * | 2005-07-21 | 2008-04-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming high reliability bump structure |
| US7667335B2 (en) * | 2007-09-20 | 2010-02-23 | Stats Chippac, Ltd. | Semiconductor package with passivation island for reducing stress on solder bumps |
| EP2449582A4 (en) * | 2009-07-02 | 2013-06-12 | Flipchip Internat L L C | Methods and structures for a vertical pillar interconnect |
| CN102446780A (en) * | 2011-12-19 | 2012-05-09 | 南通富士通微电子股份有限公司 | Wafer-level packaging method |
| CN202616228U (en) * | 2012-06-21 | 2012-12-19 | 欣兴电子股份有限公司 | Packaging substrate |
-
2016
- 2016-12-30 CN CN201611264360.8A patent/CN106653719B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1635634A (en) * | 2003-12-30 | 2005-07-06 | 中芯国际集成电路制造(上海)有限公司 | Method and apparatus for producing welding pad for chip level packaging |
| CN101728347A (en) * | 2008-10-22 | 2010-06-09 | 中芯国际集成电路制造(上海)有限公司 | Package structure and manufacture method thereof |
| CN102222629A (en) * | 2010-04-16 | 2011-10-19 | 台湾积体电路制造股份有限公司 | Semiconductor device and manufacturing method thereof |
| CN103474402A (en) * | 2013-09-29 | 2013-12-25 | 南通富士通微电子股份有限公司 | Semiconductor package structure |
| CN103489803A (en) * | 2013-09-29 | 2014-01-01 | 南通富士通微电子股份有限公司 | Method for forming semiconductor packaging structure |
| CN103779246A (en) * | 2014-02-21 | 2014-05-07 | 江阴长电先进封装有限公司 | High-reliability copper cylinder bump packaging method and packaging structure |
| CN103871908A (en) * | 2014-03-28 | 2014-06-18 | 江阴长电先进封装有限公司 | Method for encapsulating copper pillar bump |
| CN103928417A (en) * | 2014-04-18 | 2014-07-16 | 江阴长电先进封装有限公司 | Low-cost wafer-level CSP method and structure |
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