CN103474402A - Semiconductor package structure - Google Patents
Semiconductor package structure Download PDFInfo
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- CN103474402A CN103474402A CN2013104547751A CN201310454775A CN103474402A CN 103474402 A CN103474402 A CN 103474402A CN 2013104547751 A CN2013104547751 A CN 2013104547751A CN 201310454775 A CN201310454775 A CN 201310454775A CN 103474402 A CN103474402 A CN 103474402A
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- layer
- opening
- lower metal
- protruding lower
- polymer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05558—Shape in side view conformal layer on a patterned surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13082—Two-layer arrangements
Abstract
A semiconductor package structure comprises a semiconductor substrate, a welding pad layer, a polymer layer and a convex metal layer. The semiconductor substrate and the welding pad layer are covered by the polymer layer, an opening where the surface of one part of the welding pad layer is exposed is formed in the polymer layer, a plurality of separated polymer columns are arranged on the surface of the welding pad layer in the opening, and the convex lower metal layer is arranged on the surface of one part of the polymer layer outside the welding pad layer, the polymer columns and the opening. The semiconductor package structure is higher in reliability.
Description
Technical field
The present invention relates to field of semiconductor fabrication, particularly a kind of semiconductor package.
Background technology
In today of information-based high speed development, the market prospects of integrated circuit are more and more wide, corresponding, integrated circuit (IC) design, chip manufacturing and all fast developments of integrated antenna package industry.In China, integrated antenna package had become the Important Economic growth point of IC industry already.For many-sided demands such as the high speed processing that meets integrated circuit package, multifunction, integrated, miniaturization and low priceization, the integrated antenna package technology also need be towards slightization, densification development.Integrated antenna package technology commonly used comprises spherical grid array type encapsulation (Ball Grid Array, BGA), chip scale encapsulation (Chip-Scale Package, CSP) and multi-chip module (Multi-Chip Module, MCM) at present.In the encapsulation technology of integrated circuit, integrated antenna package density refers to how many degree of the quantity in the contained front line of unit are (Pin), for highdensity integrated antenna package, the length that shortens distribution contributes to improve the transmission speed of signal, so the application of projection (Bump) has become the main flow of high-density packages.
With reference to figure 1, the cross-sectional view that Fig. 1 is the prior art convex block package structure.Described convex block package structure comprises: semiconductor base 101 is formed with soldering pad layer 102 on described semiconductor base 101; Cover the passivation layer 103 on described semiconductor base 101 and part of solder pads layer 102 surface, described passivation layer 103 has first opening on expose portion soldering pad layer 102 surfaces; Be positioned at the soldering pad layer 102 of the first opening and the protruding lower metal layer 105 on part passivation layer 103 surfaces outside the first opening; Be positioned at the projection 104 on protruding lower metal layer 105.
But the reliability of existing convex block package structure still remains to be improved.
Summary of the invention
The problem that the present invention solves is to improve the reliability of semiconductor package.
For addressing the above problem, the invention provides a kind of semiconductor package, comprising: semiconductor base is positioned at the soldering pad layer on semiconductor base; Cover the polymeric layer of described semiconductor base and soldering pad layer, there is the opening on expose portion soldering pad layer surface in described polymeric layer, on the soldering pad layer surface in opening, there are some discrete polymer columns; Be positioned at the outer lip-deep protruding lower metal layer of partial polymer layer of described soldering pad layer, polymer column and opening.
Optionally, the material of described polymer column is identical with the material of polymeric layer.
Optionally, the material of described polymeric layer is the photosensitive organic thing.
Optionally, described photosensitive organic thing is photosensitive epoxy resin, polyimides, phenyl ring butylene, polybenzoxazoles.
Optionally, the quantity of described polymer column is more than or equal to 1.
Optionally, the size of polymer column is less than the size of opening.
Optionally, the thickness of described protruding lower metal layer is less than the height of the polymer column on soldering pad layer surface.
Optionally, described protruding lower metal layer is the single or multiple lift stacked structure.
Optionally, also comprise: be positioned at the projection on the protruding lower metal layer on opening.
Optionally, also comprise: be positioned at the metal column on the protruding lower metal layer on opening.
Compared with prior art, technical scheme of the present invention has the following advantages:
Described semiconductor package comprises the polymeric layer that covers described semiconductor base and part of solder pads layer, has the opening that exposes described soldering pad layer surface in described polymeric layer, on the soldering pad layer surface in opening, has some discrete polymer columns; Be positioned at the outer lip-deep protruding lower metal layer of partial polymer layer of described soldering pad layer, polymer column and opening.The existence of polymer column, make the surface area of the protruding lower metal layer in opening increase, while on the protruding lower metal layer in opening, forming projection or metal column, make the contact area of projection or metal column and protruding lower metal layer increase, thereby strengthened the adhesiveness of projection or metal column and protruding lower metal layer, when being subject to external pressure or internal stress, prevent that projection or metal column from coming off from protruding lower metal layer surface or preventing from producing rift defect at both contact interfaces when projection or metal column.
Further, described polymeric layer is identical with the material of polymer column, and the material of described polymeric layer is the photosensitive organic thing, therefore after forming polymeric layer, can form the polymer column that opening is positioned at opening in polymeric layer by exposure and developing process, save processing step.
Further, the thickness of described protruding lower metal layer is less than the height of the polymer column on soldering pad layer surface, so that the surface of the protruding lower metal layer formed, along with the surface height fluctuating of polymer column, has increased the surface area of the protruding lower metal layer formed.
The accompanying drawing explanation
The cross-sectional view that Fig. 1 is the prior art convex block package structure;
The cross-sectional view that Fig. 2～Fig. 7 is semiconductor package forming process of the present invention.
Embodiment
After deliberation, the projection of existing encapsulating structure is to be positioned at protruding lower metal layer Surface Contact, when being subject to the stress of outside pressure or inside, described projection easily comes off from protruding lower metal layer surface or produces rift defect at the contact interface of projection and protruding lower metal layer, has affected the encapsulating structure reliability.
The invention provides a kind of semiconductor package and forming method thereof, described semiconductor package comprises the polymeric layer that covers described semiconductor base and part of solder pads layer, there is the opening that exposes described soldering pad layer surface in described polymeric layer, on the soldering pad layer surface in opening, there are some discrete polymer columns; Be positioned at the outer lip-deep protruding lower metal layer of partial polymer layer of described soldering pad layer, polymer column and opening.The existence of polymer column, make the surface area of the protruding lower metal layer in opening increase, while on the protruding lower metal layer in opening, forming projection or metal column, make the contact area of projection or metal column and protruding lower metal layer increase, thereby strengthened the adhesiveness of projection or metal column and protruding lower metal layer.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.When the embodiment of the present invention is described in detail in detail, for ease of explanation, schematic diagram can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of the invention at this.The three-dimensional space that in actual fabrication, should comprise in addition, length, width and the degree of depth.
The cross-sectional view that Fig. 2～Fig. 7 is semiconductor package forming process of the present invention.
At first, please refer to Fig. 2, semiconductor base 201 is provided, on described semiconductor base 201, be formed with soldering pad layer 202.
Be formed with some inside chip (not shown)s in described semiconductor base 201, described soldering pad layer 202 is connected with the inside chip in semiconductor base 201, described soldering pad layer 202 interface be connected with external chip as inside chip.
Described semiconductor base 201 is the single or multiple lift stacked structure, when semiconductor base 201 is the multiple-level stack structure, comprises Semiconductor substrate and is positioned at least one deck dielectric layer on Semiconductor substrate.Described semiconductor substrate materials can be silicon (Si), germanium (Ge) or SiGe (GeSi), carborundum (SiC); Can be also silicon-on-insulator (SOI), germanium on insulator (GOI); Perhaps can also be for other material, such as the III such as GaAs-V compounds of group.
The material of described soldering pad layer 202 can be one or more the combination in aluminium, copper, silver, gold, nickel, tungsten.Described soldering pad layer 202 is for connecting inside chip and the outer enclosure parts in semiconductor base.
It should be noted that, the formation technique of soldering pad layer 202 and inside chip please refer to prior art, and the present invention does not limit this.
Then, with reference to figure 3, form the polymeric layer 203 that covers described semiconductor base 201 and soldering pad layer 202, there is the opening 204 on expose portion soldering pad layer 202 surfaces in described polymeric layer 203, on soldering pad layer 202 surfaces in opening 204, be formed with some discrete polymer columns 205.
Before forming polymeric layer 203, can also form the passivation layer (not shown) on semiconductor base 201 and part of solder pads layer 202, described passivation layer is for the protection of the device formed in semiconductor base.Described passivation layer material can be one or more in silicon nitride, silicon oxynitride, silica, Pyrex, phosphorosilicate glass or boron-phosphorosilicate glass.Because passivation layer hardness is large, and material is more crisp, easily damaged, and easily produce larger stress, therefore after forming passivation layer, need to form polymeric layer 203 on passivation layer, the quality of polymeric layer 203 is relatively soft, can effectively cushion the stress that passivation layer produces, and polymeric layer 203 materials has preferably adhesiveness good between heat-resistant stability, high insulation resistance, low stress, low-hygroscopicity and metal base etc. with respect to passivation material.
Described polymeric layer 203 is identical with the material of polymer column 205, the material of polymeric layer described in the present embodiment 203 is the photosensitive organic thing, therefore after forming polymeric layer, can form opening 204 and the polymer column 205 that is positioned at opening 204 in polymeric layer by exposure and developing process, save processing step.
The material of polymeric layer 203 is the photosensitive organic thing, described photosensitive organic thing is photosensitive epoxy resin, polyimides, phenyl ring butylene, polybenzoxazoles, can be formed opening 204 and polymer column 205 by polymeric layer 203 exposing and developing, and the polymeric layer 203 of remaining covering semiconductor base 201 and part of solder pads layer 202 can also be as the separator between semiconductor package and external environment condition.It should be noted that, described polymeric layer 203 or polymer column 205 also can adopt other suitable materials.
The forming process of opening 204 and polymer column 205 is: form the polymeric layer 203 that covers described semiconductor base 201 and soldering pad layer 202 surfaces; Exposed and developed, formed the opening 204 on expose portion soldering pad layer surface in polymeric layer 203, being formed some discrete polymer columns 205 on soldering pad layer 202 surfaces in opening 204 simultaneously.In the present embodiment, the height of described polymer column 205 equals the thickness of the polymeric layer 203 on soldering pad layer 202 surfaces.
The quantity of described polymer column 205 is more than or equal to 1, and such as being 1,2,3,4,5,6 etc., and the size of described polymer column 205 is less than the size of opening.In specific embodiment, the quantity of described polymer column 205 can be 2～5, when can make the surface area of the protruding lower metal layer of follow-up formation increase, can guarantee again the protruding lower metal layer and the soldering pad layer 202 electricity contact performancies that form.
In specific embodiment, the shape of described polymer column 205 can be cylindrical, circular platform type, cube or irregularly shaped.
In specific embodiment, when polymer column 205 columns are a plurality of, polymer column 205 can be the zone line that symmetric figure (figure that each polymer column 205 central point lines form) is arranged in opening, make the surface area of the protruding lower metal layer of follow-up formation increase regional certain line of symmetry that also has, make the projection or the metal column that form on protruding lower metal layer identical in different directions with the adhesion between protruding lower metal layer, improved the uniformity of compressive resistance or the anti-stress of projection or metal column.Concrete described symmetric figure can be straight line, circle, donut, regular polygon (comprising triangle, quadrangle, pentagon etc.), array structure etc.In other embodiments, described polymer column 205 can be the irregular figure arrangement.It should be noted that, the arrangement mode of polymer column and quantity and shape can not limit the scope of the invention.
In specific embodiment, the bottom width of described polymer column 205 is greater than the width at top, during the protruding lower metal layer of follow-up formation, prevent between protruding lower metal layer stopping up the opening between polymer column 205, can so that the surface of protruding lower metal layer along with polymer column 205 height rises and falls, thereby form the protruding lower metal layer that surface area increases.
In specific embodiment, when the quantity of polymer column 205 is greater than two, distance between adjacent polymeric thing column 205 is greater than 2 times of protruding lower metal layer thickness of follow-up formation, make the protruding lower metal layer of follow-up formation can not fill opening between full polymer column 205, thereby form the protruding lower metal layer that surface area increases.
In the present invention, existence due to polymer column 205, the follow-up soldering pad layer 202 forming the 204 interior exposures of covering opening, during the protruding lower metal layer of polymer column 205 and partial polymer layer 203, make the surface height of the protruding lower metal layer of opening 204 interior formation rise and fall, thereby increased the size of the surface area of protruding lower metal layer, when the protruding lower metal layer surface on opening 204 forms projection or metal column, make the contact area of projection or metal column and protruding lower metal layer increase, thereby increased the adhesiveness of projection or metal column and protruding lower metal layer, when projection or metal column when being subject to external pressure or internal stress, prevent that projection or metal column from coming off from protruding lower metal layer surface or preventing from producing rift defect at both contact interfaces.
Then, please refer to Fig. 4, form the protruding lower metal layer 206 on partial polymer layer 203 surface outside soldering pad layer 202, polymer column 205 and the opening 204 covered in described opening 204.
Conductive layer or Seed Layer when described protruding lower metal layer 206 forms metal column as follow-up plating, and as the adhesion layer between metal column and soldering pad layer.
Described protruding lower metal layer 206 can be one or more in aluminium, nickel, copper, titanium, chromium, tantalum, gold, silver.
Described protruding lower metal layer 206 can be the single or multiple lift stacked structure, such as, protruding lower metal layer 206 can be the double stacked structure of ambrose alloy, titanium, nickel aluminium.
The formation technique of described protruding lower metal layer 206 is sputter or physical vapour deposition (PVD) etc., the thickness of described protruding lower metal layer 206 is less than the height of the polymer column 205 on soldering pad layer 202 surfaces, so that the surface of the protruding lower metal layer 206 formed, along with the surface height fluctuating of polymer column 205, has increased the surface area of the protruding lower metal layer formed.
Then, with reference to figure 5, form solder layer 207 on the protruding lower metal layer 206 in described opening and the protruding lower metal layer 206 of the part outside opening.
The material of described solder layer 207 is one or more in the metals such as tin, Xi Yin, tin lead, SAC, tin silver zinc, tin zinc, tin bismuth indium, tin indium, Sillim, tin copper, tin zinc indium or tin silver antimony.Follow-uply solder layer 207 is carried out to reflux technique form projection (bump).
The formation technique of described solder layer 207 can be for electroplating or screen painting.In the present embodiment, the formation technique of described solder layer 207 is for electroplating, its detailed process is: form the mask layer (such as photoresist layer) that covers described protruding lower metal layer 206, have the second opening that exposes the protruding lower metal layer of part 206 surfaces on soldering pad layer in described mask layer; Using the conductive layer of protruding lower metal layer 206 when electroplating, form solder layer 207 in described the second opening; Finally remove described mask layer.
With reference to figure 6, take described solder layer 207(with reference to figure 5) be mask, remove the protruding lower metal layer 206 of solder layer 207 both sides; Described solder layer 207 is refluxed, formed projection (or salient point or solder joint or soldered ball) 208.
The protruding lower metal layer 206 of removing described solder layer 207 both sides can adopt wet method or dry etch process.
In other embodiments of the invention, please refer to Fig. 7, after forming protruding lower metal layer 206, also can adopt electroplating technology, form metal column 209 on the protruding lower metal layer 206 on soldering pad layer 202, at metal column 209 top surfaces, form solder layer; Remove the protruding lower metal layer of metal column 209 both sides; Solder layer is annealed, at the top surface formation projection (or salient point or solder joint or soldered ball) 210 of metal column 209.
Described metal column 209 materials are copper or the copper alloy that contains other metals.Described other metals can be one or more in tantalum, indium, tin, zinc, manganese, chromium or nickel.Described metal column 209 can be also other suitable metal materials.
The semiconductor package that the embodiment of the present invention also provides a kind of said method to form, please refer to Fig. 6, comprising:
Cover the polymeric layer 203 of described semiconductor base 201 and soldering pad layer 202, there is the opening on the described soldering pad layer of expose portion 202 surfaces in described polymeric layer 203, on soldering pad layer 202 surfaces in opening, there are some discrete polymer columns 205;
Be positioned at the outer lip-deep protruding lower metal layer 206 of partial polymer layer 203 of soldering pad layer 202, polymer column 205 and opening of described opening.
Concrete, the material of described polymer column 205 is identical with the material of polymeric layer 203.The material of described polymeric layer 203 is the photosensitive organic thing, and described photosensitive organic thing is photosensitive epoxy resin, polyimides, phenyl ring butylene, polybenzoxazoles.
The quantity of described polymer column 205 is more than or equal to 1, and the size of polymer column 205 is less than the size of opening.
The thickness of described protruding lower metal layer 206 is less than the height of the polymer column 205 on soldering pad layer 202 surfaces.
Described protruding lower metal layer 206 is the single or multiple lift stacked structure.
Also comprise: be positioned at the projection 208 on the protruding lower metal layer 206 on opening.
In other embodiments of the invention, please refer to Fig. 7, also comprise: be positioned on the protruding lower metal layer 206 on opening and form metal column 209; Be positioned at the projection 210 of metal column 209 top surfaces.
Although the present invention discloses as above, the present invention not is defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with the claim limited range.
Claims (10)
1. a semiconductor package, is characterized in that, comprising:
Semiconductor base, be positioned at the soldering pad layer on semiconductor base;
Cover the polymeric layer of described semiconductor base and soldering pad layer, there is the opening on expose portion soldering pad layer surface in described polymeric layer, on the soldering pad layer surface in opening, there are some discrete polymer columns;
Be positioned at the outer lip-deep protruding lower metal layer of partial polymer layer of described soldering pad layer, polymer column and opening.
2. semiconductor package as claimed in claim 1, is characterized in that, the material of described polymer column is identical with the material of polymeric layer.
3. semiconductor package as claimed in claim 1, is characterized in that, the material of described polymeric layer is the photosensitive organic thing.
4. semiconductor package as claimed in claim 3, is characterized in that, described photosensitive organic thing is photosensitive epoxy resin, polyimides, phenyl ring butylene, polybenzoxazoles.
5. semiconductor package as claimed in claim 1, is characterized in that, the quantity of described polymer column is more than or equal to 1.
6. semiconductor package as claimed in claim 5, is characterized in that, the size of polymer column is less than the size of opening.
7. semiconductor package as claimed in claim 1, is characterized in that, the thickness of described protruding lower metal layer is less than the height of the polymer column on soldering pad layer surface.
8. semiconductor package as claimed in claim 1, is characterized in that, described protruding lower metal layer is the single or multiple lift stacked structure.
9. semiconductor package as claimed in claim 1, is characterized in that, also comprises: be positioned at the projection on the protruding lower metal layer on opening.
10. semiconductor package as claimed in claim 1, is characterized in that, also comprises: be positioned at the metal column on the protruding lower metal layer on opening.
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| CN2013104547751A CN103474402A (en) | 2013-09-29 | 2013-09-29 | Semiconductor package structure |
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| CN2013104547751A CN103474402A (en) | 2013-09-29 | 2013-09-29 | Semiconductor package structure |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103871908A (en) * | 2014-03-28 | 2014-06-18 | 江阴长电先进封装有限公司 | Method for encapsulating copper pillar bump |
| CN104465571A (en) * | 2014-12-16 | 2015-03-25 | 南通富士通微电子股份有限公司 | Wafer packaging structure |
| CN106252316A (en) * | 2015-06-05 | 2016-12-21 | 华亚科技股份有限公司 | Attachment structure and manufacture method thereof |
| CN106653719A (en) * | 2016-12-30 | 2017-05-10 | 通富微电子股份有限公司 | Wafer level packaging structure and packaging method |
| CN106847783A (en) * | 2017-01-19 | 2017-06-13 | 通富微电子股份有限公司 | Make the method and bump packaging structure of bump packaging structure |
| CN107591386A (en) * | 2016-07-06 | 2018-01-16 | 南亚科技股份有限公司 | Semiconductor structure and its manufacture method |
| CN111261608A (en) * | 2018-11-30 | 2020-06-09 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of forming the same |
| WO2020192347A1 (en) * | 2019-03-27 | 2020-10-01 | 京东方科技集团股份有限公司 | Driving backplane and manufacturing method thereof and display panel |
| CN113611680A (en) * | 2021-09-28 | 2021-11-05 | 甬矽电子(宁波)股份有限公司 | Anti-drop bump packaging structure and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1431681A (en) * | 2002-01-03 | 2003-07-23 | 台湾积体电路制造股份有限公司 | Method for encapsulation in chip level by use of electroplating mask of elastic body |
| CN1635634A (en) * | 2003-12-30 | 2005-07-06 | 中芯国际集成电路制造(上海)有限公司 | Method and apparatus for producing welding pad for chip level packaging |
| US20070020906A1 (en) * | 2005-07-21 | 2007-01-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming high reliability bump structure |
| US20090079070A1 (en) * | 2007-09-20 | 2009-03-26 | Stats Chippac, Ltd. | Semiconductor Package with Passivation Island for Reducing Stress on Solder Bumps |
-
2013
- 2013-09-29 CN CN2013104547751A patent/CN103474402A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1431681A (en) * | 2002-01-03 | 2003-07-23 | 台湾积体电路制造股份有限公司 | Method for encapsulation in chip level by use of electroplating mask of elastic body |
| CN1635634A (en) * | 2003-12-30 | 2005-07-06 | 中芯国际集成电路制造(上海)有限公司 | Method and apparatus for producing welding pad for chip level packaging |
| US20070020906A1 (en) * | 2005-07-21 | 2007-01-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming high reliability bump structure |
| TWI305405B (en) * | 2005-07-21 | 2009-01-11 | Taiwan Semiconductor Mfg | Method for forming high reliability bump structure |
| US20090079070A1 (en) * | 2007-09-20 | 2009-03-26 | Stats Chippac, Ltd. | Semiconductor Package with Passivation Island for Reducing Stress on Solder Bumps |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103871908A (en) * | 2014-03-28 | 2014-06-18 | 江阴长电先进封装有限公司 | Method for encapsulating copper pillar bump |
| CN104465571A (en) * | 2014-12-16 | 2015-03-25 | 南通富士通微电子股份有限公司 | Wafer packaging structure |
| US10950564B2 (en) | 2015-06-05 | 2021-03-16 | Micron Technology, Inc. | Methods of forming microelectronic devices having a patterned surface structure |
| CN106252316A (en) * | 2015-06-05 | 2016-12-21 | 华亚科技股份有限公司 | Attachment structure and manufacture method thereof |
| US10008461B2 (en) | 2015-06-05 | 2018-06-26 | Micron Technology, Inc. | Semiconductor structure having a patterned surface structure and semiconductor chips including such structures |
| US10354966B2 (en) | 2015-06-05 | 2019-07-16 | Micron Technology, Inc. | Methods of forming microelectronic structures having a patterned surface structure |
| US11640948B2 (en) | 2015-06-05 | 2023-05-02 | Micron Technology, Inc. | Microelectronic devices and apparatuses having a patterned surface structure |
| CN107591386A (en) * | 2016-07-06 | 2018-01-16 | 南亚科技股份有限公司 | Semiconductor structure and its manufacture method |
| CN107591386B (en) * | 2016-07-06 | 2019-11-26 | 南亚科技股份有限公司 | Semiconductor structure and its manufacturing method |
| CN106653719A (en) * | 2016-12-30 | 2017-05-10 | 通富微电子股份有限公司 | Wafer level packaging structure and packaging method |
| CN106653719B (en) * | 2016-12-30 | 2020-01-17 | 通富微电子股份有限公司 | Wafer level packaging structure and packaging method |
| CN106847783A (en) * | 2017-01-19 | 2017-06-13 | 通富微电子股份有限公司 | Make the method and bump packaging structure of bump packaging structure |
| CN106847783B (en) * | 2017-01-19 | 2020-03-27 | 通富微电子股份有限公司 | Method for manufacturing bump packaging structure and bump packaging structure |
| CN111261608A (en) * | 2018-11-30 | 2020-06-09 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of forming the same |
| US11217538B2 (en) | 2018-11-30 | 2022-01-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit package and method |
| WO2020192347A1 (en) * | 2019-03-27 | 2020-10-01 | 京东方科技集团股份有限公司 | Driving backplane and manufacturing method thereof and display panel |
| CN113611680A (en) * | 2021-09-28 | 2021-11-05 | 甬矽电子(宁波)股份有限公司 | Anti-drop bump packaging structure and preparation method thereof |
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