CN106652957A - Liquid crystal display device and drive method - Google Patents
Liquid crystal display device and drive method Download PDFInfo
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- CN106652957A CN106652957A CN201710028926.5A CN201710028926A CN106652957A CN 106652957 A CN106652957 A CN 106652957A CN 201710028926 A CN201710028926 A CN 201710028926A CN 106652957 A CN106652957 A CN 106652957A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
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- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
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- Liquid Crystal Display Device Control (AREA)
Abstract
An embodiment of the invention discloses a liquid crystal display device and a drive method. The liquid crystal display device comprises a display panel and a drive circuit, wherein the display panel comprises a plurality of pixel units arranged into a matrix of n lines and m rows, each pixel unit comprises a thin film transistor, a pixel electrode connected with the output end of the thin film transistor and a common electrode located below the pixel electrode and isolated from the pixel electrode, the pixel units on the same row receive identical gray scale voltage, the pixel units on the same line receive an identical gating signal, and n and m are nonzero natural number; the drive circuit is used for providing drive signals including the gray scale voltage, the drive circuit generates multiple compensation voltage according to the distribution positions of various rows of pixel units, the high-level voltage of the gating signals corresponding to various rows of pixel units is respectively equal to the multiple compensation voltage, and the public voltage of the public electrodes of various rows of the pixel units is allowed to keep consistent within the error margin.
Description
Technical field
The present invention relates to display technology field, in particular it relates to liquid crystal indicator and driving method.
Background technology
Liquid crystal indicator is broadly divided into the liquid crystal of integrated raster data model (Gate Driver in Array, GIA) structure
The liquid crystal indicator of display device and general structure (non-GIA structures).
By taking the liquid crystal indicator of general structure as an example, liquid crystal indicator mainly include display floater, display floater it
Outer gate drivers and source electrode driver, display floater includes being arranged in multiple pixel cells of matrix, each pixel
Unit includes thin film transistor (TFT) (Thin-film Transistor, TFT), pixel electrode and public electrode.Positioned at same
Capable pixel cell receives the same gating signal provided by gate drivers by scan line, positioned at the pixel list of same row
Unit receives the same gray scale voltage provided by source electrode driver by data wire.However, due to each row pixel cell and grid
The distance between driver difference, therefore the length of corresponding scan line is different, be distributed in the resistance and electricity corresponded in scan line
The value of appearance is different, so as to cause each row pixel cell to receive the response time difference of gate voltage.Because TFT obtains parasitic capacitance meeting
The voltage for making pixel electrode because of capacity effect when TFT is turned off produces feedthrough error (feedthrough), and feedthrough error amount
Size change with the change that each row pixel cell receives the response time of gate voltage, therefore, according to pixel electrode with it is public
Common electrode produce capacity effect understand, in each row pixel cell the common electric voltage of public electrode by distributing position affected and not
Unified, this phenomenon causes the display heterogeneity of liquid crystal indicator, have impact on the display quality of liquid crystal indicator.
To solve the inhomogenous problem of above-mentioned common electric voltage, prior art is using the thickness or compensation for increasing metal routing layer
The method of TFT parasitic capacitances adjusts the common electric voltage of the public electrode being distributed in each pixel cell.In theory, increase metal to walk
The thickness of line layer can reduce the resistance and electric capacity of the metal routings such as scan line, and so as to reduce each pixel cell gating electricity is received
The difference of the response time of pressure is realizing the unification of common electric voltage；The method of compensation TFT parasitic capacitances can be reduced in each picture
The feedthrough error produced on the pixel electrode of plain unit, so as to reduce public electrode in each pixel cell according to capacity effect
Difference between common electric voltage, that is, realize the unification of common electric voltage.
But in the implementation process to prior art, the wind of the increase meeting lifting process processing procedure of metal routing thickness degree
Danger, that is, reduce the product yield of liquid crystal indicator, and the compensation to TFT parasitic capacitances is also easily affected by manufacturing process
And expected effect difficult to realize.
The content of the invention
In order to solve the problems, such as above-mentioned prior art, the present invention provides a kind of liquid crystal indicator and driving method,
The unification of common electric voltage in each row pixel cell can be realized under the influence of manufacturing process is avoided.
A kind of liquid crystal indicator is embodiments provided, including：Display floater, including it is multiple be arranged in n rows m row
The pixel cell of matrix, each described pixel cell includes what thin film transistor (TFT) was connected with the thin film transistor (TFT) output end
Pixel electrode and the public electrode isolated below the pixel electrode and with the pixel electrode, pixel described in same row
Unit receives identical gray scale voltage, and with pixel cell described in a line identical gating signal is received, and n and m is non-zero natural number；
Drive circuit, for providing including the drive signal including the gray scale voltage, wherein, the drive circuit is according to each row pixel
The distributing position of unit generates multiple offset voltages, the high level voltage point of the gating signal corresponding with each row pixel cell
Deng Yu the plurality of offset voltage so that the common electric voltage value on public electrode in each row pixel cell allows model in error
It is consistent in enclosing.
Preferably, pixel cell described in n rows be divided into it is multigroup, each pixel cell group include pixel list described in adjacent k rows
Unit, k is the non-zero natural number less than n, the corresponding offset voltage of the k rows pixel cell that each pixel cell group is included
It is identical.
Preferably, the drive circuit includes voltage compensating circuit, and the voltage compensating circuit includes resistor voltage divider circuit,
For generating the plurality of offset voltage according to reference voltage.
Preferably, the drive circuit includes source electrode driver and gate drivers, and the source electrode driver provides described
Gray scale voltage, the gate drivers generate the gating signal, pixel cell described in each row according to the plurality of offset voltage
Respectively the corresponding gating signal is received by scan line.
Preferably, the electricity of the longer corresponding offset voltage of the pixel cell group of the length sum of the scan line
Pressure value is higher.
Preferably, the display floater also includes the multiple integrated raster data model being connected with pixel cell described in each row respectively
Circuit, the drive signal of the drive circuit output also includes multiple clock signals, the height electricity of the plurality of clock signal
Ordinary telegram pressure be respectively equal to the plurality of offset voltage, each described integrated gate drive circuitry respectively by with the drive circuit
Connected clock line receives the corresponding clock signal, and produces the gating signal according to the clock signal.
Preferably, corresponding to same group of each described integrated gate drive circuitry of the same pixel cell group, when described
The magnitude of voltage of the longer corresponding offset voltage of the integrated gate drive circuitry group of clock line sum is higher.
Preferably, the error allowed band includes -10mV to+10mV.
According to a further aspect in the invention, a kind of driving method for liquid crystal indicator, the liquid crystal are additionally provided
Display device includes display floater and drive circuit, and the display floater includes being arranged in multiple pixel cells of n rows m row, n
It is non-zero natural number with m, the driving method includes：Respectively to pixel cell output gray scale voltage described in each column；According to each row
The distributing position of the pixel cell generates multiple offset voltages；Respectively to pixel cell output gating signal described in every row, its
In, the high level voltage of the gating signal corresponding with each row pixel cell is respectively equal to the plurality of offset voltage so that
The common electric voltage value of each row pixel cell is consistent in error allowed band.
Preferably, the step of distributing position of the pixel cell according to each row generates multiple offset voltages includes：
Pixel cell described in n rows in display floater is divided into multigroup, adjacent k row pixel cells are included in every group of pixel cell, k is
Non-zero natural number；Generate multiple offset voltages corresponding with each pixel cell group respectively, the signal with the drive circuit
The magnitude of voltage of the corresponding offset voltage of the more remote pixel cell group of transmission range is bigger.
Liquid crystal indicator according to embodiments of the present invention and driving method, on the premise of manufacturing process is not relied on,
By providing the gating signal with different high level voltages to the pixel cell for being distributed in different rows, realize to each row pixel
The compensation of the common electric voltage in unit on public electrode so that the value of the common electric voltage on public electrode in each row pixel cell
It is consistent in the range of error is allowed, it is to avoid common electric voltage changes with the difference of pixel cell distributing position, improves
The display homogeneity of liquid crystal indicator, improves display quality.
Description of the drawings
By referring to the drawings to the description of the embodiment of the present invention, the above-mentioned and other purposes of the present invention, feature and
Advantage will be apparent from.
Fig. 1 illustrates the schematic block diagram of traditional liquid crystal display device.
Fig. 2 is illustrated in the case of gating signal identical in traditional liquid crystal display device in the pixel cell of different rows
The time dependent waveform diagram of grid voltage of TFT.
Fig. 3 illustrates the circuit model schematic of pixel cell in the display floater of traditional liquid crystal display device.
Fig. 4 illustrates the public affairs in the display floater of traditional liquid crystal display device in the pixel cell of diverse location on public electrode
The distribution schematic diagram of common voltage value.
Fig. 5 illustrates the distribution of the average common electric voltage value of each row pixel cell of display floater in traditional liquid crystal display device
Schematic diagram.
Fig. 6 illustrates the partial structural diagram of the gate drivers in the liquid crystal indicator of first embodiment of the invention.
Fig. 7 illustrates the structural representation of the gating signal output unit of first embodiment of the invention.
Fig. 8 illustrates the signal of the voltage compensating circuit of gate drivers in the liquid crystal indicator of first embodiment of the invention
Property circuit diagram.
Fig. 9 illustrates the high level voltage distribution of the gating signal of the corresponding different rows pixel cell of first embodiment of the invention
Exemplary waveform diagrams.
Figure 10 illustrates the public of display floater adjacent lines pixel cell in the liquid crystal indicator of first embodiment of the invention
The distribution schematic diagram of voltage difference.
Figure 11 illustrates the eDRAM of the gating signal output unit of first embodiment of the invention.
Figure 12 illustrates that the timing waveform of gating signal output unit in the alternate embodiment of first embodiment of the invention is illustrated
Figure.
Figure 13 illustrates the schematic block diagram of the liquid crystal indicator of traditional integrated gate drive configuration.
Figure 14 goes out the schematic diagram of the equivalent circuit of the liquid crystal indicator of traditional integrated gate drive configuration.
Figure 15 is illustrated and be located in the liquid crystal indicator of traditional integrated gate drive configuration display floater diverse location
The distribution schematic diagram of the common electric voltage value in pixel cell on public electrode.
Figure 16 illustrates each row pixel cell in the display floater of the liquid crystal indicator of traditional integrated gate drive configuration
Average common electric voltage value distribution schematic diagram.
Figure 17 illustrates the signal of the voltage compensating circuit of drive circuit in the liquid crystal indicator of second embodiment of the invention
Property circuit diagram.
Figure 18 illustrates the high level voltage point of the gating signal of the corresponding different rows pixel cell of second embodiment of the invention
The exemplary waveform diagrams of cloth.
Figure 19 illustrates the public of display floater adjacent lines pixel cell in the liquid crystal indicator of second embodiment of the invention
The distribution schematic diagram of voltage difference.
Figure 20 illustrates the eDRAM of the integrated gate drive circuitry of second embodiment of the invention.
Figure 21 illustrates that the timing waveform of gating signal output unit in the alternate embodiment of second embodiment of the invention is illustrated
Figure.
Figure 22 illustrates the basic flow sheet of the driving method of the liquid crystal indicator of third embodiment of the invention.
Specific embodiment
The present invention is more fully described hereinafter with reference to accompanying drawing.In various figures, identical element is attached using what is be similar to
Icon is remembered to represent.For the sake of clarity, the various pieces in accompanying drawing are not necessarily to scale.Additionally, not drawing in figure
Lead-out wire in addition to correspondence driving electrodes with induction electrode, and may not shown some known parts.
Describe hereinafter many specific details of the present invention, the structure of such as device, material, size, place's science and engineering
Skill and technology, to be more clearly understood that the present invention.But just as the skilled person will understand, can not press
The present invention is realized according to these specific details.
Fig. 1 illustrates the schematic block diagram of traditional liquid crystal display device.
As shown in figure 1, liquid crystal indicator 1000 includes drive circuit and display floater 1200.The drive circuit includes source
Driver 1100 and gate drivers 1300.Source electrode driver 1110 is display floater by a plurality of data lines D [1]～D [m]
1200 provide gray scale voltage Vgam, and gate drivers 1120 are provided by multi-strip scanning line G [1]～G [n] for display floater 1200
The natural number of gating signal sel, wherein n and m respectively more than or equal to 1.
Display floater 1200 includes the multiple pixel cells 1210 arranged by n row m column matrix, and each pixel cell 1210 is wrapped
A thin film transistor (TFT) (respectively TFT [11] to TFT [nm]), pixel electrode 1212 and public electrode are included, wherein, the leakage of TFT
Pole is connected with pixel electrode 1212, and public electrode is located at pixel electrode lower section and is isolated from it and forms pixel capacitance.Positioned at same
The gate interconnection of the TFT that the pixel cell of a line is included simultaneously is connected with a scan line outside display floater, positioned at same row
The TFT that included of pixel cell source electrode interconnection and be connected with the data line outside display floater.
The scanned line G [1] of gating signal sel that gate drivers 1300 are provided is transmitted to display floater to G [n]
1200, so as to the grid voltage Vg [1] to Vg [n] of the TFT in each pixel cell in display floater becomes with gating signal sel
Change so that TFT [11] to TFT [nm] is switched on respectively or turns off.
Under normal conditions, the chip size of gate drivers 1300 is significantly less than display floater 1200, therefore to realize
The optimization of scan line G [1] to G [n] length, gate drivers 1300 are typically positioned over the horizontal axis of display floater 1200
On line, the length which results in scan line G [the 1]～G [n] being connected between display floater 1200 and gate drivers 1300 is not united
One：When n be even number when, scan line G [1] to the length of G [n/2] is successively decreased successively, the length of scan line G [n/2+1] to G [n] according to
It is secondary to be incremented by；When n is odd number, the length of scan line G [1] to G [(n-1)/2] is successively decreased successively, scan line G [(n+1)/2] to G
The length of [n] is incremented by successively.
Because the wire of different length has different resistance values and capacitance, therefore, when gate drivers 1300 are distinguished
When exporting identical gating signal sel to each row pixel cell, the grid voltage Vg [1] to Vg of the TFT in each row pixel cell
[n] follows gating signal sel to change and there are the different response times, and the bigger scan line of the length corresponding response time is more
It is long.
Fig. 2 is illustrated in the case of gating signal identical in traditional liquid crystal display device in the pixel cell of different rows
The time dependent waveform diagram of grid voltage of TFT.It should be noted that only illustrating the corresponding picture of part of scanning line in Fig. 2
The time dependent waveform diagram of grid voltage of the TFT in plain unit.
As shown in Fig. 2 gating signal sel is a square wave, (gating signal sel when gating signal sel is high level
Voltage be high level voltage VselH when), the TFT received in that one-row pixels unit of the gating signal is both turned on, be elected to
When messenger sel is low level (when the voltage of gating signal sel is low level voltage VselL), the gating signal is received
That one-row pixels unit in TFT be turned off.
As shown in Fig. 2 at the t1 moment, gating signal sel is changed into high level voltage VselH from low level voltage VselL.This
When correspondence scan line G [1] to the TFT in the pixel cell of G [n] grid voltage Vg [1] to Vg [n] start by low level voltage
VselL is gradually risen to high level voltage VselH.
As shown in Fig. 2 at the t2 moment, gating signal sel is changed into low level voltage VselL from high level voltage VselH.This
When correspondence scan line G [1] to the TFT in the pixel cell of G [n] grid voltage Vg [1] to Vg [n] start by high level voltage
VselH declines, decline response time Tf [1] of grid voltage Vg [1] to Vg [n] to Tf [n] be respectively equal to the grid voltage by
High level voltage VselH is reduced to the time needed for low level voltage VselL.Due to scan line G [1] and G [n] length most
It is long, therefore the decline of the grid voltage Vg [1] and Vg [n] of the TFT in pixel cell corresponding with scan line G [1], G [n] responds
Time is most long, and the closer to the horizontal axis line position of display floater scan line corresponding to pixel cell in TFT grid
The decline response time of voltage is shorter.For example shown in Fig. 2, decline response time Tf [3] of grid voltage Vg [3] is less than grid electricity
Decline response time Tf [1] of decline response time Tf [2] of pressure Vg [2] less than grid voltage Vg [1] is (due to scan line G [1]
Length to scan line G [3] is sequentially reduced), decline response time Tf [n-2] of grid voltage Vg [n-2] is less than grid voltage
Decline response time Tf [n] of decline response time Tf [n-1] of Vg [n-1] less than grid voltage Vg [n] is (due to scan line G
[n-2] to the length of scan line G [n] increases successively).
Presence due to declining the response time, TFT needs certain turn-off time, grid voltage by being conducted to complete switch off
The decline response time it is shorter, the turn-off time of TFT is shorter, and the grid voltage Vg_off of TFT shutdown moments is bigger.
During TFT is turned off, TFT gate voltage is gradually dropped to the low electricity of gating signal sel by the grid voltage Vg_off of shutdown moment
Ordinary telegram presses VselL, so as to generate grid voltage variable quantity at the grid of TFT.The capacity effect of TFT (is related to parasitic gate electricity
Hold the electric capacity such as Cgs) voltage of the pixel electrode being connected with TFT drain can be made because of the grid voltage variable quantity of TFT to produce feedthrough
(feedthrough) error Vp.The grid voltage variable quantity of TFT is bigger, the feedthrough error of the pixel electrode voltage being attached thereto
Vp is bigger.It can be seen from analysis above, the closer to the horizontal axis line position of display floater scan line corresponding to pixel
The feedthrough error of pixel electrode voltage is bigger in unit, and further away from the horizontal axis line position of display floater scan line corresponding to
Pixel cell in pixel electrode voltage feedthrough error Vp it is less.For example shown in Fig. 1, the pixel electrode of correspondence scan line G [3]
The feedthrough error of voltage is more than correspondence scan line G [1] more than the feedthrough error of the pixel electrode voltage of correspondence scan line G [2]
The feedthrough error of pixel electrode voltage, the feedthrough error of the pixel electrode voltage of correspondence scan line G [n-2] is more than correspondence scan line
Feedthrough error of the feedthrough error of the pixel electrode voltage of G [n-1] more than the pixel electrode voltage of correspondence scan line G [n].
Fig. 3 illustrates the circuit model schematic of pixel cell in the display floater of traditional liquid crystal display device.
As shown in figure 3, in each pixel cell of display floater, the grid of TFT is connected to corresponding with the pixel cell
Scan line, the source electrode of TFT is connected to data wire corresponding with the pixel cell, and the drain electrode of TFT is connected to pixel electrode (quite
In one end of storage capacitance Cst and pixel capacitance Clc in parallel), public electrode is (equivalent to storage capacitance Cst and picture in parallel
The other end of plain electric capacity Clc) common electric voltage Vcom is provided, wherein, common electric voltage Vcom is the gray scale voltage that TFT source electrodes are received
High level voltage VdH and low level voltage VdL mean value.Because there is parasitic capacitance, therefore the grid and picture of TFT in TFT
There is parasitic capacitance Cp between plain electrode.According to above-mentioned analysis, according to grid voltage Vg_off and the gating letter of TFT shutdown moments
Difference between the low level voltage VselL of number sel obtains the feedthrough error Vp=(Vgh_off- of pixel electrode voltage
VselL)·Cp/(Cp+Cst+Clc).Presence and the electricity of storage capacitance Cst and pixel capacitance Clc due to feedthrough error Vp
Hold effect, common electric voltage Vcom=(VdH+VdL)/2 changes turn to Vcom=(VdH+VdH)/2-Vp, i.e. common electric voltage Vcom is presented
Linear change.Due to pixel electrode electricity in the pixel cell corresponding to the scan line the closer to the horizontal axis line position of display floater
The feedthrough error of pressure is bigger, and further away from the horizontal axis line position of display floater scan line corresponding to pixel cell in pixel
Feedthrough error Vp of electrode voltage is less, thus the closer to the horizontal axis line position of display floater scan line corresponding to pixel
Common electric voltage Vcom in unit on public electrode is less, and right further away from the scan line institute of the horizontal axis line position of display floater
Common electric voltage Vcom in the pixel cell answered on public electrode is bigger.
Fig. 4 illustrates the public affairs in the display floater of traditional liquid crystal display device in the pixel cell of diverse location on public electrode
The distribution schematic diagram of common voltage value.
As shown in figure 4, due in the pixel cell corresponding to the scan line the closer to the horizontal axis line position of display floater
The feedthrough error of pixel electrode voltage is bigger, and further away from the horizontal axis line position of display floater scan line corresponding to pixel
Feedthrough error Vp of pixel electrode voltage is less in unit, therefore the closer to the scan line institute of the horizontal axis line position of display floater
Common electric voltage Vcom in corresponding pixel cell on public electrode is less, and further away from the horizontal axis line position of display floater
Common electric voltage Vcom in pixel cell corresponding to scan line on public electrode is bigger.
And for the pixel cell 1210 in display floater per a line, the closer to the pixel list of gate drivers 1300
The grid of the thin film transistor (TFT) (TFT [xm] to TFT [x1] is one by one near gate drivers) in unit and gate drivers 1300 it
Between conductor length it is shorter, therefore, the common electric voltage the closer in the pixel cell of gate drivers 1300 on public electrode
Vcom is less.
Fig. 5 illustrates the distribution of the average common electric voltage value of each row pixel cell of display floater in traditional liquid crystal display device
Schematic diagram.
As shown in figure 5, the common electric voltage Vcom in each pixel cell in every one-row pixels unit is averaged, obtain
The average common electric voltage Avg.Vcom of row.Due to the pixel list corresponding to the scan line the closer to the horizontal axis line position of display floater
The feedthrough error of pixel electrode voltage is bigger in unit, and further away from the horizontal axis line position of display floater scan line corresponding to
Feedthrough error Vp of pixel electrode voltage is less in pixel cell, therefore the closer to the scanning of the horizontal axis line position of display floater
The average common electric voltage Avg.Vcom of row corresponding to line is less, and further away from the scan line institute of the horizontal axis line position of display floater
Average common electric voltage Avg.Vcom is bigger for corresponding row.It can be seen that the corresponding row of each row pixel cell is averagely public in display floater
Common voltage Avg.Vcom is linearly distributed.
According to feedthrough error Vp=(Vghoff- VselL) Cp/ (Cp+Cst+Clc) and Vcom=(VdH+VdL)/2-
Vp understand, common electric voltage Vcom linearly changes with feedthrough error Vp, feedthrough error Vp with TFT shutdown moment grid voltage
Vg_off linearly changes.
Due to scan line G [1] it is most long with the length of G [n], therefore in pixel cell corresponding with scan line G [1], G [n]
TFT grid voltage Vg [1] and Vg [n] the decline response time it is most long, then TFT corresponding with scan line G [1], G [n]
It is less in the grid voltage Vg_off of shutdown moment；And the closer to the horizontal axis line position of display floater scan line corresponding to
Pixel cell in TFT grid voltage decline that the response time is shorter, TFT shutdown moment grid voltage Vg_off
It is bigger.
Therefore, it is that the common electric voltage Vcom for ensureing each pixel cell in display floater can tend to be steady, needs each
TFT is close in the grid voltage Vg_off of shutdown moment.
First embodiment of the invention is realized to common electric voltage by adjusting the high level voltage VselH of gating signal sel
The compensation of Vcom so that Vcom levels off to steadily.
Fig. 6 illustrates the partial structural diagram of the gate drivers in the liquid crystal indicator of first embodiment of the invention.
As shown in fig. 6, the structure of block diagram of the liquid crystal indicator of first embodiment of the invention and the traditional liquid crystal shown in Fig. 1
The structure of block diagram of display device is identical, i.e., including drive circuit and display floater 1200, and drive circuit includes source electrode driver
1100 and gate drivers 1300, wherein source electrode driver 1110 is display floater 1200 by a plurality of data lines D [1]～D [m]
Gray scale voltage Vgam is provided, gate drivers 1120 are that display floater 1200 provides gating by multi-strip scanning line G [1]～G [n]
The natural number of signal sel [1] to sel [n], wherein n and m respectively more than or equal to 1.
In the present embodiment, gate drivers 1300 include voltage compensating circuit 1320 and multiple gating signal output units
SU [1] to SU [n].
Each gating signal output unit SU [1] to SU [n] receive gate clock signal gate_clk, enabling signal stp and
Timing control signal ctl simultaneously exports respectively gating signal sel [1]～sel [n] to scan line G [1]～G [n], wherein with it is existing
Unlike technology, the high level voltage VselH [1] to VselH [n] of gating signal sel [1] to sel [n] linearly changes.
Voltage compensating circuit 1320 generates offset voltage Vc [1] to Vc [n] according to reference voltage V refh.
Fig. 7 illustrates the structural representation of the gating signal output unit of first embodiment of the invention.
As shown in fig. 7, gating signal output unit SU [1] has to SU [n] to be respectively used to receive gate clock signal
Gate_clk, starting impulse signal stp, offset voltage Vc, low level voltage VselL and timing control signal ctl it is multiple
Input and the output end for exporting gating signal sel.
In each gating signal output unit, shift register 1311 is according to gate clock signal gate_clk and startup
Pulse signal stp exports the first preparatory signal, and reception offset voltage Vc of level shifting circuit 1312 and low level voltage VselL are simultaneously
And the first preparatory signal is converted into the second preparatory signal in the presence of timing control signal ctl, and (the second preparatory signal is height
Voltage during level logic be equal to offset voltage Vc, for low-level logic when voltage be equal to low level voltage VselL), output
Buffer circuit receives offset voltage Vc and low level voltage VselL and enters row buffering to the second preparatory signal and obtains final gating
Signal sel (the high level voltage VselH of gating signal sel be equal to offset voltage Vc, for low-level logic when voltage be equal to it is low
Level voltage VselL).
Each gating signal output unit SU [1] is to SU [n] compensation that respectively receiving voltage compensation circuit 1320 is generated electricity
Pressure Vc [1] to Vc [n], so that individual gating signal output unit 1310 correspondence output gating signal sel [1] to sel [n], so as to
TFT in each pixel cell of control display floater is close in the grid voltage Vg_off of shutdown moment, it is ensured that display floater
In the common electric voltage Vcom of each pixel cell can tend to be steady, improve the performance of liquid crystal indicator.
In above-mentioned analysis, can obtain：ΔVghoff=[(VdH+VdL)/2- Δ Vcom] (Cp+Cst+Clc)/Cp+
VselL, that is to say, that offset voltage Vc [1] can be chosen according to the linear variability law of the voltage of analysis common electric voltage Vcom
To Vc [n].
Fig. 8 illustrates the signal of the voltage compensating circuit of gate drivers in the liquid crystal indicator of first embodiment of the invention
Property circuit diagram.
Voltage compensating circuit 1320 can be realized by resistor voltage divider circuit as shown in Figure 8.Voltage compensating circuit includes string
Multiple resistance R [1] of connection to R [mid+1], one end of resistance R [1] receive reference voltage V refh, the other end and resistance R [2] string
Connection, one end ground connection of resistance R [min+1], the other end are connected with resistance R [mid], the node point between the resistance of each two series connection
Tong Guo not draw resistance be connected with each offset voltage Vc [1] to the output port of Vc [n] (when n be odd number when, mid1=(n+
1)/2, when n is even number, mid=n/2).Due in the present embodiment, to make display floater in public affairs in each row pixel cell
The upper common electric voltage Vcom of common electrode is of substantially equal, offset voltage Vc for needing the output linearity of voltage compensating circuit 1320 to change
[1] to Vc [n], according to above-mentioned analysis, offset voltage Vc [1] is maximum with Vc [n], and the closer to the horizontal axis of display floater
Offset voltage Vc is less corresponding to scan line.Therefore, the port for exporting offset voltage Vc [1] with Vc [n] is respectively by drawing electricity
Resistance is connected with the node between resistance R [1] and R [2], exports offset voltage Vc [2] with the port of Vc [n-1] respectively by drawing
Node between resistance and resistance R [2] and R [3] is connected, and by that analogy, output offset voltage Vc [min] or output compensation are electric
The port of pressure Vc [min] and Vc [mid+1] is respectively by drawing resistance and the node phase between resistance R [n] and resistance R [n+1]
Even, so that offset voltage Vc [1] of the output of voltage compensating circuit 1320 is maximum with Vc [n], and it is horizontal the closer to display floater
Offset voltage Vc corresponding to the scan line of axis is less.
Fig. 9 illustrates the high level voltage distribution of the gating signal of the corresponding different rows pixel cell of first embodiment of the invention
Exemplary waveform diagrams.Figure 10 illustrates display floater adjacent lines pixel cell in the liquid crystal indicator of first embodiment of the invention
Common electrical pressure reduction distribution schematic diagram.
As shown in figure 9, gate drivers 1300 export gating signal sel [1] extremely respectively by scan line G [1] to G [n]
Sel [n], because the high level voltage VselH [1] to VselH [n] of gating signal sel [1] to sel [n] is equal to voltage compensation electricity
Offset voltage Vc [1] that road 1320 generates is to Vc [n], therefore the high level voltage VselH [1] of gating signal sel [1] and gating
High level voltage VselH [n] highest of signal sel [n], the closer to the horizontal axis line position of display floater scan line corresponding to
Gating signal sel high level voltage VselH it is less.This be because scan line G [1] is most long with the length of G [n], so as to
The decline response time of the grid voltage Vg [1] and Vg [n] of the TFT in scan line G [1], the corresponding pixel cells of G [n] is most long,
Therefore the high level voltage of gating signal sel [1] corresponding with scan line G [1], G [n], sel [n] is set into highest with phase
The decline response time to shortening grid voltage；And the closer to the horizontal axis line position of display floater scan line corresponding to picture
The decline response time of the grid voltage of the TFT in plain unit is shorter, and the high level voltage of corresponding gating signal sel is got over
It is low, with the decline response time of relative increase grid voltage so that be distributed in the TFT [1y] to TFT of each row in display floater
[ny] (arranging from top to bottom), i.e., in display floater each row pixel essentially identical in the value of the grid voltage Vg_off of shutdown moment
Common electric voltage Vcom on the public electrode of unit is essentially identical.As shown in Figure 10, with display surface in traditional liquid crystal display device
The waveform of common electrical pressure differential deltap Vcom (scope is about 70mV～85mV) of the adjacent lines pixel cell of plate is compared, the present invention first
The liquid crystal indicator of embodiment makes the public affairs of adjacent lines pixel cell because the high level voltage to gating signal is compensated
Common-battery pressure differential deltap Vcom is obviously reduced (scope is about 10mV～20mV).
Figure 11 illustrates the eDRAM of the gating signal output unit of first embodiment of the invention.
As shown in figure 11, when the timing control signal ctl that gating signal output unit is received is high level, the gating
First preparatory signal (is selected from Vc [1] to Vc by the level shifting circuit in signal output unit according to corresponding offset voltage Vc
One of [n]) it is converted into the second preparatory signal and exports to output buffer so that the gating letter that output buffer is exported
The high level voltage VselH of number sel is equal to offset voltage Vc, so as to be realized to aobvious by the setting to high level voltage VselH
The linear change for showing the common electric voltage Vcom of the pixel cell that diverse location is distributed in panel is compensated.
Figure 12 illustrates that the timing waveform of gating signal output unit in the alternate embodiment of first embodiment of the invention is illustrated
Figure.
In above-described embodiment, the height electricity of gating signal sel [1] that every scan line G [1] to G [n] receives to sel [n]
Ordinary telegram pressure VselH [1] to VselH [n] corresponds to respectively offset voltage Vc [1] one of to Vc [n].Due to generally wrapping in display floater
Pixel cell containing large number of rows, accordingly, as a kind of alternative embodiment, the correspondence per k bar scan lines (k is the natural number more than 1)
One identical offset voltage Vc.
Such as same timing control signal ctl of each two gating signal output unit correspondence and offset voltage Vc.As schemed
Shown in 12, gating signal output unit SU [2] receives identical offset voltage Vc [1] and timing control signal ctl with SU [1],
So as to gating signal sel [2] cannot not export overlappingly respectively and with identical high level voltage and sel [1], gating signal output
Cell S U [4] receives identical offset voltage Vc [2] and timing control signal ctl with SU [3], so as to what is cannot do not exported overlappingly respectively
And gating signal sel [4] and sel [3] with identical high level voltage, the like.
Liquid crystal indicator according to a first embodiment of the present invention, on the premise of manufacturing process is not relied on, by right
The pixel cell for being distributed in different rows provides the gating signal with different high level voltages, realizes in each row pixel cell
The compensation of the common electric voltage on public electrode so that the value of the common electric voltage on public electrode in each row pixel cell is in error
It is consistent in the range of permission, it is to avoid common electric voltage changes with the difference of pixel cell distributing position, improves liquid crystal
The display homogeneity of showing device, improves display quality.
Figure 13 illustrates the schematic block diagram of the liquid crystal indicator of traditional integrated gate drive configuration.
As Figure 13 shows, the liquid crystal indicator 2000 of traditional integrated gate drive configuration includes drive circuit 2100 and shows
Show panel 2200.Drive circuit 2100 is that display floater 2200 provides gray scale voltage by a plurality of data lines D [1]～D [m]
Vgam, and be that display floater 2200 provides gating clock signal sclk [1] to sclk by multiple clock lines C [1]～C [n]
[n].Wherein m and n are the natural number more than or equal to 1.Drive circuit 2100 includes voltage compensating circuit 2120, the voltage compensation
Circuit generates offset voltage Vc [1] corresponding with gating clock signal sclk [1] to sclk [n] extremely according to reference voltage V refh
Vc[n]。
Display floater 2200 includes multiple integrated gate drive circuitries (Gate Driver in Array, GIA) GIA [1]
The multiple pixel cells 2210 arranged to GIA [n] and by n row m column matrix.Each pixel cell 2210 includes a film crystalline substance
Body pipe (one of TFT [11] to TFT [nm]), pixel electrode 2212 and public electrode, wherein, the drain electrode of TFT and pixel electrode
2212 are connected, and public electrode is located at the lower section of pixel electrode and is isolated from it forming pixel capacitance.Positioned at the pixel of same a line
The gate interconnection of the TFT that unit is included and integrated gate drive circuitry corresponding with are connected, positioned at the pixel of same row
The source electrode interconnection of the TFT that unit is included simultaneously is connected with the data line (selected from one of D [1]～D [m]) outside display floater.
Integrated gate drive circuitry GIA [1] to GIA [n] obtains choosing by clock line C [1]～C [n] from drive circuit 2100 respectively
Logical clock signal sclk [1] is to sclk [n].
Figure 13 illustrate only the line between section driving circuit 2100 and each integrated gate drive circuitry.
Figure 14 goes out the schematic diagram of the equivalent circuit of the liquid crystal indicator of traditional integrated gate drive configuration.
As Figure 14 shows that each row pixel cell being connected with each integrated gate drive circuitry in display floater is abstracted bunchiness
The equivalent resistance Rgate of connection and equivalent capacity Cgate, the equivalent resistance Rgate of series connection and a termination of equivalent capacity Cgate
Ground, other end integrated gate drive circuitry corresponding with is connected.Integrated gate drive circuitry GIA in display floater 2200
[1] from top to bottom it is arranged in order that (integrated gate drive circuitry GIA [1] is extremely with the position of the pixel cell of corresponding row to GIA [n]
GIA [n] may be located at the homonymy of display floater, it is also possible to be alternately located in the of laterally opposite both sides of display floater), work as drive circuit
2100 lower sections for being located at display floater place plane and when on the extension line of display floater longitudinal central axis line, integrated grid drives
Dynamic circuit GIA [1] to GIA [n] levels off to one by one drive circuit 2100, i.e. the length of clock line C [1] to C [n] is successively decreased successively.
Therefore, the resistance value on clock line C [1] to C [n] is successively decreased successively with capacitance, i.e. integrated gate drive circuitry GIA [1] to GIA
[n] receives the response time of gating clock signal sclk [1] to sclk [n] and successively decreases successively so that integrated gate drive circuitry
Gating signal sel [1] that GIA [1] to GIA [n] is exported is successively decreased successively to the response time of sel [n], so that correspondence row
Pixel cell in TFT grid voltage Vg [1] to Vg [n] response time successively decrease successively, correspondence row pixel cell in
Feedthrough error Vp [1] of pixel electrode voltage increases successively to Vp [n], public electrode in the pixel cell of correspondence row it is public
Voltage Vcom [1] to Vcom [n] is sequentially reduced.
Figure 15 is illustrated and be located in the liquid crystal indicator of traditional integrated gate drive configuration display floater diverse location
The distribution schematic diagram of the common electric voltage value in pixel cell on public electrode.In the liquid of the integrated gate drive configuration shown in Figure 15
In crystal device, the pixel cell in display floater per a line is connected respectively with the GIA positioned at the pixel cell row two ends, shape
Liquidate GIA structures into both-end.
As shown in figure 15, it is because the length of the clock line the closer to drive circuit 2100 is shorter therefore electric the closer to driving
Feedthrough error Vp of pixel electrode is bigger in the pixel cell on road 2100, and further away from picture in the pixel cell of drive circuit 2100
Feedthrough error Vp of plain electrode is less.According to Vp=(Vgh_off-VselL) Cp/ (Cp+Cst+Clc) and Vcom=(VdH
+ VdH)/2-Vp understand, the common electric voltage Vcom of public electrode is less the closer in the pixel cell of drive circuit 2100, and gets over
It is bigger away from the common electric voltage Vcom of public electrode in the pixel cell of drive circuit 2100.
And for the pixel cell in display floater per a line, the film crystal the closer in the pixel cell of GIA
The grid of pipe (more remote the closer to the thin film transistor (TFT) of display floater longitudinal central axis line and the distance of GIA in TFT [xm] to TFT [x1])
Conductor length between pole and GIA is shorter, therefore in each pixel cell row, the common electrical the closer in the pixel cell of GIA
The common electric voltage Vcom for extremely going up is less.
Figure 16 illustrates each row pixel cell in the display floater of the liquid crystal indicator of traditional integrated gate drive configuration
Average common electric voltage value distribution schematic diagram.
As shown in figure 16, the common electric voltage in each pixel cell in every one-row pixels unit is averaged, OK
Average common electric voltage Avg.Vcom.Due to the feedthrough error of pixel electrode voltage in the pixel cell the closer to drive circuit 2100
It is bigger, and it is less further away from feedthrough error Vp of pixel electrode voltage in the pixel cell of drive circuit 2100, therefore the closer to
The average common electric voltage Avg.Vcom of row of drive circuit 2100 is less, and further away from the average common electric voltage of row of drive circuit 2100
Avg.Vcom is bigger.It can be seen that the average common electric voltage Avg.Vcom of the corresponding row of each row pixel cell is linear in display floater
Distribution.
According to feedthrough error Vp=(Vgh_off-VselL) Cp/ (Cp+Cst+Clc) and Vcom=(VdH+VdH)/
2-Vp understands that common electric voltage Vcom linearly changes with feedthrough error Vp, feedthrough error Vp is electric in the grid of shutdown moment with TFT
Pressure Vg_off linearly changes.
Due to the length of clock line C [1] it is most long, therefore the grid of the TFT in pixel cell corresponding with clock line C [1]
The response time of voltage Vg [1] is most long, then TFT corresponding with clock line C [1] shutdown moment grid voltage Vg_off just
It is less；And the closer to the grid voltage of the TFT in the pixel cell of drive circuit response time is shorter, TFT is in shut-off wink
Between grid voltage Vg_off it is bigger.
Therefore, it is that the common electric voltage Vcom for ensureing each pixel cell in display floater can tend to be steady, needs each
TFT is close in the grid voltage Vg_off of shutdown moment.
The high level voltage that second embodiment of the invention passes through regulation gating clock signal sclk [1] to sclk [n]
VsclkH [1] to VsclkH [n] realizes the compensation to common electric voltage Vcom so that Vcom levels off to steadily.
The structure of block diagram of the liquid crystal indicator of second embodiment of the invention and the traditional liquid crystal display device shown in Figure 13
Structure of block diagram it is identical, i.e., including drive circuit and display floater, drive circuit is aobvious by a plurality of data lines D [1]～D [m]
Show that panel provides gray scale voltage Vgam, and gating clock signal is provided for display floater by multiple clock lines C [1]～C [n]
Sclk [1] to sclk [n].Wherein m and n are the natural number more than or equal to 1.Drive circuit includes voltage compensating circuit 2120,
The voltage compensating circuit generates multiple benefits corresponding with gating clock signal sclk [1] to sclk [n] according to reference voltage V refh
Repay voltage Vc [1] to Vc [n].
It should be noted that in the present embodiment, the quantity of integrated gate drive circuitry is equal to pixel cell in display floater
Row quantity, in alternate embodiments, an integrated gate drive circuitry can correspond to multirow pixel cell, or to carry
High driving ability, multiple integrated gate drive circuitries can correspond to the number of same one-row pixels unit, i.e. integrated gate drive circuitry
Amount can be more than or less than the line number of pixel cell in display floater.
Figure 17 illustrates the signal of the voltage compensating circuit of drive circuit in the liquid crystal indicator of second embodiment of the invention
Property circuit diagram.
Voltage compensating circuit 2120 can be realized by resistor voltage divider circuit as shown in figure 17.Voltage compensating circuit 2120 is wrapped
Multiple resistance R [1] of series connection are included to R [n+1], one end of resistance R [1] receives reference voltage V refh, the other end and resistance R [2]
Series connection, one end ground connection of resistance R [n+1], the other end are connected with resistance R [n], the node difference between the resistance of each two series connection
It is connected to the output port of Vc [n] with each offset voltage Vc [1] by drawing resistance.Due in the present embodiment, to make to show
Show that the upper common electric voltage Vcom of public electrode in panel in each row pixel cell is of substantially equal, need voltage compensating circuit
, to Vc [n], according to above-mentioned analysis, offset voltage Vc [1] to Vc [n] is successively for offset voltage Vc [1] of 2120 output linearities change
Reduce, therefore, export offset voltage Vc [1] port by draw resistance be connected with the node between resistance R [1] and R [2],
The port of output offset voltage Vc [2] is connected by drawing resistance with the node between resistance R [2] and R [3], by that analogy, defeated
The port for going out offset voltage Vc [n] is connected by drawing resistance with the node between resistance R [n] and resistance R [n+1], so that
Offset voltage Vc [1] of the output of voltage compensating circuit 2120 is sequentially reduced to Vc [n].
Figure 18 illustrates the high level voltage point of the gating signal of the corresponding different rows pixel cell of second embodiment of the invention
The exemplary waveform diagrams of cloth.Figure 19 illustrates display floater adjacent lines pixel list in the liquid crystal indicator of second embodiment of the invention
The distribution schematic diagram of the common electrical pressure reduction of unit.
As shown in figure 18, the output of drive circuit 2100 has multiple gate clock signal gate_ of different high level voltages
Clk, integrated gate drive circuitry GIA [1] to GIA [n] intercepts out gating from multiple gate clock signal gate_clk respectively
(the high level voltage VsclkH [1] of gating clock signal sclk [1] to sclk [n] is extremely to sclk [n] for clock signal sclk [1]
VsclkH [n] is respectively equal to offset voltage Vc [1] to Vc [n]), so as to integrated gate drive circuitry GIA [1] to GIA [n] respectively
The high level voltage VselH [1] of gating signal sel [1] to sel [n] of the grid output of TFT in the pixel cell of correspondence row
To VselH [n] offset voltage Vc [1] is equal to Vc [n].Integrated gate drive circuitry the closer to drive circuit 2100 is received
Gating clock signal sclk high level voltage VsclkH it is lower, i.e., each integrated grid of correspondence that drive circuit 2100 is exported
The high level voltage VsclkH [1] of the gating clock signal sclk [1] to sclk [n] of drive circuit GIA [1] to GIA [n] is extremely
VsclkH [n's] successively decreases successively, so that integrated gate drive circuitry GIA [1] to GIA [n] defeated to each row pixel cell institute
The high level voltage VselH [1] to VselH [n] of gating signal sel [1] for going out to sel [n] successively decreases successively, with increase successively by
The response time of the grid voltage of TFT in each row pixel cell under up to so that the TFT being distributed in display floater everywhere exists
The value of the grid voltage Vg_off of shutdown moment is essentially identical.As shown in figure 19, with display floater in traditional liquid crystal display device
The waveform of common electrical pressure differential deltap Vcom (scope is about 40mV～85mV) of adjacent lines pixel cell compare, the present invention second is real
Apply the liquid crystal indicator of example makes the public of adjacent lines pixel cell because the high level voltage to gating signal is compensated
Voltage difference delta Vcom is obviously reduced (scope is about 15mV～35mV).
Figure 20 illustrates the eDRAM of the integrated gate drive circuitry of second embodiment of the invention.
As shown in figure 20, when the timing control signal ctl that integrated gate drive circuitry is received is high level, this is integrated
Gate driver circuit intercepts out corresponding gating clock signal sclk from gate clock signal, and according to the gating clock signal
Sclk exports gating signal sel.
For example, the integrated gate drive circuitry GIA [2] being connected with clock line C [2] from drive circuit 2100 exported it is many
The high level voltage VsclkH [2] of the gating clock signal sclk [2] being truncated in individual gate clock signal gate_clk is less than
The integrated gate drive circuitry GIA [1] being connected with clock line C [1] believes from multiple gate clocks that drive circuit 2100 is exported
The high level voltage VsclkH [1] of the gating clock signal sclk [1] being truncated in number gate_clk, i.e., integrated raster data model electricity
The high level voltage VselH [2] of gating signal sel [2] of road GIA [2] outputs is defeated less than integrated gate drive circuitry GIA [1]
The high level voltage VselH [1] of gating signal sel [1] for going out, so as in display floater with integrated gate drive circuitry GIA
[2] TFT in that connected one-row pixels unit shutdown moment grid voltage Vg_off substantially with corresponding to integrated grid
TFT in that one-row pixels unit of drive circuit GIA [1] is identical in the grid voltage Vg_off of shutdown moment.According to Vp=
(Vgh_off-VselL) Cp/ (Cp+Cst+Clc) and Vcom=(VdH+
VdL knowable to)/2-Vp, pixel electrode in integrated gate drive circuitry GIA [1] pixel cells corresponding with GIA [2]
The feedthrough error of voltage is essentially identical, so as to common electric voltage Vcom is essentially identical.Pixel electrode voltage in other pixel cells
Feedthrough error and common electric voltage Vcom are essentially identical, and principle is as described above, will not be described here.
Figure 21 illustrates that the timing waveform of gating signal output unit in the alternate embodiment of second embodiment of the invention is illustrated
Figure.
In above-described embodiment, the sel [1] to sel [n] that each integrated gate drive circuitry GIA [1] to GIA [n] is exported
High level voltage VselH [1] to VselH [n] correspond to offset voltage Vc [1] respectively one of to Vc [n].Due in display floater
Large number of rows pixel cell is generally comprised, accordingly, as a kind of alternative embodiment, (k is the nature more than 1 per k bar scan lines
Number) one identical offset voltage Vc of correspondence.
Such as same timing control signal ctl of each two integrated gate drive circuitry correspondence and offset voltage Vc.As schemed
Shown in 20, integrated gate drive circuitry GIA [1] and GIA [2] is exported respectively according to identical timing control signal ctl and not overlapped
And gating signal sel [1] and sel [2] with identical high level voltage, integrated gate drive circuitry GIA [3] and GIA [4]
Gating signal sel [3] cannot not exported overlappingly respectively according to identical timing control signal ctl and with identical high level voltage
With sel [4], the like.
The liquid crystal indicator with integrated gate drive configuration according to a second embodiment of the present invention, is not relying on work
On the premise of skill processing procedure, the gating signal with different high level voltages is provided by the pixel cell to being distributed in different rows,
Realize the compensation to the common electric voltage on public electrode in each row pixel cell so that the public electrode in each row pixel cell
On common electric voltage value it is consistent in the range of error is allowed, it is to avoid common electric voltage is with the different of pixel cell distributing position
Change, improve the display homogeneity of liquid crystal indicator, improve display quality.
Figure 22 illustrates the basic flow sheet of the driving method of the liquid crystal indicator of third embodiment of the invention.The method bag
Include step S01 to S04.
In step S01, respectively gray scale voltage is exported to each column pixel cell.
In step S02, the pixel cell in display floater is divided into multigroup.
Liquid crystal indicator includes display floater and drive circuit, and the display floater includes being arranged in many of n rows m row
Individual pixel cell, n and m are non-zero natural number.Pixel cell described in n rows in display floater is divided into multigroup, every group of pixel list
Adjacent k row pixel cells are included in unit, k is non-zero natural number, and the value of k is unsuitable excessive, otherwise can affect to common electric voltage school
Positive precision.
In step S03, multiple offset voltages corresponding with each pixel cell group respectively are generated.With the letter of drive circuit
The magnitude of voltage of number corresponding offset voltage of the more remote pixel cell group of transmission range is bigger.
In step S04, according to offset voltage to each row pixel cell export gating signal so that often go the pixel list
Unit's output gating signal, the high level voltage of the gating signal corresponding with each row pixel cell is respectively equal to the plurality of benefit
Repay voltage so that the common electric voltage value of each row pixel cell is consistent in error allowed band.
The driving method for liquid crystal indicator according to a third embodiment of the present invention, is not relying on manufacturing process
Under the premise of, the gating signal with different high level voltages is provided by the pixel cell to being distributed in different rows, it is right to realize
The compensation of the common electric voltage in each row pixel cell on public electrode so that public on the public electrode in each row pixel cell
The value of voltage is consistent in the range of error is allowed, it is to avoid common electric voltage becomes with the different of pixel cell distributing position
Change, improve the display homogeneity of liquid crystal indicator, improve display quality.
In this manual, " horizontal " refers to the line direction of display floater, i.e., in display floater institute in the planes, grid
The orientation of each pixel cell that connected TFT is located；" longitudinal direction " refers to the column direction of display floater, i.e., in display floater
Institute in the planes, the orientation of each pixel cell that the connected TFT of source electrode is located." lower section " refers to be located with pixel electrode
Plane has the position of certain vertical range.
It should be noted that herein, such as first and second or the like relational terms are used merely to a reality
Body or operation make a distinction with another entity or operation, and not necessarily require or imply these entities or deposit between operating
In any this actual relation or order.And, term " including ", "comprising" or its any other variant are intended to
Nonexcludability is included, so that a series of process, method, article or equipment including key elements not only will including those
Element, but also including other key elements being not expressly set out, or also include for this process, method, article or equipment
Intrinsic key element.In the absence of more restrictions, the key element for being limited by sentence "including a ...", it is not excluded that
Also there is other identical element in process, method, article or equipment including the key element.
According to embodiments of the invention as described above, these embodiments do not have all of details of detailed descriptionthe, not yet
It is only described specific embodiment to limit the invention.Obviously, as described above, can make many modifications and variations.This explanation
These embodiments are chosen and specifically described to book, is in order to preferably explain the principle and practical application of the present invention, so that affiliated
Technical field technical staff can be used well using modification of the invention and on the basis of the present invention.The present invention only receives right
The restriction of claim and its four corner and equivalent.
Claims (10)
1. a kind of liquid crystal indicator, including：
Display floater, including multiple pixel cells for being arranged in n row m column matrix, each described pixel cell includes that film is brilliant
Pixel electrode that body pipe is connected with the thin film transistor (TFT) output end and positioned at pixel electrode lower section and with the pixel
The public electrode of electrode isolation, pixel cell described in same row receives identical gray scale voltage, connects with pixel cell described in a line
Identical gating signal is received, n and m is non-zero natural number；
Drive circuit, for providing including the drive signal including the gray scale voltage,
Wherein, the drive circuit generates multiple offset voltages according to the distributing position of each row pixel cell, with each row pixel list
The high level voltage of the corresponding gating signal of unit is respectively equal to the plurality of offset voltage so that in each row pixel cell
Common electric voltage value on public electrode is consistent in error allowed band.
2. liquid crystal indicator according to claim 1, wherein, pixel cell described in n rows is divided into multigroup, each pixel list
Tuple includes pixel cell described in adjacent k rows, and k is the non-zero natural number less than n,
The corresponding offset voltage of the k rows pixel cell that each pixel cell group is included is identical.
3. liquid crystal indicator according to claim 2, wherein, the drive circuit includes voltage compensating circuit, described
Voltage compensating circuit includes resistor voltage divider circuit, for generating the plurality of offset voltage according to reference voltage.
4. liquid crystal indicator according to claim 2, wherein, the drive circuit includes that source electrode driver and grid drive
Dynamic device, the source electrode driver provides the gray scale voltage, and the gate drivers generate institute according to the plurality of offset voltage
Gating signal is stated, pixel cell described in each row receives the corresponding gating signal by scan line respectively.
5. liquid crystal indicator according to claim 4, wherein, the longer pixel of the length sum of the scan line
The magnitude of voltage of the corresponding offset voltage of unit group is higher.
6. liquid crystal indicator according to claim 2, wherein, the display floater also include respectively with picture described in each row
The connected multiple integrated gate drive circuitries of plain unit, the drive signal of the drive circuit output also includes multiple clocks
Signal, the high level voltage of the plurality of clock signal is respectively equal to the plurality of offset voltage,
Each described integrated gate drive circuitry is respectively by corresponding with the clock line reception that the drive circuit is connected described
Clock signal, and the gating signal is produced according to the clock signal.
7. liquid crystal indicator according to claim 6, wherein, corresponding to each described of the same pixel cell group
Same group of integrated gate drive circuitry, the longer corresponding compensation of the integrated gate drive circuitry group of the clock line sum
The magnitude of voltage of voltage is higher.
8. liquid crystal indicator according to claim 1, wherein, the error allowed band includes -10mV to+10mV.
9. a kind of driving method for liquid crystal indicator, the liquid crystal indicator includes display floater and drive circuit,
The display floater includes being arranged in multiple pixel cells of n rows m row, and n and m is non-zero natural number, the driving method bag
Include：
Respectively to pixel cell output gray scale voltage described in each column；
The distributing position of pixel cell generates multiple offset voltages according to each row；
Respectively to pixel cell output gating signal described in every row,
Wherein, the high level voltage of the gating signal corresponding with each row pixel cell is respectively equal to the plurality of compensation electricity
Pressure so that the common electric voltage value of each row pixel cell is consistent in error allowed band.
10. driving method according to claim 9, wherein, the distributing position life of the pixel cell according to each row
The step of into multiple offset voltages, includes：
Pixel cell described in n rows in display floater is divided into it is multigroup, in every group of pixel cell include adjacent k row pixel lists
Unit, k is non-zero natural number；
Generate multiple offset voltages corresponding with each pixel cell group respectively, the signal transmission distance with the drive circuit
The magnitude of voltage of the corresponding offset voltage of more remote pixel cell group is bigger.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111027516A (en) * | 2019-12-25 | 2020-04-17 | 北京集创北方科技股份有限公司 | Biological characteristic image acquisition device and method and intelligent equipment |
| CN111883082A (en) * | 2020-07-30 | 2020-11-03 | 惠科股份有限公司 | Grid driving circuit, driving method and display |
| CN111883083A (en) * | 2020-07-30 | 2020-11-03 | 惠科股份有限公司 | Grid driving circuit and display device |
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| CN111883083B (en) * | 2020-07-30 | 2021-11-09 | 惠科股份有限公司 | Grid driving circuit and display device |
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