CN106652957B

CN106652957B - Liquid crystal display device and driving method

Info

Publication number: CN106652957B
Application number: CN201710028926.5A
Authority: CN
Inventors: 朱欢欢; 赵青青
Original assignee: InfoVision Optoelectronics Kunshan Co Ltd
Current assignee: InfoVision Optoelectronics Kunshan Co Ltd
Priority date: 2017-01-16
Filing date: 2017-01-16
Publication date: 2020-04-24
Anticipated expiration: 2037-01-16
Also published as: CN106652957A

Abstract

The embodiment of the invention discloses a liquid crystal display device and a driving method, wherein the liquid crystal display device comprises: the display panel comprises a plurality of pixel units which are arranged into an n-row m-column matrix, each pixel unit comprises a thin film transistor, a pixel electrode connected with the output end of the thin film transistor and a common electrode which is positioned below the pixel electrode and is isolated from the pixel electrode, the pixel units in the same row receive the same gray scale voltage, the pixel units in the same row receive the same gating signal, and n and m are non-zero natural numbers; and the driving circuit is used for providing driving signals including the gray scale voltages, generating a plurality of compensation voltages according to the distribution positions of the pixel units in each row, wherein the high-level voltages of the gating signals corresponding to the pixel units in each row are respectively equal to the plurality of compensation voltages, so that the common voltage values on the common electrodes in the pixel units in each row are kept consistent within an error allowable range.

Description

Liquid crystal display device and driving method

Technical Field

The present invention relates to the field of display technologies, and in particular, to a liquid crystal display device and a driving method.

Background

The liquid crystal display device is mainly classified into a Gate Driver in Array (GIA) structure integrated liquid crystal display device and a general structure (non-GIA structure) liquid crystal display device.

Taking a liquid crystal display device with a general structure as an example, the liquid crystal display device mainly includes a display panel, a gate driver and a source driver outside the display panel, the display panel includes a plurality of pixel units arranged in a matrix, and each pixel unit includes a Thin-film Transistor (TFT), a pixel electrode and a common electrode. The pixel units in the same row receive the same gate signal provided by the gate driver through the scan lines, and the pixel units in the same column receive the same gray scale voltage provided by the source driver through the data lines. However, due to the different distances between the pixel units in each row and the gate driver, the lengths of the corresponding scan lines are different, and the values of the resistors and the capacitors distributed on the corresponding scan lines are different, so that the response time of the pixel units in each row receiving the gate voltage is different. Because the parasitic capacitance of the TFT can cause the voltage of the pixel electrode to generate a feed-through error (feed-through) due to the capacitance effect when the TFT is turned off, and the magnitude of the feed-through error value changes with the response time of each row of pixel units receiving the gate voltage, according to the capacitance effect generated by the pixel electrode and the common electrode, the common voltage of the common electrode in each row of pixel units is not uniform due to the influence of the distribution position, which causes the display nonuniformity of the liquid crystal display device and affects the display quality of the liquid crystal display device.

In order to solve the problem of non-uniform common voltage, the prior art adjusts the common voltage of the common electrode distributed in each pixel unit by increasing the thickness of the metal wiring layer or compensating the parasitic capacitance of the TFT. Theoretically, increasing the thickness of the metal wiring layer can reduce the resistance and capacitance of metal wirings such as scanning lines and the like, thereby reducing the difference of response time of each pixel unit for receiving the gating voltage to realize the unification of the common voltage; the method of compensating the parasitic capacitance of the TFT may reduce a feedthrough error generated on the pixel electrode of each pixel unit, thereby reducing a difference between common voltages of the common electrodes in each pixel unit according to a capacitance effect, i.e., achieving uniformity of the common voltages.

However, in the implementation process of the prior art, the increase of the thickness of the metal trace layer may increase the risk of the process, i.e. decrease the product yield of the liquid crystal display device, and the compensation for the TFT parasitic capacitance is also easily affected by the process, so that it is difficult to achieve the desired effect.

Disclosure of Invention

In order to solve the problems in the prior art, the present invention provides a liquid crystal display device and a driving method thereof, which can realize the uniformity of the common voltage in each row of pixel units without the influence of the process.

An embodiment of the present invention provides a liquid crystal display device, including: the display panel comprises a plurality of pixel units which are arranged into an n-row m-column matrix, each pixel unit comprises a thin film transistor, a pixel electrode connected with the output end of the thin film transistor and a common electrode which is positioned below the pixel electrode and is isolated from the pixel electrode, the pixel units in the same row receive the same gray scale voltage, the pixel units in the same row receive the same gating signal, and n and m are non-zero natural numbers; and the driving circuit is used for providing driving signals including the gray scale voltages, generating a plurality of compensation voltages according to the distribution positions of the pixel units in each row, wherein the high-level voltages of the gating signals corresponding to the pixel units in each row are respectively equal to the plurality of compensation voltages, so that the common voltage values on the common electrodes in the pixel units in each row are kept consistent within an error allowable range.

Preferably, the n rows of pixel units are divided into a plurality of groups, each pixel unit group includes k adjacent rows of pixel units, k is a non-zero natural number smaller than n, and the compensation voltages corresponding to the k rows of pixel units included in each pixel unit group are the same.

Preferably, the driving circuit includes a voltage compensation circuit including a resistance voltage division circuit for generating the plurality of compensation voltages from a reference voltage.

Preferably, the driving circuit includes a source driver and a gate driver, the source driver provides the grayscale voltages, the gate driver generates the gate signals according to the compensation voltages, and each row of the pixel units receives the corresponding gate signals through the scan lines.

Preferably, the longer the sum of the lengths of the scan lines is, the higher the voltage value of the compensation voltage corresponding to the pixel cell group is.

Preferably, the display panel further includes a plurality of integrated gate driving circuits respectively connected to the pixel units in each row, the driving signal output by the driving circuit further includes a plurality of clock signals, high level voltages of the plurality of clock signals are respectively equal to the plurality of compensation voltages, and each integrated gate driving circuit receives the corresponding clock signal through a clock line connected to the driving circuit and generates the gating signal according to the clock signal.

Preferably, the voltage value of the compensation voltage corresponding to the integrated gate driving circuit group with a longer sum of the clock lines is higher for each integrated gate driving circuit corresponding to the same pixel cell group.

Preferably, the error tolerance range includes-10 mV to +10 mV.

According to another aspect of the present invention, there is also provided a driving method for a liquid crystal display device including a display panel including a plurality of pixel units arranged in n rows and m columns, n and m being non-zero natural numbers, and a driving circuit, the driving method including: respectively outputting gray scale voltage to each row of pixel units; generating a plurality of compensation voltages according to the distribution positions of the pixel units in each row; and respectively outputting gating signals to the pixel units of each row, wherein the high-level voltages of the gating signals corresponding to the pixel units of each row are respectively equal to the compensation voltages, so that the common voltage values of the pixel units of each row are kept consistent within an error allowable range.

Preferably, the step of generating a plurality of compensation voltages according to the distribution positions of the pixel units in each row includes: dividing n rows of pixel units in a display panel into a plurality of groups, wherein each group of pixel units comprises k adjacent rows of pixel units, and k is a non-zero natural number; the compensation voltages are generated so as to correspond to the respective pixel cell groups, and the voltage value of the compensation voltage corresponding to the pixel cell group having a longer signal transmission distance from the drive circuit is larger.

According to the liquid crystal display device and the driving method provided by the embodiment of the invention, on the premise of not depending on a process, the compensation of the common voltage on the common electrode in each row of pixel units is realized by providing the gating signals with different high-level voltages for the pixel units distributed in different rows, so that the value of the common voltage on the common electrode in each row of pixel units is consistent within an error allowable range, the common voltage is prevented from changing along with the difference of the distribution positions of the pixel units, the display uniformity of the liquid crystal display device is improved, and the display quality is improved.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.

Fig. 1 shows a schematic block diagram of a conventional liquid crystal display device.

Fig. 2 is a waveform diagram showing a variation with time of gate voltages of TFTs in pixel units of different rows in a conventional liquid crystal display device under the same gate signal.

Fig. 3 is a schematic circuit diagram of a pixel unit in a display panel of a conventional liquid crystal display device.

Fig. 4 is a schematic diagram showing the distribution of common voltage values on the common electrode in pixel units at different positions in the display panel of the conventional liquid crystal display device.

Fig. 5 is a diagram illustrating a distribution of average common voltage values of pixel units in each row of a display panel in a conventional liquid crystal display device.

Fig. 6 is a partial schematic structural diagram of a gate driver in a liquid crystal display device according to a first embodiment of the present invention.

Fig. 7 illustrates a schematic configuration diagram of a gate signal output unit according to a first embodiment of the present invention.

Fig. 8 shows a schematic circuit diagram of a voltage compensation circuit of a gate driver in a liquid crystal display device of a first embodiment of the present invention.

Fig. 9 is a schematic waveform diagram showing high-level voltage distributions of gate signals corresponding to different rows of pixel units according to the first embodiment of the present invention.

Fig. 10 is a schematic diagram illustrating a distribution of a common voltage difference between adjacent rows of pixel units in a display panel in a liquid crystal display device according to a first embodiment of the invention.

Fig. 11 illustrates a timing waveform diagram of the gate signal output unit according to the first embodiment of the present invention.

Fig. 12 shows a timing waveform diagram of the gate signal output unit in an alternative embodiment of the first embodiment of the present invention.

Fig. 13 shows a schematic block diagram of a conventional liquid crystal display device integrating a gate driving structure.

Fig. 14 is a schematic diagram showing an equivalent circuit of a conventional liquid crystal display device with an integrated gate driving structure.

Fig. 15 is a schematic diagram illustrating the distribution of common voltage values on the common electrode in pixel units located at different positions of the display panel in the conventional liquid crystal display device with integrated gate driving structure.

Fig. 16 is a schematic diagram illustrating a distribution of average common voltage values of pixel units in each row in a display panel of a conventional liquid crystal display device with an integrated gate driving structure.

Fig. 17 shows a schematic circuit diagram of a voltage compensation circuit of a driving circuit in a liquid crystal display device according to a second embodiment of the present invention.

Fig. 18 is a schematic waveform diagram showing a high-level voltage distribution of gate signals corresponding to different rows of pixel units according to the second embodiment of the present invention.

Fig. 19 is a schematic diagram illustrating a distribution of a common voltage difference between adjacent rows of pixel units in a display panel in a liquid crystal display device according to a second embodiment of the invention.

Fig. 20 is a timing waveform diagram of the integrated gate driving circuit according to the second embodiment of the present invention.

Fig. 21 shows a timing waveform diagram of a gate signal output unit in an alternative embodiment of the second embodiment of the present invention.

Fig. 22 is a basic flowchart showing a driving method of a liquid crystal display device according to a third embodiment of the present invention.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, lead-out lines other than the corresponding driving electrodes and sensing electrodes are not drawn in the drawings, and some well-known portions may not be shown.

In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

As shown in fig. 1, the liquid crystal display device 1000 includes a driving circuit and a display panel 1200. The driving circuit includes a source driver 1100 and a gate driver 1300. The source driver 1110 supplies a gray scale voltage Vgam to the display panel 1200 through a plurality of data lines D [1] to D [ m ], and the gate driver 1120 supplies a gate signal sel to the display panel 1200 through a plurality of scan lines G [1] to G [ n ], where n and m are natural numbers greater than or equal to 1, respectively.

The display panel 1200 includes a plurality of pixel units 1210 arranged in a matrix of n rows and m columns, each pixel unit 1210 includes a thin film transistor (TFT [11] to TFT [ nm ], respectively), a pixel electrode 1212, and a common electrode, wherein a drain of the TFT is connected to the pixel electrode 1212, and the common electrode is located below and isolated from the pixel electrode to form a pixel capacitor. The gates of the TFTs included in the pixel units in the same row are connected to each other and to a scan line outside the display panel, and the sources of the TFTs included in the pixel units in the same column are connected to each other and to a data line outside the display panel.

Gate signal sel provided by gate driver 1300 is transmitted to display panel 1200 through scan lines G [1] to G [ n ], so that gate voltages Vg [1] to Vg [ n ] of TFTs in respective pixel units in the display panel are varied in accordance with gate signal sel, so that TFTs [11] to TFT [ nm ] are turned on or off, respectively.

In general, the chip size of the gate driver 1300 is significantly smaller than that of the display panel 1200, so to optimize the lengths of the scan lines G [1] to G [ n ], the gate driver 1300 is generally disposed on the horizontal central axis of the display panel 1200, which results in non-uniformity of the lengths of the scan lines G [1] to G [ n ] connected between the display panel 1200 and the gate driver 1300: when n is even number, the lengths of the scanning lines G1 to G n/2 are decreased in sequence, and the lengths of the scanning lines G n/2+1 to G n are increased in sequence; when n is an odd number, the lengths of the scanning lines G1 to G [ (n-1)/2] are sequentially decreased and the lengths of the scanning lines G [ (n +1)/2] to G [ n ] are sequentially increased.

Since the wires with different lengths have different resistance values and capacitance values, when the gate driver 1300 outputs the same gate signal sel to each row of pixel units, respectively, the gate voltages Vg [1] to Vg [ n ] of the TFTs in each row of pixel units have different response times following the change of the gate signal sel, and the longer the length of the scan line, the longer the response time corresponding to the scan line.

Fig. 2 is a waveform diagram showing a variation with time of gate voltages of TFTs in pixel units of different rows in a conventional liquid crystal display device under the same gate signal. It should be noted that fig. 2 is a schematic waveform diagram showing the time-dependent change of the gate voltage of the TFT in the pixel unit corresponding to only a part of the scanning line.

As shown in fig. 2, the gate signal sel is a square wave, and when the gate signal sel is at a high level (i.e., the voltage of the gate signal sel is the high-level voltage VselH), the TFTs in the row of pixel units receiving the gate signal are all turned on, and when the gate signal sel is at a low level (i.e., the voltage of the gate signal sel is the low-level voltage VselL), the TFTs in the row of pixel units receiving the gate signal are all turned off.

As shown in fig. 2, at time t1, the gate signal sel changes from the low-level voltage VselL to the high-level voltage VselH. At this time, the gate voltages Vg [1] to Vg [ n ] of the TFTs in the pixel units corresponding to the scanning lines G [1] to G [ n ] start to gradually increase from the low level voltage VselL to the high level voltage VselH.

As shown in fig. 2, at time t2, the gate signal sel changes from the high-level voltage VselH to the low-level voltage VselL. At this time, the gate voltages Vg [1] to Vg [ n ] of the TFTs in the pixel units corresponding to the scanning lines G [1] to G [ n ] begin to fall from the high level voltage VselH, and the fall response times Tf [1] to Tf [ n ] of the gate voltages Vg [1] to Vg [ n ] are respectively equal to the time required for the gate voltage to fall from the high level voltage VselH to the low level voltage VselL. Since the scan lines G1 and G n have the longest length, the gate voltages Vg 1 and Vg n of the TFTs in the pixel units corresponding to the scan lines G1 and G n have the longest response time to fall, while the gate voltages of the TFTs in the pixel units corresponding to the scan lines closer to the axis in the lateral direction of the display panel have the shorter response time to fall. For example, as shown in fig. 2, the falling response time Tf [3] of the gate voltage Vg [3] is shorter than the falling response time Tf [2] of the gate voltage Vg [2] (since the length from the scan line G [1] to the scan line G [3] is sequentially decreased), the falling response time Tf [ n-2] of the gate voltage Vg [ n-2] is shorter than the falling response time Tf [ n-1] of the gate voltage Vg [ n-1] (since the length from the scan line G [ n-2] to the scan line G [ n ] is sequentially increased).

Due to the existence of the drop response time, a certain turn-off time is required from the turn-on state to the complete turn-off state of the TFT, the shorter the drop response time of the grid voltage is, the shorter the turn-off time of the TFT is, and the larger the grid voltage Vg _ off at the turn-off moment of the TFT is. During the turn-off of the TFT, the gate voltage of the TFT gradually drops from the gate voltage Vg _ off at the turn-off instant to the low level voltage VselL of the gate signal sel, so that a gate voltage variation is generated at the gate of the TFT. The capacitance effect of the TFT (capacitance related to the gate parasitic capacitance Cgs) causes a feed-through error Vp of the voltage of the pixel electrode connected to the drain of the TFT due to the gate voltage variation of the TFT. The larger the gate voltage variation of the TFT is, the larger the feed-through error Vp of the pixel electrode voltage connected thereto is. From the above analysis, the feedthrough error Vp of the pixel electrode voltage in the pixel unit corresponding to the scanning line closer to the horizontal axis of the display panel is larger, and the feedthrough error Vp of the pixel electrode voltage in the pixel unit corresponding to the scanning line farther from the horizontal axis of the display panel is smaller. For example, as shown in FIG. 1, the feedthrough error of the pixel electrode voltage corresponding to the scan line G [3] is larger than that of the pixel electrode voltage corresponding to the scan line G [2], and the feedthrough error of the pixel electrode voltage corresponding to the scan line G [ n-2] is larger than that of the pixel electrode voltage corresponding to the scan line G [ n-1 ].

As shown in fig. 3, in each pixel cell of the display panel, a gate of the TFT is connected to a scan line corresponding to the pixel cell, a source of the TFT is connected to a data line corresponding to the pixel cell, a drain of the TFT is connected to a pixel electrode (corresponding to one end of the storage capacitor Cst and the pixel capacitor Clc connected in parallel), and a common electrode (corresponding to the other end of the storage capacitor Cst and the pixel capacitor Clc connected in parallel) provides a common voltage Vcom, wherein the common voltage Vcom is an average value of a high-level voltage VdH and a low-level voltage VdL of a gray scale voltage received by the source of the TFT. Since the TFT has a parasitic capacitance, a parasitic capacitance Cp exists between the gate electrode of the TFT and the pixel electrode. According to the above analysis, the feed-through error Vp of the pixel electrode voltage is obtained from the difference between the gate voltage Vg _ off at the moment of turn-off of the TFT and the low-level voltage VselL of the gate signal sel (Vgh _ off-VselL) · Cp/(Cp + Cst + Clc). Due to the feed-through error Vp and the capacitance effect of the storage capacitor Cst and the pixel capacitor Clc, the common voltage Vcom ═ is changed to (VdH + VdL)/2 — Vp, that is, the common voltage Vcom exhibits a linear change. Since the feed-through error of the pixel electrode voltage in the pixel unit corresponding to the scanning line closer to the horizontal central axis of the display panel is larger, and the feed-through error Vp of the pixel electrode voltage in the pixel unit corresponding to the scanning line farther from the horizontal central axis of the display panel is smaller, the common voltage Vcom on the common electrode in the pixel unit corresponding to the scanning line closer to the horizontal central axis of the display panel is smaller, and the common voltage Vcom on the common electrode in the pixel unit corresponding to the scanning line farther from the horizontal central axis of the display panel is larger.

As shown in fig. 4, since the feed-through error of the pixel electrode voltage in the pixel unit corresponding to the scanning line closer to the horizontal axis line position of the display panel is larger, and the feed-through error Vp of the pixel electrode voltage in the pixel unit corresponding to the scanning line farther from the horizontal axis line position of the display panel is smaller, the common voltage Vcom on the common electrode in the pixel unit corresponding to the scanning line closer to the horizontal axis line position of the display panel is smaller, and the common voltage Vcom on the common electrode in the pixel unit corresponding to the scanning line farther from the horizontal axis line position of the display panel is larger.

For each row of pixel cells 1210 in the display panel, the shorter the length of the conductive line between the gate electrodes of the thin film transistors (TFT [ xm ] to TFT [ x1] are closer to the gate driver) in the pixel cells closer to the gate driver 1300 and the gate driver 1300, and thus, the smaller the common voltage Vcom on the common electrode in the pixel cells closer to the gate driver 1300.

As shown in fig. 5, the common voltage Vcom in each pixel unit in each row of pixel units is averaged to obtain a row average common voltage avg. Since the feed-through error of the pixel electrode voltage in the pixel unit corresponding to the scanning line closer to the horizontal axis position of the display panel is larger, and the feed-through error Vp of the pixel electrode voltage in the pixel unit corresponding to the scanning line farther from the horizontal axis position of the display panel is smaller, the row average common voltage avg.vcom corresponding to the scanning line closer to the horizontal axis position of the display panel is smaller, and the row average common voltage avg.vcom corresponding to the scanning line farther from the horizontal axis position of the display panel is larger. It can be seen that the average row common voltage avg.vcom corresponding to each row of pixel units in the display panel is linearly distributed.

According to the feed-through error Vp ═ Vgho (Vgho)_ffVselL) · Cp/(Cp + Cst + Clc) and Vcom ═ of (VdH + VdL)/2-Vp, it is known that the common voltage Vcom varies linearly with the feed-through error Vp, and the feed-through error Vp varies linearly with the gate voltage Vg _ off of the TFT at the turn-off instant.

Because the length of the scanning lines G [1] and G [ n ] is longest, the falling response time of the grid voltage Vg [1] and Vg [ n ] of the TFT in the pixel unit corresponding to the scanning lines G [1] and G [ n ] is longest, and the grid voltage Vg _ off of the TFT corresponding to the scanning lines G [1] and G [ n ] at the turn-off moment is smaller; the response time of the drop of the gate voltage of the TFT in the pixel unit corresponding to the scanning line closer to the horizontal axis of the display panel is shorter, and the gate voltage Vg _ off of the TFT at the moment of turning off is larger.

Therefore, to ensure that the common voltage Vcom of each pixel unit in the display panel can be smooth, the gate voltages Vg _ off of each TFT at the moment of turning off are required to be close.

The first embodiment of the present invention compensates the common voltage Vcom by adjusting the high level voltage VselH of the gate signal sel, so that Vcom approaches to be stable.

As shown in FIG. 6, the block diagram structure of the LCD device according to the first embodiment of the present invention is the same as the block diagram structure of the conventional LCD device shown in FIG. 1, that is, the LCD device includes a driving circuit and a display panel 1200, and the driving circuit includes a source driver 1100 and a gate driver 1300, wherein the source driver 1110 provides a gray scale voltage Vgam to the display panel 1200 through a plurality of data lines D [1] to D [ m ], and the gate driver 1120 provides gate signals sel [1] to sel [ n ] to the display panel 1200 through a plurality of scan lines G [1] to G [ n ], where n and m are natural numbers greater than or equal to 1 respectively.

In the present embodiment, the gate driver 1300 includes a voltage compensation circuit 1320 and a plurality of gate signal output units SU [1] to SU [ n ].

Each of the gate signal output units SU [1] to SU [ n ] receives the gate clock signal gate _ clk, the start signal stp and the timing control signal ctl and outputs the gate signals sel [1] to sel [ n ] to the scan lines G [1] to G [ n ], respectively, wherein high level voltages VselH [1] to VselH [ n ] of the gate signals sel [1] to sel [ n ] are linearly varied, unlike the prior art.

The voltage compensation circuit 1320 generates compensation voltages Vc [1] to Vc [ n ] from a reference voltage Vrefh.

As shown in fig. 7, the gate signal output units SU [1] to SU [ n ] have a plurality of input terminals for receiving the gate clock signal gate _ clk, the start pulse signal stp, the compensation voltage Vc, the low level voltage VselL, and the timing control signal ctl, respectively, and an output terminal for outputting the gate signal sel.

In each gate signal output unit, the shift register 1311 outputs a first preliminary signal according to the gate clock signal gate _ clk and the start pulse signal stp, the level shift circuit 1312 receives the compensation voltage Vc and the low-level voltage VselL and converts the first preliminary signal into a second preliminary signal (the voltage of the second preliminary signal when the second preliminary signal is a high-level logic is equal to the compensation voltage Vc and the voltage of the second preliminary signal when the second preliminary signal is a low-level logic is equal to the low-level voltage VselL) by the timing control signal ctl, and the output buffer circuit receives the compensation voltage Vc and the low-level voltage VselL and buffers the second preliminary signal to obtain a final gate signal sel (the high-level voltage VselL of the gate signal sel is equal to the compensation voltage Vc and the voltage of the gate signal when the second preliminary signal is a low-level logic is equal to the low-level voltage VselL).

Each of the gate signal output units SU [1] to SU [ n ] respectively receives the compensation voltages Vc [1] to Vc [ n ] generated by the voltage compensation circuit 1320, so that each of the gate signal output units 1310 correspondingly outputs the gate signals sel [1] to sel [ n ], thereby controlling the gate voltages Vg _ off of the TFTs in each of the pixel units of the display panel to be close at the moment of turning off, ensuring that the common voltage Vcom of each of the pixel units in the display panel can tend to be stable, and improving the performance of the liquid crystal display device.

In the above analysis, it is possible to obtain: Δ Vgho_ff＝[(VdH+VdL)/2-ΔVcom](Cp + Cst + Clc)/Cp + VselL, that is, the compensation voltage Vc [1] can be selected according to the analysis of the linear variation of the voltage of the common voltage Vcom]To Vc [ n ]]。

The voltage compensation circuit 1320 may be implemented by a resistance divider circuit as shown in fig. 8. The voltage compensation circuit comprises a plurality of resistors R [1] to R [ mid +1] which are connected in series, one end of the resistor R [1] receives a reference voltage Vrefh, the other end of the resistor R [2] is connected in series, one end of the resistor R [ min +1] is grounded, the other end of the resistor R [ min +1] is connected in series with the resistor R [ mid ], and a node between every two resistors connected in series is respectively connected with output ports of the compensation voltages Vc [1] to Vc [ n ] through a lead-out resistor (when n is an odd number, mid1 is (n +1)/2, and when n is an even number, mid is n/2). Since in this embodiment, in order to make the common voltage Vcom on the common electrode in each row of pixel units in the display panel substantially equal, the voltage compensation circuit 1320 is required to output linearly varying compensation voltages Vc [1] to Vcn ], according to the above analysis, the compensation voltages Vc [1] and Vcn are the largest, and the compensation voltage Vc corresponding to the scan line closer to the horizontal central axis of the display panel is smaller. Therefore, the ports of output compensation voltages Vc 1 and Vcn are connected with the node between the resistors R1 and R2 through the leading-out resistor, the ports of output compensation voltages Vc 2 and Vcn-1 are connected with the node between the resistors R2 and R3 through the leading-out resistor, and so on, the ports of output compensation voltages Vcmin or Vcmin and Vcmid +1 are connected with the node between the resistor R n and the resistor R n +1 through the leading-out resistor, so that the compensation voltages Vc 1 and Vcn output by the voltage compensation circuit 1320 are the maximum, and the compensation voltage Vc corresponding to the scanning line closer to the transverse central axis of the display panel is the smaller.

Fig. 9 is a schematic waveform diagram showing high-level voltage distributions of gate signals corresponding to different rows of pixel units according to the first embodiment of the present invention. Fig. 10 is a schematic diagram illustrating a distribution of a common voltage difference between adjacent rows of pixel units in a display panel in a liquid crystal display device according to a first embodiment of the invention.

As shown in FIG. 9, the gate driver 1300 outputs the gate signals sel [1] to sel [ n ] through the scan lines G [1] to G [ n ], respectively, and since the high level voltages VselH [1] to VselH [ n ] of the gate signals sel [1] to sel [ n ] are equal to the compensation voltages Vc [1] to Vc [ n ] generated by the voltage compensation circuit 1320, the high level voltage VselH [1] of the gate signal sel [1] and the high level voltage VselH [ n ] of the gate signal sel [ n ] are the highest, and the high level voltage VselH of the gate signal sel corresponding to the scan line closer to the horizontal axis of the display panel is the lower. This is because the scan lines G [1] and G [ n ] have the longest length, and thus the falling response time of the gate voltages Vg [1] and Vg [ n ] of the TFTs in the pixel units corresponding to the scan lines G [1], G [ n ] is the longest, and therefore the high level voltages of the gate signals sel [1], sel [ n ] corresponding to the scan lines G [1], G [ n ] are set to be the highest to relatively shorten the falling response time of the gate voltages; the falling response time of the gate voltage of the TFT in the pixel unit corresponding to the scanning line closer to the horizontal axis of the display panel is shorter, and the high level voltage of the corresponding gate signal sel is lower to relatively increase the falling response time of the gate voltage, so that the gate voltages Vg _ off of the TFTs [1y ] to TFT [ ny ] (arranged from top to bottom) distributed in each row in the display panel at the turn-off moment are substantially the same, that is, the common voltage Vcom on the common electrode of the pixel units in each row in the display panel is substantially the same. As shown in fig. 10, compared with the waveform of the common voltage difference Δ Vcom (in the range of about 70mV to about 85mV) of the adjacent row of pixel units of the display panel in the conventional lcd device, the lcd device according to the first embodiment of the present invention compensates the high level voltage of the gate signal, so that the common voltage difference Δ Vcom of the adjacent row of pixel units is significantly reduced (in the range of about 10mV to about 20 mV).

As shown in fig. 11, when the timing control signal ctl received by the gate signal output unit is at a high level, the level conversion circuit in the gate signal output unit converts the first preliminary signal into the second preliminary signal according to the corresponding compensation voltage Vc (selected from one of Vc [1] to Vc [ n ]) and outputs the second preliminary signal to the output buffer circuit, so that the high-level voltage vsell of the gate signal sel output by the output buffer circuit is equal to the compensation voltage Vc, thereby compensating for linear variation of the common voltage Vcom of the pixel units distributed at different positions in the display panel by setting the high-level voltage vsell.

In the above embodiment, the high level voltages VselH [1] VselH [ n ] of the gate signals sel [1] sel [ n ] received by each of the scan lines G [1] G [ n ] respectively correspond to one of the compensation voltages Vc [1] Vc [ n ]. Since a display panel usually includes many rows of pixel units, as an alternative embodiment, every k scan lines (k is a natural number greater than 1) corresponds to a same compensation voltage Vc.

For example, every two strobe signal output units correspond to the same timing control signal ctl and compensation voltage Vc. As shown in FIG. 12, the gate signal output units SU [2] and SU [1] receive the same compensation voltage Vc [1] and timing control signal ctl, thereby respectively outputting gate signals sel [2] and sel [1] that are not overlapped and have the same high level voltage, the gate signal output units SU [4] and SU [3] receive the same compensation voltage Vc [2] and timing control signal ctl, thereby respectively outputting gate signals sel [4] and sel [3] that are not overlapped and have the same high level voltage, and so on.

According to the liquid crystal display device of the first embodiment of the invention, on the premise of not depending on the process, the compensation of the common voltage on the common electrode in each row of pixel units is realized by providing the gate signals with different high-level voltages to the pixel units distributed in different rows, so that the values of the common voltage on the common electrode in each row of pixel units are consistent within the allowable range of errors, the common voltage is prevented from changing along with the difference of the distribution positions of the pixel units, the display uniformity of the liquid crystal display device is improved, and the display quality is improved.

As shown in fig. 13, the conventional liquid crystal display device 2000 integrated with a gate driving structure includes a driving circuit 2100 and a display panel 2200. The driving circuit 2100 supplies a gray scale voltage Vgam to the display panel 2200 through a plurality of data lines D [1] to D [ m ] and supplies gate clock signals sclk [1] to sclk [ n ] to the display panel 2200 through a plurality of clock lines C [1] to C [ n ]. Wherein m and n are natural numbers of 1 or more. The driving circuit 2100 includes a voltage compensation circuit 2120 that generates compensation voltages Vc [1] to Vc [ n ] corresponding to the gate clock signals sclk [1] to sclk [ n ] according to a reference voltage Vrefh.

The display panel 2200 includes a plurality of Gate Driver in Array (GIA) GIA [1] to GIA [ n ] and a plurality of pixel cells 2210 arranged in a matrix of n rows and m columns. Each pixel cell 2210 includes a thin film transistor (one of TFT [11] to TFT [ nm ]), a pixel electrode 2212, the drain of which is connected to the pixel electrode 2212, and a common electrode, which is located below and isolated from the pixel electrode to form a pixel capacitance. The gates of the TFTs included in the pixel cells located in the same row are connected to each other and to a corresponding integrated gate driver circuit, and the sources of the TFTs included in the pixel cells located in the same column are connected to each other and to a data line (selected from one of D1 to D m) outside the display panel. The integrated gate driving circuits GIA [1] to GIA [ n ] respectively acquire the gate clock signals sclk [1] to sclk [ n ] from the driving circuit 2100 through the clock lines C [1] to C [ n ].

Fig. 13 shows only the wiring between part of the driving circuit 2100 and each integrated gate driving circuit.

As shown in fig. 14, each row of pixel units connected to each integrated gate driving circuit in the display panel is abstracted into a series connection of an equivalent resistor Rgate and an equivalent capacitor Cgate, where the series connection of the equivalent resistor Rgate and the equivalent capacitor Cgate has one end grounded and the other end connected to a corresponding integrated gate driving circuit. The integrated gate driving circuits GIA [1] to GIA [ n ] and the pixel units in the corresponding row in the display panel 2200 are sequentially arranged from top to bottom (the integrated gate driving circuits GIA [1] to GIA [ n ] may be located on the same side of the display panel, or alternatively located on two opposite sides of the display panel in the transverse direction), when the driving circuit 2100 is located below the plane of the display panel and on the extension line of the longitudinal central axis of the display panel, the integrated gate driving circuits GIA [1] to GIA [ n ] are gradually approached to the driving circuit 2100, i.e. the lengths of the clock lines C [1] to C [ n ] are sequentially decreased. Therefore, the resistance values and capacitance values on the clock lines C [1] to C [ n ] are sequentially decreased, that is, the response times of the integrated gate driving circuits GIA [1] to GIA [ n ] receiving the gate clock signals sclk [1] to sclk [ n ] are sequentially decreased, so that the response times of the gate signals sel [1] to sel [ n ] output by the integrated gate driving circuits GIA [1] to GIA [ n ] are sequentially decreased, so that the response times of the gate voltages Vg [1] to Vg [ n ] of the TFTs in the pixel units of the corresponding row are sequentially decreased, the error feed-throughs Vp [1] to Vp [ n ] of the pixel electrode voltages in the pixel units of the corresponding row are sequentially increased, and the common voltages Vcom [1] to Vcom [ n ] of the common electrodes in the pixel units of the corresponding row are sequentially decreased.

Fig. 15 is a schematic diagram illustrating the distribution of common voltage values on the common electrode in pixel units located at different positions of the display panel in the conventional liquid crystal display device with integrated gate driving structure. In the liquid crystal display device with integrated gate driving structure shown in fig. 15, the pixel units in each row of the display panel are respectively connected to the GIAs at two ends of the pixel unit row, so as to form a double-end opposite-punch GIA structure.

As shown in fig. 15, since the length of the clock line is shorter closer to the drive circuit 2100, the feed-through error Vp of the pixel electrode in the pixel unit closer to the drive circuit 2100 is larger, and the feed-through error Vp of the pixel electrode in the pixel unit farther from the drive circuit 2100 is smaller. As can be seen from the values of (Vgh _ off-VselL) · Cp/(Cp + Cst + Clc) and (VdH + VdH)/2-Vp, the common voltage Vcom of the common electrode in the pixel cell closer to the driving circuit 2100 is smaller, and the common voltage Vcom of the common electrode in the pixel cell farther from the driving circuit 2100 is larger.

For each row of pixel cells in the display panel, the shorter the length of the conductive line between the gate of the thin film transistor in the pixel cell closer to the GIA (the farther the thin film transistor in the TFT [ xm ] to TFT [ x1] closer to the central axis in the longitudinal direction of the display panel is from the GIA), and the shorter the common voltage Vcom on the common electrode in the pixel cell closer to the GIA in each row of pixel cells.

As shown in fig. 16, the common voltage in each pixel unit in each row of pixel units is averaged to obtain the row average common voltage avg. Since the feedthrough error of the pixel electrode voltage in the pixel cell closer to the drive circuit 2100 is larger and the feedthrough error Vp of the pixel electrode voltage in the pixel cell farther from the drive circuit 2100 is smaller, the row average common voltage avg.vcom closer to the drive circuit 2100 is smaller and the row average common voltage avg.vcom farther from the drive circuit 2100 is larger. It can be seen that the average row common voltage avg.vcom corresponding to each row of pixel units in the display panel is linearly distributed.

As can be seen from the feed-through error Vp being (Vgh _ off-VselL) · Cp/(Cp + Cst + Clc) and Vcom being (VdH + VdH)/2-Vp, the common voltage Vcom varies linearly with the feed-through error Vp, and the feed-through error Vp varies linearly with the gate voltage Vg _ off of the TFT at the turn-off instant.

Because the length of the clock line C [1] is longest, the response time of the gate voltage Vg [1] of the TFT in the pixel unit corresponding to the clock line C [1] is longest, and the gate voltage Vg _ off of the TFT corresponding to the clock line C [1] at the moment of turning off is smaller; the response time of the gate voltage of the TFT in the pixel unit closer to the driving circuit is shorter, and the gate voltage Vg _ off of the TFT at the moment of turning off is larger.

The second embodiment of the present invention implements compensation of the common voltage Vcom by adjusting the high level voltages VsclkH [1] to VsclkH [ n ] of the gate clock signals sclk [1] to sclk [ n ], so that Vcom approaches to be stable.

The block diagram structure of the LCD device of the second embodiment of the present invention is the same as that of the conventional LCD device shown in FIG. 13, that is, it includes a driving circuit and a display panel, the driving circuit provides the gray scale voltage Vgam for the display panel through a plurality of data lines D [1] to D [ m ], and provides the gate clock signals sclk [1] to sclk [ n ] for the display panel through a plurality of clock lines C [1] to C [ n ]. Wherein m and n are natural numbers of 1 or more. The driving circuit includes a voltage compensation circuit 2120 that generates a plurality of compensation voltages Vc [1] to Vc [ n ] corresponding to the gate clock signals sclk [1] to sclk [ n ] according to a reference voltage Vrefh.

It should be noted that, in this embodiment, the number of the integrated gate driving circuits is equal to the number of rows of the pixel units in the display panel, in an alternative embodiment, one integrated gate driving circuit may correspond to multiple rows of the pixel units, or to improve the driving capability, multiple integrated gate driving circuits may correspond to the same row of the pixel units, that is, the number of the integrated gate driving circuits may be greater than or less than the number of rows of the pixel units in the display panel.

The voltage compensation circuit 2120 may be implemented by a resistance voltage division circuit as shown in fig. 17. The voltage compensation circuit 2120 includes a plurality of resistors R1 to R n +1 connected in series, one end of the resistor R1 receives a reference voltage Vrefh, the other end is connected in series with a resistor R2, one end of the resistor R n +1 is grounded, the other end is connected in series with the resistor R n, and a node between every two resistors connected in series is connected with output ports of the compensation voltages Vc 1 to Vc n through lead-out resistors respectively. Since in this embodiment, in order to make the common voltage Vcom on the common electrode in each row of pixel cells in the display panel substantially equal, it is necessary for the voltage compensation circuit 2120 to output linearly varying compensation voltages Vc [1] to Vcn ], according to the above analysis, the compensation voltages Vc 1 to Vc n are sequentially reduced, so that the port outputting the compensation voltage Vc 1 is connected to the node between the resistors R1 and R2 through the lead-out resistor, the port outputting the compensation voltage Vc 2 is connected to the node between the resistors R2 and R3 through the lead-out resistor, by analogy, the port of output compensation voltage Vc n is connected with the node between the resistance R n and the resistance R n +1 through the leading-out resistance, so that the compensation voltages Vc [1] to Vc [ n ] output by the voltage compensation circuit 2120 are reduced in sequence.

Fig. 18 is a schematic waveform diagram showing a high-level voltage distribution of gate signals corresponding to different rows of pixel units according to the second embodiment of the present invention. Fig. 19 is a schematic diagram illustrating a distribution of a common voltage difference between adjacent rows of pixel units in a display panel in a liquid crystal display device according to a second embodiment of the invention.

As shown in fig. 18, the driving circuit 2100 outputs a plurality of gate clock signals gate _ clk having different high level voltages, and the integrated gate driving circuits GIA [1] to GIA [ n ] respectively intercept the gate clock signals sclk [1] to sclk [ n ] (the high level voltages VsclkH [1] to VsclkH [ n ] of the gate clock signals sclk [1] to sclk [ n ] are respectively equal to the compensation voltages Vc [1] to Vc [ n ]), so that the integrated gate driving circuits GIA [1] to GIA [ n ] respectively output the high level voltages VselH [1] to VselH [ n ] of the gate signals sel [1] to sel [ n ] to the gates of the TFTs in the pixel cells of the corresponding row are respectively equal to the compensation voltages Vc [1] to Vc [ n ]. The integrated gate driving circuits closer to the driving circuit 2100 receive the lower the high level voltage VsclkH of the gate clock signal sclk, i.e., the sequentially decreasing high level voltages VsclkH [1] to VsclkH [ n ] of the gate clock signals sclk [1] to sclk [ n ] output by the driving circuit 2100 corresponding to the respective integrated gate driving circuits GIA [1] to GIA [ n ], such that the integrated gate driving circuits GIA [1] to GIA [ n ] sequentially decrease the high level voltages VselH [1] to VselH [ n ] of the gate signals sel [1] to sel [ n ] output by the respective rows of pixel cells to sequentially increase the response time of the gate voltages of the TFTs in the respective rows of pixel cells from top to bottom, such that the gate voltage Vg of the TFTs distributed at respective positions in the display panel at the moment of turn-off is substantially the same. As shown in fig. 19, compared with the waveform of the common voltage difference Δ Vcom (in the range of about 40mV to about 85mV) of the adjacent row of pixel units of the display panel in the conventional lcd device, the lcd device according to the second embodiment of the present invention compensates the high level voltage of the gate signal, so that the common voltage difference Δ Vcom of the adjacent row of pixel units is significantly reduced (in the range of about 15mV to about 35 mV).

As shown in fig. 20, when the timing control signal ctl received by the integrated gate driving circuit is at a high level, the integrated gate driving circuit intercepts a corresponding gate clock signal sclk from the gate clock signal, and outputs a gate signal sel according to the gate clock signal sclk.

For example, the integrated gate drive circuit GIA [2] connected to the clock line C [2] intercepts, from among the plurality of gate clock signals gate _ clk outputted from the drive circuit 2100, the high level voltage VsclkH [2] of the gate clock signal sclk [2] which is smaller than the high level voltage VsclkH [1] of the gate clock signal sclk [1] intercepted from among the plurality of gate clock signals gate _ clk outputted from the drive circuit 2100 by the integrated gate drive circuit GIA [1] connected to the clock line C [1], i.e., the high level voltage VselH [2] of the gate signal sel [2] outputted from the integrated gate drive circuit GIA [2] is lower than the high level voltage VselH [1] of the gate signal sel [1] outputted from the integrated gate drive circuit GIA [1], so that the TFTs in the row of pixel cells connected to the integrated gate drive circuit GIA [2] in the display panel are turned off at the moment in which the gate voltages of the rows of the gate cells correspond to about one row of the gate drive circuits GIA [1] in the display panel The gate voltage Vg _ off of the TFT at the moment of turn-off is the same. According to Vp ═ Vgh _ off-VselL) · Cp/(Cp + Cst + Clc) and Vcom ═ VdH +

VdL)/2-Vp shows that the feed-through errors of the pixel electrode voltages in the pixel units corresponding to the integrated gate driving circuits GIA [1] and GIA [2] are substantially the same, and thus the common voltage Vcom is substantially the same. The feed-through error of the pixel electrode voltage in other pixel units and the common voltage Vcom are substantially the same, and the principle is as described above, and will not be described herein again.

In the above embodiment, the high level voltages VselH [1] VselH [ n ] of sel [1] sel [ n ] output by the integrated gate driving circuits GIA [1] GIA [ n ] respectively correspond to one of the compensation voltages Vc [1] Vc [ n ]. Since a display panel usually includes many rows of pixel units, as an alternative embodiment, every k scan lines (k is a natural number greater than 1) corresponds to a same compensation voltage Vc.

For example, every two integrated gate driving circuits correspond to the same timing control signal ctl and compensation voltage Vc. As shown in FIG. 20, the integrated gate driving circuits GIA [1] and GIA [2] respectively output the gate signals sel [1] and sel [2] which are not overlapped and have the same high level voltage according to the same timing control signal ctl, the integrated gate driving circuits GIA [3] and GIA [4] respectively output the gate signals sel [3] and sel [4] which are not overlapped and have the same high level voltage according to the same timing control signal ctl, and so on.

According to the liquid crystal display device with the integrated gate drive structure provided by the second embodiment of the invention, on the premise of not depending on a process, the compensation of the common voltage on the common electrode in each row of pixel units is realized by providing the gate signals with different high-level voltages to the pixel units distributed in different rows, so that the values of the common voltage on the common electrode in each row of pixel units are consistent within an error allowable range, the common voltage is prevented from changing along with the difference of the distribution positions of the pixel units, the display uniformity of the liquid crystal display device is improved, and the display quality is improved.

Fig. 22 is a basic flowchart showing a driving method of a liquid crystal display device according to a third embodiment of the present invention. The method includes steps S01 to S04.

In step S01, gray scale voltages are output for each row of pixel cells.

In step S02, the pixel cells in the display panel are divided into a plurality of groups.

The liquid crystal display device includes a display panel including a plurality of pixel units arranged in n rows and m columns, n and m being non-zero natural numbers, and a driving circuit. The pixel units of n rows in the display panel are divided into a plurality of groups, each group of pixel units comprises k adjacent rows of pixel units, k is a non-zero natural number, the value of k is not too large, and otherwise the accuracy of public voltage correction is affected.

In step S03, a plurality of compensation voltages respectively corresponding to the respective pixel cell groups are generated. The voltage value of the compensation voltage corresponding to the pixel cell group having the longer signal transmission distance from the driving circuit is larger.

In step S04, gate signals are output to the pixel units in each row according to the compensation voltages, so that the pixel units in each row output the gate signals, and the high-level voltages of the gate signals corresponding to the pixel units in each row are respectively equal to the compensation voltages, so that the common voltage values of the pixel units in each row are kept consistent within the error tolerance range.

According to the driving method for the liquid crystal display device in the third embodiment of the present invention, on the premise of not depending on the process, the compensation of the common voltage on the common electrode in each row of pixel units is realized by providing the gate signals with different high-level voltages to the pixel units distributed in different rows, so that the values of the common voltage on the common electrode in each row of pixel units are consistent within the range of error allowance, the common voltage is prevented from changing with the difference of the distribution positions of the pixel units, the display uniformity of the liquid crystal display device is improved, and the display quality is improved.

In this specification, "horizontal direction" refers to a row direction of the display panel, that is, an arrangement direction of each pixel unit where the TFTs connected to the gate electrode are located in a plane of the display panel; "longitudinal" refers to the column direction of the display panel, i.e., the direction of arrangement of each pixel cell in which the source-connected TFTs are located in the plane of the display panel. "below" refers to a position that is at a vertical distance from the plane of the pixel electrode.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A liquid crystal display device comprising:

the display panel comprises a plurality of pixel units which are arranged into an n-row m-column matrix, each pixel unit comprises a thin film transistor, a pixel electrode connected with the output end of the thin film transistor and a common electrode which is positioned below the pixel electrode and is isolated from the pixel electrode, the pixel units in the same row receive the same gray scale voltage, the pixel units in the same row receive the same gating signal, and n and m are non-zero natural numbers;

the display panel further comprises a plurality of integrated gate driving circuits which are respectively connected with the pixel units in each row, wherein each integrated gate driving circuit respectively receives the corresponding clock signal through a clock line connected with the driving circuit and generates the gating signal according to the clock signal, so that the high level voltage of the gating signal corresponding to the pixel units in each row is respectively equal to the plurality of compensation voltages, and the common voltage value on the common electrode in the pixel units in each row is kept consistent within an error allowable range.

2. The liquid crystal display device according to claim 1, wherein n rows of the pixel units are divided into a plurality of groups, each pixel unit group containing k adjacent rows of the pixel units, k being a non-zero natural number smaller than n,

the compensation voltages corresponding to the k rows of pixel units included in each pixel unit group are the same.

3. The liquid crystal display device according to claim 2, wherein the driving circuit includes a voltage compensation circuit including a resistance voltage division circuit for generating the plurality of compensation voltages from a reference voltage.

4. The liquid crystal display device according to claim 2, wherein the integrated gate driving circuits corresponding to the same pixel cell group have the same group, and the longer the sum of the clock lines is, the higher the voltage value of the compensation voltage corresponding to the integrated gate driving circuit group is.

5. The liquid crystal display device according to claim 1, wherein the error allowable range includes-10 mV to +10 mV.

6. A driving method for a liquid crystal display device, the liquid crystal display device including a display panel and a driving circuit, the display panel including a plurality of pixel units arranged in n rows and m columns and a plurality of integrated gate driving circuits respectively connected to the pixel units of the respective rows, n and m being non-zero natural numbers, the driving method comprising:

respectively outputting gray scale voltage to each row of pixel units;

generating a plurality of compensation voltages according to the distribution positions of the pixel units in each row;

the driving circuit generates a plurality of clock signals according to the plurality of compensation voltages, wherein the high-level voltages of the plurality of clock signals are respectively equal to the plurality of compensation voltages;

each integrated gate driving circuit receives the corresponding clock signal through a clock line connected with the driving circuit and outputs a corresponding gating signal to each row of the pixel units according to the clock signal,

the high-level voltages of the gating signals corresponding to the pixel units in each row are respectively equal to the compensation voltages, so that the common voltage values of the pixel units in each row are kept consistent within an error allowable range.

7. The driving method according to claim 6, wherein the step of generating a plurality of compensation voltages according to the distribution positions of the pixel units in each row comprises:

dividing n rows of pixel units in a display panel into a plurality of groups, wherein each group of pixel units comprises k adjacent rows of pixel units, and k is a non-zero natural number;

the compensation voltages are generated so as to correspond to the respective pixel cell groups, and the voltage value of the compensation voltage corresponding to the pixel cell group having a longer signal transmission distance from the drive circuit is larger.