CN111883083A - Grid driving circuit and display device - Google Patents
Grid driving circuit and display device Download PDFInfo
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- CN111883083A CN111883083A CN202010749857.9A CN202010749857A CN111883083A CN 111883083 A CN111883083 A CN 111883083A CN 202010749857 A CN202010749857 A CN 202010749857A CN 111883083 A CN111883083 A CN 111883083A
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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Abstract
The application discloses circuit board and display device includes: a compensation signal generator for outputting a compensation signal, wherein the compensation signal is a square wave signal with 2T as a period, and in one period, a first level lasts for T/2 time, a first second level lasts for T/2 +. DELTA.T time, and a second first level lasts for T/2-. DELTA.t time; the second level lasts for T/2 time; a shift trigger receiving the compensation signal and respectively generating a plurality of first gate driving signals and a plurality of second gate driving signals; driving the plurality of scanning lines to be sequentially opened in a group of two scanning lines in a non-sequential manner; correspondingly outputting the grid driving signals to an output buffer of each scanning line, and outputting the first grid driving signals to the scanning lines which are opened in each group; the second gate driving signal is output to a scan line that is turned on later in each group. The charging efficiency between rows with different polarities is compensated, and the display quality is improved.
Description
Technical Field
The application relates to the technical field of display, in particular to a gate driving circuit and a display device.
Background
The liquid crystal display device is driven by adjusting the applied signals, and a driving electric field is established according to the phase, the peak value, the frequency and the like of different signals, so that the effect of deflecting a display picture by liquid crystals is realized. The most common polarity inversion method is dot inversion, a gate driving circuit sequentially transmits gate driving signals to scanning lines on a display panel line by line from a first row to a last row to sequentially turn on switching elements of each row, and in order to match the inversion of pixel electrode signals, data signals are switched from positive polarity to negative polarity or from negative polarity to positive polarity at the moment of turning on the data signals, that is, for a dot inversion display panel consisting of n rows of pixels in a frame, the data signals of each row of data lines are switched between positive and negative polarities n times, which causes the problem that the conventional dot inversion driving method has uniform display but large power consumption. According to different display pictures, the two adjacent rows of scanning lines are likely to generate bright and dark stripes due to large voltage span.
How to avoid the phenomenon that the panel is easy to have stripe feeling when the charging time for switching to the next opposite-polarity row is insufficient or the charging is not saturated, and the quality of the display picture is improved, which becomes a problem of attention in the industry.
Disclosure of Invention
The application aims to provide a gate driving circuit and a display device so as to avoid stripes.
The application discloses a grid driving circuit which is connected with a plurality of scanning lines and comprises a compensation signal generator for outputting a compensation signal, wherein the compensation signal is a square wave signal taking 2T as a period, and in the period, a first level lasts for T/2 time, a first second level lasts for T/2 plus delta T time, and a second first level lasts for T/2-delta T time; the second level lasts for T/2 time; a shift trigger receiving the compensation signal and respectively generating a plurality of first gate driving signals and a plurality of second gate driving signals; the high level duration time of the first gate driving signal is T + Deltat, the high level duration time of the second gate driving signal is T-Deltat, and a plurality of scanning lines are driven to be sequentially opened in a group of two scanning lines; correspondingly outputting the gate driving signals to an output buffer of each scanning line, and outputting the first gate driving signals to the scanning lines which are opened in each group; the second gate driving signal is output to the scan line that is turned on later in each group.
Optionally, the compensation signal generator receives the first clock signal and the second clock signal, and outputs a compensation signal;
the first clock signal CKVi is a square wave signal taking T as a period, and in one period, a first level lasts for T/2 time, and a second level lasts for T/2 time;
the second clock signal is a square wave signal with 2T as one period, in one period, after the first second level lasts for T time, the first level lasts for DeltaT time, and the second level lasts for T-Deltat time again.
Optionally, the compensation signal generator includes a comparator, a positive pole of the comparator receives the first clock signal, a negative pole of the comparator receives the second clock signal, and the compensation signal is output by performing a comparison operation on the first clock signal and the second clock signal.
Optionally, the compensation signal generator includes an inverter and an adder, and the inverter receives the second clock signal and performs a non-operation, and then performs an or operation with the first clock signal through the adder to output the compensation signal.
Optionally, the first level is a high level; the second level is a low level;
the shift trigger is a rising edge trigger, and outputs a high level duration time T + [ delta ] T as a first gate drive signal in a period of 2T; and then, the shift trigger outputs a high level with the duration time T-delta T as a second grid driving signal.
Optionally, in the same frame, corresponding to the same data line, the polarities of the data driving signals of the pixels corresponding to the two adjacent rows of scanning lines are opposite;
in two adjacent groups of the scan lines, the output buffer outputs the first gate driving signal of the first group to a first one of the scan lines, outputs the second gate driving signal of the first group to a third one of the scan lines, outputs the first gate driving signal of the second group to a second one of the scan lines, and outputs the second gate driving signal of the second group to a fourth one of the scan lines.
Optionally, in the same frame of picture, corresponding to the same data line, in four adjacent rows of the scanning lines, the polarities of the data driving signals of the pixels corresponding to every two adjacent rows of the scanning lines are the same, and the polarities of the data driving signals of the pixels corresponding to the front and rear groups of the scanning lines are opposite;
in two adjacent groups of the scan lines, the output buffer outputs the first gate driving signal of the first group to the first scan line, outputs the second gate driving signal of the first group to the second scan line, outputs the first gate driving signal of the second group to the third scan line, and outputs the second gate driving signal of the second group to the fourth scan line.
The application also discloses a gate driving circuit, which comprises a compensation signal generator for receiving a first clock signal and a second clock signal, wherein the compensation signal generator comprises an inverter and an adder, the inverter receives the second clock signal and performs non-operation, and then performs OR operation with the first clock signal through the adder to output the compensation signal, the compensation signal is a square wave signal with 2T as a period, in one period, a first high level lasts for T/2 time, a first low level lasts for T/2 +. DELTA.T time, and a second high level lasts for T/2-. DELTA.t time; the second low level lasts for T/2 time; the shift trigger receives a compensation signal, is a rising edge trigger, and drives the scanning lines to be opened in a non-sequential manner by taking two scanning lines as a group; in a period of 2T time, the shift trigger firstly outputs a high level with duration of T plus Deltat as a first gate driving signal, and then outputs a high level with duration of T minus Deltat as a second gate driving signal; the output buffer corresponds to the same data line in the same frame of picture, and the polarities of the data driving signals of the pixels corresponding to the scanning lines in two adjacent rows are opposite; in two adjacent groups of the scanning lines which are opened, the output buffer outputs the first gate driving signal of the first group to a first scanning line, outputs the second gate driving signal of the first group to a third scanning line, outputs the first gate driving signal of the second group to a second scanning line, and outputs the second gate driving signal of the second group to a fourth scanning line; the first clock signal is a square wave signal taking T as a period, and in one period, the high level lasts for T/2 time and the low level lasts for T/2 time; the second clock signal is a square wave signal with 2T as a period, in one period, after the first low level lasts for T time, the high level lasts for DeltaT time, and the second low level lasts for T-Deltat time.
The application discloses a display device, which comprises the grid drive circuit, a display panel and a source drive circuit; in the same frame of picture, the grid driving circuit outputs grid driving signals corresponding to each scanning line one by one, and drives the scanning lines to be sequentially opened in a group of two scanning lines in a non-sequential manner; corresponding to the same data line, the polarities of the data driving signals of the pixels corresponding to the same group of scanning lines are the same; the polarities of the data driving signals of the pixels corresponding to the two groups of adjacent opened scanning lines are opposite; the high level duration time of the first grid driving signal is T +. DELTA.t, and the first grid driving signal is output to the scanning line which is opened in advance in each group; the high level duration time of the second grid driving signal is T-delta T, and the second grid driving signal is output to a scanning line which is opened later in each group; and driving the plurality of scanning lines to be sequentially opened in a group of two in sequence or in a non-sequence manner.
Optionally, the display device further includes a storage unit, which stores a preset compensation schedule; the compensation time table stores the time length information of delta t corresponding to G1 and G2; the G1 is an average gray scale value of a row of pixels corresponding to a scanning line opened later in the previous group, and the G2 is an average gray scale value of a row of pixels corresponding to a scanning line opened earlier in the current group; the gate driving circuit generates a plurality of first gate driving signals and a plurality of second gate driving signals according to the delta t values obtained corresponding to G1 and G2 in the memory cells respectively.
Compared with a dot inversion display panel formed by n rows of pixels, the scheme that data signals of each row of data lines are switched between positive and negative polarities for n times and power consumption is increased is characterized in that two scanning lines which are taken as a group are sequentially or non-sequentially turned on, power consumption is reduced, and a shift trigger receives a first clock signal and a second clock signal to respectively generate a plurality of first grid driving signals and a plurality of second grid driving signals; the high level duration time of the first gate driving signal is T +. DELTA.t, and the high level duration time of the second gate driving signal is T-. DELTA.t; during charging, regardless of a sequential or non-sequential mode, the first gate driving signal delays for delta t time, and the second gate driving signal reduces for delta t time, so that the charging efficiency in the same time is avoided to be low, the charging efficiency between lines with different polarities is compensated, the charging time for switching to the next line with opposite polarity is insufficient or unsaturated, the phenomenon that stripe feeling is easy to occur due to large voltage across is avoided, the charging time between each group of scanning lines is balanced, and the quality of a display picture is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
fig. 1 is a schematic diagram of a display device according to an embodiment of the present application;
FIG. 2 is a schematic illustration of the polarity of an embodiment of the present application;
FIG. 3 is a schematic diagram of a gate driving circuit according to an embodiment of the present application;
FIG. 4 is a gate driving circuit diagram according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a compensation signal generator according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a compensation signal generator according to another embodiment of the present application;
FIG. 7 is a schematic illustration of the polarity of another embodiment of the present application;
FIG. 8 is a schematic diagram of a gate driver circuit according to another embodiment of the present application;
FIG. 9 is a schematic diagram of a compensation schedule of an embodiment of the present application;
fig. 10 is a schematic diagram of a source driver circuit according to another embodiment of the present application.
100. A gate drive circuit; 110. a compensation signal generator; 111. a comparator; 112. an inverter; 113. an adder; 130. a shift trigger; 140. an output buffer; 150. scanning a line; 180. a display device; 181. a display panel; 182. a source driver circuit; 183. and a data line.
Detailed Description
It is to be understood that the terminology, the specific structural and functional details disclosed herein are for the purpose of describing particular embodiments only, and are representative, but that the present application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or as implicitly indicating the number of technical features indicated. Thus, unless otherwise specified, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "plurality" means two or more. The terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that one or more other features, integers, steps, operations, elements, components, and/or combinations thereof may be present or added.
Further, terms of orientation or positional relationship indicated by "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are described based on the orientation or relative positional relationship shown in the drawings, are simply for convenience of description of the present application, and do not indicate that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.
Furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly and may include, for example, fixed connections, removable connections, and integral connections; can be mechanically or electrically connected; either directly or indirectly through intervening media, or through both elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
The application is further described with reference to the drawings and alternative embodiments.
As shown in fig. 1 and 2, as an embodiment of the present application, a display device 180 is disclosed, which includes a display panel 181, a gate driving circuit 100 outputting a gate driving signal, and a source driving circuit 182 outputting a data driving signal to drive the display panel 181.
In the same frame of picture, the gate driving circuit 100 outputs gate driving signals corresponding to each scanning line one by one, and drives the scanning lines to be sequentially opened in a group of two scanning lines in a non-sequential manner; corresponding to the same data line, the polarities of the data driving signals of the pixels corresponding to the same group of scanning lines are the same; the polarities of the data driving signals of the pixels corresponding to the two groups of adjacently opened scanning lines are opposite. The high level duration time of the first grid driving signal is T +. DELTA.t, and the first grid driving signal is output to the scanning line which is opened in advance in each group; the high level duration time of the second grid driving signal is T-delta T, and the second grid driving signal is output to a scanning line which is opened later in each group; the scanning lines are driven to be sequentially opened in a group of two scanning lines or in a non-sequential manner, so that the image quality is improved.
Correspondingly, as shown in fig. 3 and 4, the gate driving circuit 100 includes a compensation signal generator 110 for outputting a compensation signal CKVo, a shift flip-flop 130 for receiving the compensation signal CKVo, and an output buffer 140 for correspondingly outputting the gate driving signal to each scan line. The compensation signal CKVo is a square wave signal with 2T as a period, and in one period, a first level lasts for T/2 time, a first second level lasts for T/2 +. DELTA.T time, and a second first level lasts for T/2-DELTA.t time; the second level lasts for T/2 time. The shift flip-flop 130 receiving the compensation signal CKVo generates a plurality of first gate driving signals and a plurality of second gate driving signals, respectively; the high level duration time of the first gate driving signal is T + Deltat, and the plurality of scanning lines are driven to be sequentially opened in a non-sequential manner by taking two scanning lines as a group. The first gate driving signal is output to a scanning line which is opened in advance in each group; the second gate driving signal is output to a scan line that is turned on later in each group, where the first level is a high level and the second level is a low level. Of course, the first level may be a low level, and the second level may be a high level.
The scanning lines are driven to be sequentially opened in a group of two scanning lines in a non-sequential mode; corresponding to the same data line, the polarities of the data driving signals of the pixels corresponding to the same group of scanning lines are the same; the polarities of the data driving signals of the pixels corresponding to the two groups of adjacently opened scanning lines are opposite; because the voltage across the data driving signal corresponding to each group of scanning lines which are opened first is larger, and the voltage across the data driving signal corresponding to each group of scanning lines which are opened later is smaller, the condition of insufficient charging corresponding to each group of scanning lines which are opened first is more obvious. The shift flip-flop 130 receives the first clock signal CKVi and the second clock signal y to generate a plurality of first gate driving signals and a plurality of second gate driving signals, respectively; the high level duration time of the first gate driving signal is T +. DELTA.t, and the high level duration time of the second gate driving signal is T-. DELTA.t; during charging, regardless of a sequential or non-sequential mode, the first gate driving signal is delayed by the time delta t, and the second gate driving signal is reduced by the time delta t, so that the time of the scanning lines which are firstly opened in each group is prolonged, the opening time of the scanning lines which are firstly opened is increased by the initial time difference delta t, the charging degrees of the two rows of the scanning lines in each group are closer, and bright and dark stripes of a display panel are reduced, so that the display effect is improved. It should be noted that, the first gate driving signal and the second gate driving signal are generated by the gate driving chip and synchronously output to each scanning line, and the steps are not separated in sequence.
Taking the display panel in the dot inversion mode as an example, the polarities of the data driving signals corresponding to every two rows of scanning lines of the display panel are opposite, specifically, if four adjacent scanning lines are taken as an example, the gate driving signals of the 4n +1 th and 4n +3 th rows are a group, and the gate driving signals of the 4n +2 th and 4n +4 th rows are a group; therefore, the gate driving signals of the 4n +1 th and 4n +2 th rows are the first gate driving signals, and the gate driving signals of the 4n +3 th and 4n +4 th rows are the second gate driving signals.
In the present application, the initial time difference Δ t is added to the first gate driving signal, i.e., the gate driving signals of the 4n +1 th and 4n +2 th rows, and the initial time difference Δ t is subtracted from the second gate driving signal, i.e., the gate driving signals of the 4n +3 th and 4n +4 th rows. The high level duration time of the first gate driving signal is T +. DELTA.t, because the first gate driving signal charges all groups of scanning lines which are opened first, the duration time of the high level of the first gate driving signal needs to be prolonged to ensure that enough time is available for charging when the voltage across the data driving signal is large, and the second gate driving signal charges all scanning lines which are opened later, and the polarity of the pixel electrode corresponding to the scanning line which is opened later is the same as that of the pixel electrode corresponding to the scanning line which is arranged on the previous row, so that the voltage across the data driving signal corresponding to the scanning line which is opened later is small, the charging efficiency is fast, and therefore the high level duration time of the second gate driving signal does not need to increase. DELTA.t, so that the charging degree of the two rows of scanning lines in each group is closer, and the bright and dark stripes of the display panel are reduced to improve the display effect.
Specifically, the compensation signal generator 110 receives the first clock signal CKVi and the second clock signal y, and outputs the compensation signal CKVo; the first clock signal CKVi is a square wave signal taking T as a period, and in one period, high level lasts for T/2 time, and low level lasts for T/2 time; the second clock signal y is a square wave signal with 2T as one period, in one period, after the first low level lasts for T time, the high level lasts for T time, and the second low level lasts for T- Δ T time. The compensation signal CKVo is output by the compensation signal generator 110 through the first clock signal CKVi and the second clock signal y, and the compensation signal CKVo can be generated only by providing a superposition of the second clock signal y and the first clock signal CKVi, so that the method is simpler.
As shown in fig. 5, the compensation signal generator 110 includes an inverter 112 and an adder 113, and the inverter 112 receives the second clock signal y and performs a non-operation, and then performs an or operation with the first clock signal CKVi through the adder 113 to output the compensation signal CKVo. The second clock signal y is not operated through the inverter 112, the output signal after the operation is then subjected to or operation with the first clock signal CKVi, and the waveform signal superposed and output by the two clock signals after the two operations is the required compensation signal CKVo, so that the signal acquisition is rapid, simple and convenient.
Further, the shift flip-flop 130 is a rising edge flip-flop, a rising edge of the compensation signal CKVo is aligned with a rising edge of the first gate driving signal, and in a period of 2T time, the shift flip-flop 130 outputs a high level with a duration of T + Δt as the first gate driving signal; and then, the shift trigger outputs a high level with the duration time T-delta T as a second grid driving signal. When the compensation signal CKVo is turned on, the first gate driving signal is correspondingly turned on, when the compensation signal CKVo is turned off for the first time, the first gate driving signal is kept at a high level and is turned on for the total time of T plus delta T, when the compensation signal CKVo is turned on for the second time, the first gate driving signal is turned off, meanwhile, the second gate driving signal is turned on, when the compensation signal CKVo is turned off for the second time, the second gate driving signal is kept at a high level and is turned on for the total time of T minus delta T, the charging time of the first gate driving signal is delayed by delta T, the low charging efficiency in the same time is avoided, and the charging efficiency among lines with different polarities is compensated.
Further, the output buffer 140 outputs the first gate driving signal of the first group to the first scanning line 150, the second gate driving signal of the first group to the third scanning line 150, the first gate driving signal of the second group to the second scanning line 150, and the second gate driving signal of the second group to the fourth scanning line 150. Specifically, in the case of scanning two groups of scan lines 150 that are opened adjacently, taking scanning four adjacent rows as an example (e.g., L1, L2, L3, and L4), scanning a pixel row may also be referred to as turning on the pixel row, and the non-sequential scanning mode scans each row not by row but by cross scanning, for example, first scanning L1, then scanning L3, then scanning L2, and finally scanning L4 according to the gate driving signal output by the output buffer 140.
Moreover, in order to obtain the required compensation signal CKVo, as shown in fig. 6, the compensation signal generator may also be a comparator 111, wherein an anode of the comparator 111 receives the first clock signal CKVi, a cathode of the comparator receives the second clock signal y, and the first clock signal CKVi and the second clock signal y are compared to output the compensation signal CKVo. Only one comparator 111 is needed to generate the compensation signal CKVo, and the method is relatively simple in elements and fast to implement.
As shown in fig. 7 and fig. 8, in the same frame, corresponding to the same data line, in the adjacent four rows of scan lines 150, the polarities of the data driving signals of the pixels corresponding to each two adjacent rows of scan lines 150 are the same, and the polarities of the data driving signals of the pixels corresponding to the front and rear two groups of scan lines 150 are opposite; in two adjacent groups of scan lines 150 that are opened, the output buffer 140 outputs the first gate driving signal of the first group to a first scan line 150, outputs the second gate driving signal of the first group to a second scan line 150, outputs the first gate driving signal of the second group to a third scan line 150, and outputs the second gate driving signal of the second group to a fourth scan line 150. Specifically, for example, in the two groups of scan lines 150 opened adjacently, scanning four rows (e.g., L1, L2, L3, and L4) is performed, and scanning a pixel row may also be referred to as turning on the pixel row, and scanning each row is performed line by line (i.e., from top to bottom), for example, first scanning L1, then scanning L2, then scanning L3, and finally scanning L4 according to the gate driving signal output by the output buffer 140.
As shown in fig. 2, 3, 4 and 5, as another embodiment of the present application, a gate driving circuit 100 is disclosed, which includes a compensation signal generator receiving a first clock signal CKVi and a second clock signal y, wherein the compensation signal generator 110 includes an inverter 112 and an adder 113, the inverter 112 receives the second clock signal y and performs a non-operation, and then performs an or operation with the first clock signal CKVi through the adder 113 to output a compensation signal CKVo, the compensation signal CKVo is a square wave signal with 2T as one cycle, and in one cycle, a first high level lasts for T/2 time, a first low level lasts for T/2 +/Δ time, and a second high level lasts for T/2- Δ T time; the second low level lasts for T/2 time; a shift flip-flop 130 receiving the compensation signal CKVo, wherein the shift flip-flop 130 is a rising edge flip-flop and drives the plurality of scan lines 150 to be sequentially turned on in a non-sequential manner with two scan lines as a group; in a period of 2T time, the shift trigger 130 outputs a high level duration T +. DELTA.t as a first gate driving signal, and then outputs a high level duration T-. DELTA.t as a second gate driving signal; an output buffer 140 corresponding to the same data line in the same frame, wherein the polarities of the data driving signals of the pixels corresponding to the two adjacent rows of scanning lines 150 are opposite; in two adjacent groups of scan lines 150 that are opened, the output buffer 140 outputs the first gate driving signal of the first group to a first scan line 150, outputs the second gate driving signal of the first group to a third scan line 150, outputs the first gate driving signal of the second group to a second scan line 150, and outputs the second gate driving signal of the second group to a fourth scan line 150; the first clock signal CKVi is a square wave signal taking T as a period, and in one period, high level lasts for T/2 time, and low level lasts for T/2 time; the second clock signal y is a square wave signal with 2T as one period, in one period, after the first low level lasts for T time, the high level lasts for T time, and the second low level lasts for T- Δ T time.
Even if the same scanning line is used, when the gray scale values of the data driving signals are different, the corresponding time length of delta t can be different, and specifically, the display device further comprises a storage unit for storing a preset compensation time table; the compensation time table stores the time length information of delta t corresponding to G1 and G2; the G1 is an average gray scale value of a row of pixels corresponding to a scanning line opened later in the previous group, and the G2 is an average gray scale value of a row of pixels corresponding to a scanning line opened earlier in the current group; the gate driving circuit generates a plurality of first gate driving signals and a plurality of second gate driving signals according to the delta t values obtained corresponding to G1 and G2 in the memory cells respectively.
With reference to fig. 9, the average gray-scale value G1 of a row of pixels corresponding to a scanning line opened later in the previous group of the current frame and the average gray-scale value G2 of a row of pixels corresponding to a scanning line opened earlier in the current group are obtained and calculated, and the Δ t time of the corresponding scanning line is obtained by searching a preset compensation time table with the obtained values of G1 and G2 as parameters. And obtaining the time delta t of the corresponding scanning line according to G1 and G2, and generating a first gate driving signal of the scanning line according to the time delta t so as to drive the display panel.
As shown in fig. 10, in the driving method of the display panel, it is necessary to generate the corresponding data driving signals SIC according to the Δ T such that the data driving signals continue for a time T + Δ T corresponding to the data voltage when the first gate driving signal is turned on and continue for a time T- Δ T corresponding to the data voltage when the second gate driving signal is turned on.
The generation of the corresponding data driving signal SIC according to said Δ t is realized by means of a data control signal TP. The data control signal TP is generated according to the Δ T, a period of the data control signal TP is 2T, in one period, a first falling edge of the data control signal TP corresponds to a time when the first gate driving signal is turned on, a time between the first falling edge and a second falling edge of the data control signal TP is T + Δt, and a time between the second falling edge of the data control signal TP and a first falling edge of a next period is T- Δ T.
Each falling edge of the data control signal TP corresponds to a rising edge of the compensation signal CKVo after the operation of the second clock signal y and the first clock signal CKVi, so that when the compensation signal scans each row of scanning lines, the continuous charging time of the data driving signal SIC on the row of scanning lines is synchronized, and the phenomenon that the display pixels are not fully charged due to the fact that the scanning time of the gate driving circuit and the charging time of the data driving circuit are not synchronized is prevented.
The source electrode driving circuit outputs a data driving signal SIC, and charges the pixel electrode on the corresponding scanning line when the corresponding scanning line is opened. The data voltage duration of the data driving signal SIC corresponding to the first gate driving signal is T +. DELTA.t, and the data voltage duration of the data driving signal SIC corresponding to the second gate driving signal is T-. DELTA.t regardless of whether the on-time of the second gate driving signal is 2T or T-. DELTA.t, because the gate driving signal corresponds to a switching signal for a corresponding scan line and the data driving signal SIC corresponds to a charging signal for a corresponding scan line, the data driving signal SIC and the gate driving signal need to be turned on together to charge the scan line.
The technical solution of the present application can be widely applied to various display panels, such as TN (Twisted Nematic) display panel, IPS (In-Plane Switching) display panel, VA (Vertical Alignment) display panel, MVA (Multi-Domain Vertical Alignment) display panel, and of course, other types of display panels, such as OLED (Organic Light-Emitting Diode) display panel, and the above solution can be applied.
The foregoing is a more detailed description of the present application in connection with specific alternative embodiments, and the present application is not intended to be limited to the specific embodiments shown. For those skilled in the art to which the present application pertains, several simple deductions or substitutions may be made without departing from the concept of the present application, and all should be considered as belonging to the protection scope of the present application.
Claims (10)
1. A gate driving circuit connected to a plurality of scan lines, the gate driving circuit comprising:
the compensation signal generator outputs a compensation signal, the compensation signal is a square wave signal with 2T as a period, and in one period, a first level lasts for T/2 time, a first second level lasts for T/2 plus delta T time, and a second first level lasts for T/2-delta T time; the second level lasts for T/2 time;
the shift trigger receives the compensation signal and respectively generates a plurality of first grid driving signals and a plurality of second grid driving signals; the high level duration time of the first gate driving signal is T + Deltat, the high level duration time of the second gate driving signal is T-Deltat, and a plurality of scanning lines are driven to be sequentially opened in a group of two scanning lines;
the output buffer correspondingly outputs the grid driving signals to all the scanning lines, and the first grid driving signals are output to the scanning lines which are opened in each group in advance; the second gate driving signal is output to the scan line that is turned on later in each group.
2. The gate driving circuit of claim 1, wherein the compensation signal generator receives a first clock signal and a second clock signal and outputs a compensation signal;
the first clock signal is a square wave signal with T as a period, and in one period, a first level lasts for T/2 time, and a second level lasts for T/2 time;
the second clock signal is a square wave signal with 2T as one period, in one period, after the first second level lasts for T time, the first level lasts for DeltaT time, and the second level lasts for T-Deltat time again.
3. The gate driving circuit of claim 2, wherein the compensation signal generator comprises a comparator, a positive pole of the comparator receives the first clock signal, a negative pole of the comparator receives the second clock signal, and the compensation signal is output by comparing the first clock signal and the second clock signal.
4. The gate driving circuit of claim 2, wherein the compensation signal generator comprises an inverter and an adder, and the inverter receives the second clock signal and performs a non-operation, and then performs an or operation with the first clock signal through the adder to output the compensation signal.
5. The gate drive circuit of claim 1, wherein the first level is a high level; the second level is a low level;
the shift trigger is a rising edge trigger, and outputs a high level duration time T + [ delta ] T as a first gate drive signal in a period of 2T; and then, the shift trigger outputs a high level with the duration time T-delta T as a second grid driving signal.
6. The gate driving circuit according to claim 1, wherein the polarities of the data driving signals of the pixels corresponding to two adjacent rows of the scan lines are opposite to each other corresponding to the same data line in the same frame;
in two adjacent groups of the scanning lines, the output buffer outputs the first gate driving signal of the first group to a first scanning line, outputs the second gate driving signal of the first group to a third scanning line, outputs the first gate driving signal of the second group to a second scanning line, and outputs the second gate driving signal of the second group to a fourth scanning line.
7. The gate driving circuit according to claim 1, wherein in the same frame, corresponding to the same data line, in four adjacent rows of the scanning lines, the polarities of the data driving signals of the pixels corresponding to every two adjacent rows of the scanning lines are the same, and the polarities of the data driving signals of the pixels corresponding to the front and rear groups of the scanning lines are opposite;
in two adjacent groups of the scanning lines, the output buffer outputs the first gate driving signal of the first group to a first scanning line, outputs the second gate driving signal of the first group to a second scanning line, outputs the first gate driving signal of the second group to a third scanning line, and outputs the second gate driving signal of the second group to a fourth scanning line.
8. A gate drive circuit, comprising:
the compensation signal generator receives a first clock signal and a second clock signal, comprises an inverter and an adder, receives the second clock signal, performs non-operation on the second clock signal, performs OR operation on the first clock signal through the adder, and outputs a compensation signal, wherein the compensation signal is a square wave signal with 2T as a period, and in one period, a first high level lasts for T/2 time, a first low level lasts for T/2 +. DELTA.T time, and a second high level lasts for T/2-. DELTA.T time; the second low level lasts for T/2 time;
the shift trigger receives a compensation signal, is a rising edge trigger and drives the scanning lines to be opened in a non-sequential manner by taking two scanning lines as a group; in a period of 2T time, the shift trigger firstly outputs a high level with duration of T plus Deltat as a first gate driving signal, and then outputs a high level with duration of T minus Deltat as a second gate driving signal;
the output buffer corresponds to the same data line in the same frame of picture, and the polarities of the data driving signals of the pixels corresponding to the scanning lines in two adjacent rows are opposite; in two adjacent groups of the scanning lines which are opened, the output buffer outputs a first grid driving signal of the first group to a first scanning line, outputs a second grid driving signal of the first group to a third scanning line, outputs a first grid driving signal of the second group to a second scanning line, and outputs a second grid driving signal of the second group to a fourth scanning line;
the first clock signal is a square wave signal taking T as a period, and in one period, the high level lasts for T/2 time and the low level lasts for T/2 time;
the second clock signal is a square wave signal with 2T as a period, in one period, after the first low level lasts for T time, the high level lasts for DeltaT time, and the second low level lasts for T-Deltat time.
9. A display device, comprising:
a display panel;
a gate drive circuit as claimed in any one of claims 1 to 9; and
the source electrode driving circuit outputs a data driving signal to drive the display panel;
in the same frame of picture, the grid driving circuit outputs grid driving signals corresponding to each scanning line one by one, and drives the scanning lines to be sequentially opened in a group of two scanning lines in a non-sequential manner; corresponding to the same data line, the polarities of the data driving signals of the pixels corresponding to the same group of scanning lines are the same; the polarities of the data driving signals of the pixels corresponding to the two groups of adjacent opened scanning lines are opposite;
the high level duration time of the first gate driving signal is T +. DELTA.t, and the first gate driving signal is output to the scanning line which is previously opened in each group; the high level duration time of the second grid driving signal is T-delta T, and the second grid driving signal is output to the scanning line which is opened later in each group; and driving a plurality of scanning lines to be sequentially opened in a group of two in a non-sequential manner.
10. The display device according to claim 9, wherein the display device further comprises a storage unit storing a preset compensation schedule; the compensation time table stores the time length information of delta t corresponding to G1 and G2;
the G1 is an average gray scale value of a row of pixels corresponding to a scanning line opened later in the previous group, and the G2 is an average gray scale value of a row of pixels corresponding to a scanning line opened earlier in the current group;
the gate driving circuit generates a plurality of first gate driving signals and a plurality of second gate driving signals according to the delta t values obtained corresponding to G1 and G2 in the memory cells respectively.
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