CN106652933B - Grid drive circuit with forward and reverse scanning function - Google Patents
Grid drive circuit with forward and reverse scanning function Download PDFInfo
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- CN106652933B CN106652933B CN201611019490.5A CN201611019490A CN106652933B CN 106652933 B CN106652933 B CN 106652933B CN 201611019490 A CN201611019490 A CN 201611019490A CN 106652933 B CN106652933 B CN 106652933B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
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Abstract
The invention discloses a grid driving circuit with a forward and reverse scanning function, which comprises a forward scanning pre-charging module, a reverse scanning pre-charging module, a pull-up module, a grid scanning signal maintaining module, a pull-up control node maintaining module, an auxiliary module, an emptying reset module and a bootstrap capacitor. The grid drive circuit can realize the forward and reverse scanning function; the forward scanning pre-charging module can be used as a pull-down emptying module of the pull-up control node during reverse scanning, and the reverse scanning pre-charging module can be used as a pull-down emptying module of the pull-up control node during forward scanning; the maintaining module of the pull-up control node can maintain in forward scanning and reverse scanning; the design can reduce the number of elements and reduce the space so as to realize the narrow frame design.
Description
Technical Field
The present invention relates to a gate driving circuit, and more particularly, to a gate driving circuit having a forward and reverse scanning function.
Background
In some special applications, the lcd needs to have forward and reverse scanning functions, for example, the display screen of the mobile phone can be placed normally or turned upside down, so the gate driving circuit is required to perform either top-down scanning or bottom-up scanning. Fig. 1 shows a currently mainstream gate driving circuit, which cannot perform reverse scanning. Because the maintaining module of the pull-up control node netAn in the circuit is controlled by using the previous clock signal, if reverse scanning is carried out, the pull-up control node netAn cannot maintain; the pull-down clearing module of the pull-up control node netAn utilizes the gate scanning signal G of the later stagen+3Controlled by the pre-charge module using the gate scanning signal G of the previous stagen-2The control is carried out, the control signals are asymmetric, and if reverse scanning is carried out, the circuit cannot normally operate.
Disclosure of Invention
The purpose of the invention is as follows: in view of the above problems, the present invention provides a gate driving circuit with forward and reverse scanning functions.
The technical scheme is as follows: in order to realize the purpose of the invention, the technical scheme adopted by the invention is as follows: a gate drive circuit with forward and reverse scanning functions comprises a forward scanning pre-charging module, a reverse scanning pre-charging module, a pull-up module, a gate scanning signal maintaining module, a pull-up control node maintaining module, an auxiliary module, an emptying reset module and a bootstrap capacitor, wherein the forward scanning pre-charging module is connected with the reverse scanning pre-charging module; the system comprises a forward scanning pre-charging module, a backward scanning pre-charging module, a pull-up module, a maintenance module of a pull-up control node, an auxiliary module and a bootstrap capacitor, wherein the forward scanning pre-charging module is connected with a grid scanning signal of a front stage, the backward scanning pre-charging module is connected with a grid scanning signal of a rear stage, the forward scanning pre-charging module and the backward scanning pre-charging module are both connected with the pull-up module, the maintenance module of the pull-up control node, the auxiliary module and the bootstrap capacitor are both connected with the maintenance module of the grid scanning signal, the maintenance module of the pull-up control node, the auxiliary module and the emptying.
The connection node of the forward scanning pre-charging module and the pull-up module is a pull-up control node; the forward scanning pre-charging module is controlled by a forward scanning control signal, and is used as a pre-charging module during forward scanning and used as a pull-down emptying module during reverse scanning; the reverse scanning pre-charging module is controlled by a reverse scanning control signal, and is used as a pre-charging module during reverse scanning and used as a pull-down emptying module during forward scanning; the pull-up module is controlled by a clock signal and is used for driving the output of a grid scanning signal; the maintaining module of the grid scanning signal is controlled by a clock signal and is used for maintaining the grid scanning signal; the maintaining module of the pull-up control node is controlled by a clock signal and is used for maintaining the pull-up control node during forward scanning and reverse scanning; the auxiliary module is controlled by the starting signal and is used for assisting the maintaining module; the clearing reset module is controlled by a clearing reset signal and is used for clearing electric charges of nodes in the circuit when each frame is finished and the power is turned on or off; the bootstrap capacitor is used for lifting the potential of the pull-up control node; the connection node of the pull-up module and the maintaining module of the grid scanning signal outputs the grid scanning signal.
The forward scanning pre-charging module is composed of a first thin film transistor, the source electrode of the first thin film transistor is connected with a forward scanning control signal, and the grid electrode of the first thin film transistor is connected with a grid electrode scanning signal of a front stage; the reverse scanning pre-charging module is composed of a second thin film transistor, the source electrode of the second thin film transistor is connected with a reverse scanning control signal, and the grid electrode of the second thin film transistor is connected with a grid electrode scanning signal of a rear stage; the pull-up module is composed of a third thin film transistor, the source electrode of the third thin film transistor is connected with a clock signal, and the grid electrode of the third thin film transistor is connected with the drain electrode of the second thin film transistor; the maintaining module of the grid scanning signal is composed of a fourth thin film transistor, the source electrode of the fourth thin film transistor is connected with the drain electrode of the third thin film transistor, and the grid electrode of the fourth thin film transistor is connected with the clock signal; the maintaining module of the pull-up control node comprises a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, a ninth thin film transistor and a tenth thin film transistor, wherein the source electrode of the fifth thin film transistor is connected with a forward scanning control signal, the grid electrode of the fifth thin film transistor is connected with a clock signal, the source electrode of the sixth thin film transistor is connected with a reverse scanning control signal, the grid electrode of the sixth thin film transistor is connected with the clock signal, the source electrode of the seventh thin film transistor is connected with the drain electrode of the fifth thin film transistor, the grid electrode of the seventh thin film transistor is connected with a grid scanning signal of a previous stage, the source electrode of the eighth thin film transistor is connected with the drain electrode of the fifth thin film transistor, the grid electrode of the eighth thin film transistor is connected with the drain electrode of the first thin film transistor, the source electrode of the ninth thin film transistor is connected with the drain electrode of the sixth, a source electrode of the tenth thin film transistor is connected with a drain electrode of the second thin film transistor, and a grid electrode of the tenth thin film transistor is connected with a drain electrode of the sixth thin film transistor; the auxiliary module comprises an eleventh thin film transistor and a twelfth thin film transistor, wherein the source electrode of the eleventh thin film transistor is connected with the drain electrode of the first thin film transistor, the grid electrode of the eleventh thin film transistor is connected with a forward starting signal, the source electrode of the twelfth thin film transistor is connected with the drain electrode of the first thin film transistor, and the grid electrode of the twelfth thin film transistor is connected with a reverse starting signal; the emptying resetting module comprises a thirteenth thin film transistor, a fourteenth thin film transistor and a fifteenth thin film transistor, wherein the source electrode of the thirteenth thin film transistor is connected with the drain electrode of the first thin film transistor, the source electrode of the fourteenth thin film transistor is connected with the drain electrode of the third thin film transistor, the source electrode of the fifteenth thin film transistor is connected with the drain electrode of the fifth thin film transistor, and the grid electrodes of the thirteenth thin film transistor, the fourteenth thin film transistor and the fifteenth thin film transistor are all connected with an emptying resetting signal; the bootstrap capacitor is connected with the grid electrode and the drain electrode of the third thin film transistor; the drains of the fourth thin film transistor, the seventh thin film transistor, the eighth thin film transistor, the ninth thin film transistor, the tenth thin film transistor, the eleventh thin film transistor, the twelfth thin film transistor, the thirteenth thin film transistor, the fourteenth thin film transistor and the fifteenth thin film transistor are all connected to a constant voltage low potential; the drain of the third thin film transistor outputs a gate scan signal.
The thirteenth thin film transistor is removed, and the function of the thirteenth thin film transistor is realized by the cooperation of the eleventh thin film transistor and the twelfth thin film transistor.
The grid electrode of the fifth thin film transistor is controlled by the forward scanning signal, the source electrode of the fifth thin film transistor is connected with the clock signal, the grid electrode of the sixth thin film transistor is controlled by the reverse scanning signal, and the source electrode of the sixth thin film transistor is connected with the clock signal.
Has the advantages that: the grid drive circuit can realize the forward and reverse scanning function; the forward scanning pre-charging module can be used as a pull-down emptying module of the pull-up control node during reverse scanning, and the reverse scanning pre-charging module can be used as a pull-down emptying module of the pull-up control node during forward scanning; the maintaining module of the pull-up control node can maintain in forward scanning and reverse scanning; the function of a thirteenth thin film transistor is realized by utilizing the combined action of the eleventh thin film transistor and the twelfth thin film transistor, and the thirteenth thin film transistor is removed; the design can reduce the number of elements and reduce the space so as to realize the narrow frame design.
Drawings
Fig. 1 is a circuit diagram of a conventional gate driving circuit;
FIG. 2 is a circuit diagram of a gate driving circuit with forward and reverse scanning functions according to the present invention;
FIG. 3 is a waveform diagram of the gate driving circuit of the present invention during forward scanning;
FIG. 4 is a waveform diagram of the gate driving circuit of the present invention during reverse scan;
FIG. 5 is a circuit diagram of an alternative embodiment of the present invention;
fig. 6 is a circuit diagram of another alternative embodiment of the present invention.
Detailed Description
The technical solution of the present invention is further described below with reference to the accompanying drawings and examples.
Fig. 2 is a circuit diagram of a gate driving circuit with forward and reverse scanning functions according to the present invention, which includes a forward scanning precharge module 1, a reverse scanning precharge module 2, a pull-up module 3, a gate scanning signal sustain module 4, a pull-up control node sustain module 5, an auxiliary module 6, a clear reset module 7 and a bootstrap capacitor 8, where a connection node between the forward scanning precharge module 1 and the pull-up module 3 is a pull-up control node netAn, and a connection node between the pull-up module 3 and the gate scanning signal sustain module 4 outputs a gate scanning signal G of the present stagen。
The specific circuit of the gate drive circuit is as follows: the forward scan pre-charge module 1 comprises a first thin film transistor M1, a source of the first thin film transistor M1 is connected with a forward scan control signal U2D, and a gate of the first thin film transistor M1 is connected with a gate scan signal G of a previous stagen-2The gate of the first thin film transistor M1 of the gate driving circuit of the first two stages is connected to the forward start signal GSP1, and the forward scan precharge module 1 acts as a pull-down clearing module for the pull-up control node netAn during the reverse scan.
The reverse scan precharge module 2 comprises a second thin film transistor M2, a source of the second thin film transistor M2 is connected to the reverse scan control signal D2U, and a gate of the second thin film transistor M2 is connected to the gate scan signal G of the next stagen+2The gate of the second thin film transistor M2 of the gate driving circuit of the last two stages is connected to the reverse start signal GSP2, and the reverse scan precharge module 2 acts as a pull-down clearing module for the pull-up control node netAn during forward scan.
A pull-up module 3 mainly responsible for outputting a gate scan signal GnA third TFT M3, wherein the source of the third TFT M3 is connected to the clock signal CKmThe gate of the third thin film transistor M3 is connected to the drain of the second thin film transistor M2.
A maintaining module 4 for maintaining the gate scan signal GnIncludes a fourth thin film transistor M4, the source of the fourth thin film transistor M4 is connected to the drain of the third thin film transistor M3, the gate of the fourth thin film transistor M4 is connected to the clock signal CKm+2。
The pull-up control node maintaining module 5 may maintain the pull-up control node netAn during forward scanning and maintain the pull-up control node netAn during reverse scanning, and includes a fifth thin film transistor M5, a sixth thin film transistor M6, a seventh thin film transistor M7, an eighth thin film transistor M8, a ninth thin film transistor M9 and a tenth thin film transistor M10, wherein a source of the fifth thin film transistor M5 is connected to the forward scanning control signal U2D, and a gate of the fifth thin film transistor M5 is connected to the clock signal CK 2Dm-1The source of the sixth thin film transistor M6 is connected to the inverse scan control signal D2U, and the gate of the sixth thin film transistor M6 is connected to the clock signal CKm+1A source of the seventh thin film transistor M7 is connected to the drain of the fifth thin film transistor M5, and a gate of the seventh thin film transistor M7 is connected to the gate scan signal G of the previous stagen-2A source of the eighth tft M8 is connected to the drain of the fifth tft M5, the connection point is a pull-down control node netBn, a gate of the eighth tft M8 is connected to the drain of the first tft M1, a source of the ninth tft M9 is connected to the drain of the sixth tft M6, and a gate of the ninth tft M9 is connected to the gate scan signal G of the next stagen+2The source of the tenth thin film transistor M10 is connected to the drain of the second thin film transistor M2, and the gate of the tenth thin film transistor M10 is connected to the drain of the sixth thin film transistor M6.
The auxiliary module 6, configured to assist the sustain module, includes an eleventh thin film transistor M11 and a twelfth thin film transistor M12. During forward scanning, the eleventh thin film transistor M11 assists in maintaining, the source of the eleventh thin film transistor M11 is connected to the drain of the first thin film transistor M1, and the gate of the eleventh thin film transistor M11 is connected to the forward start signal GSP 1; during the reverse scan, the twelfth thin film transistor M12 assists the sustain, the source of the twelfth thin film transistor M12 is connected to the drain of the first thin film transistor M1, the gate of the twelfth thin film transistor M12 is connected to the reverse start signal GSP2, and the eleventh thin film transistor M11 and the twelfth thin film transistor M12 of the previous third gate driving circuit are both connected to a constant voltage low potential VSS.
The clearing reset module 7 is mainly responsible for clearing charges of nodes inside the circuit when each frame is finished and the circuit is turned on and off, and includes a thirteenth thin film transistor M13, a fourteenth thin film transistor M14 and a fifteenth thin film transistor M15, wherein a source of the thirteenth thin film transistor M13 is connected to a drain of the first thin film transistor M1, a source of the fourteenth thin film transistor M14 is connected to a drain of the third thin film transistor M3, a source of the fifteenth thin film transistor M15 is connected to a drain of the fifth thin film transistor M5, and gates of the thirteenth thin film transistor M13, the fourteenth thin film transistor M14 and the fifteenth thin film transistor M15 are all connected to a clearing reset signal.
Drains of the fourth thin film transistor M4, the seventh thin film transistor M7, the eighth thin film transistor M8, the ninth thin film transistor M9, the tenth thin film transistor M10, the eleventh thin film transistor M11, the twelfth thin film transistor M12, the thirteenth thin film transistor M13, the fourteenth thin film transistor M14, and the fifteenth thin film transistor M15 are all connected to a constant voltage low potential VSS.
The bootstrap capacitor 8 is connected to the gate and the drain of the third thin film transistor M3, and is mainly used for raising the potential of the pull-up control node netAn.
When U2D is at high voltage level and D2U is at low voltage level, the gate driving circuit performs forward scan, the forward scan precharge module 1 is used as a precharge module, the reverse scan precharge module 2 is used as a pull-down empty module, and the sustain module 5 of the pull-up control node is driven by the clock signal CKm-1The pull-up control node netAn is controlled to be maintained, wherein the fifth tft M5 charges the pull-down control node netBn, and the sixth tft M6 discharges the pull-down control node netBn.
When U2D is at a low potential and D2U is at a high potential, the gate driving circuit performs a reverse scan, the reverse scan precharge module 2 is used as a precharge module, the forward scan precharge module 1 is used as a pull-down purge module, and the sustain module 5 of the pull-up control node is driven by the clock signal CKm+1The pull-up control node netAn is controlled to be maintained, wherein the pull-down control node netBn is charged by the sixth thin film transistor M6, and discharged by the fifth thin film transistor M5.
The forward and reverse scanning is performed by two signals of a forward scanning control signal U2D and a reverse scanning control signal D2UThe switching control controls the switching of the pre-charging module, the pull-down emptying module and the maintaining module, the design reduces the number of elements, and the space is reduced so as to realize the design of a narrow frame. The waveform diagram of the gate driving circuit in the forward scanning is shown in FIG. 3, in which CK1, CK2, CK3 and CK4 are clock control signals, and the clock control signals CK are sequentially outputted in the forward scanning to control the clock signals CKm-1、CKm、CKm+1And CKm+2U2D is a positive high voltage, D2U is a negative low voltage, and VSS is a constant voltage low voltage, and is mainly responsible for providing a gate scan signal GnLow potential of (3), gate scanning signal G at the time of forward scanningn-2、Gn、Gn+2And sequentially outputting from small to large. The waveform diagram of the gate driving circuit in the reverse scanning is shown in fig. 4, in which the clock control signals CK1, CK2, CK3 and CK4 are output in reverse order in the reverse scanning, D2U is a high positive voltage, U2D is a low negative voltage, and the gate scanning signal G in the forward scanning isn-2、Gn、Gn+2And (5) outputting in a reverse order from large to small.
On the basis of the gate driving circuit shown in fig. 2, the thirteenth thin film transistor M13 in the clear reset module 7 is removed, and the eleventh thin film transistor M11 and the twelfth thin film transistor M12 simultaneously function to realize the function of the thirteenth thin film transistor M13, so as to obtain the gate driving circuit shown in fig. 5.
As shown in FIG. 6, in the sustain module 5 of the pull-up control node of the gate driving circuit, the gate of the fifth TFT M5 is controlled by the forward scan signal U2D, and the source of the fifth TFT M5 is connected to the clock signal CKm-1The gate of the sixth TFT M6 is controlled by the reverse scan signal D2U, and the source of the sixth TFT M6 is connected to the clock signal CKm+1. In the forward scan, the fifth tft M5 is controlled to be turned on by U2D, and the sixth tft M6 is controlled to be turned off by D2U, at this time, the fifth tft M5 can charge the pull-down control node netBn and discharge the pull-down control node netBn. During the reverse scan, the fifth tft M5 is turned off by U2D, and the sixth tft M6 is turned on by D2U, and at this time, the sixth tft M6 may be turned on downwardThe pull control node netBn is charged and can also be discharged.
In addition to the gate driving circuit shown in fig. 6, the thirteenth thin film transistor M13 in the clear reset module 7 may be eliminated, and the eleventh thin film transistor M11 and the twelfth thin film transistor M12 may act simultaneously to realize the function of the thirteenth thin film transistor M13.
Claims (4)
1. A gate driving circuit having a forward and reverse scanning function, comprising: the device comprises a forward scanning pre-charging module (1), a reverse scanning pre-charging module (2), a pull-up module (3), a maintaining module (4) of grid scanning signals, a maintaining module (5) of a pull-up control node, an auxiliary module (6), an emptying reset module (7) and a bootstrap capacitor (8); the system comprises a forward scanning pre-charging module (1), a reverse scanning pre-charging module (2), a pull-up module (3), a maintaining module (5) of a pull-up control node, an auxiliary module (6) and a bootstrap capacitor (8), wherein the forward scanning pre-charging module (1) is connected with a grid scanning signal of a front stage, the reverse scanning pre-charging module (2) is connected with a grid scanning signal of a rear stage, the forward scanning pre-charging module (1) and the reverse scanning pre-charging module (2) are both connected with the pull-up module (3), the maintaining module (5) of the pull-up control node, the auxiliary module (6) and the bootstrap capacitor (8), the pull-up module (3) and the bootstrap capacitor (8) are both connected with the maintaining module (4) of the grid scanning signal, the maintaining module (5) of the pull-up control node, the maintaining;
the connecting node of the forward scanning pre-charging module (1) and the pull-up module (3) is a pull-up control node; the forward scanning pre-charging module (1) is controlled by a forward scanning control signal, and is used as a pre-charging module during forward scanning and used as a pull-down emptying module during reverse scanning; the reverse scanning pre-charging module (2) is controlled by a reverse scanning control signal, and is used as a pre-charging module during reverse scanning and used as a pull-down emptying module during forward scanning; the pull-up module (3) is controlled by a clock signal and is used for driving the output of a grid scanning signal; the maintaining module (4) of the grid scanning signal is controlled by a clock signal and is used for maintaining the grid scanning signal; a maintaining module (5) of the pull-up control node is controlled by a clock signal and is used for maintaining the pull-up control node during forward scanning and reverse scanning; the auxiliary module (6) is controlled by the starting signal and is used for assisting the maintaining module; the clearing reset module (7) is controlled by a clearing reset signal and is used for clearing electric charges of nodes in the circuit when each frame is finished and the circuit is turned on and off; the bootstrap capacitor (8) is used for lifting the potential of the pull-up control node; the connection node of the pull-up module (3) and the maintaining module (4) of the grid scanning signal outputs the grid scanning signal; the forward scanning pre-charging module (1) is composed of a first thin film transistor (M1), the source electrode of the first thin film transistor (M1) is connected with a forward scanning control signal, and the grid electrode of the first thin film transistor (M1) is connected with a grid electrode scanning signal of a previous stage;
the reverse scanning pre-charging module (2) is composed of a second thin film transistor (M2), the source electrode of the second thin film transistor (M2) is connected with a reverse scanning control signal, and the grid electrode of the second thin film transistor (M2) is connected with a grid electrode scanning signal of a later stage;
the pull-up module (3) is composed of a third thin film transistor (M3), the source electrode of the third thin film transistor (M3) is connected with a clock signal, and the grid electrode of the third thin film transistor (M3) is connected with the drain electrode of the second thin film transistor (M2);
the maintaining module (4) of the grid scanning signal is composed of a fourth thin film transistor (M4), the source electrode of the fourth thin film transistor (M4) is connected with the drain electrode of the third thin film transistor (M3), and the grid electrode of the fourth thin film transistor (M4) is connected with the clock signal;
the sustain module (5) of the pull-up control node includes a fifth thin film transistor (M5), a sixth thin film transistor (M6), a seventh thin film transistor (M7), an eighth thin film transistor (M8), a ninth thin film transistor (M9) and a tenth thin film transistor (M10), wherein a source of the fifth thin film transistor (M5) is connected to the forward scan control signal, a gate of the fifth thin film transistor (M5) is connected to the clock signal, a source of the sixth thin film transistor (M6) is connected to the reverse scan control signal, a gate of the sixth thin film transistor (M6) is connected to the clock signal, a source of the seventh thin film transistor (M7) is connected to a drain of the fifth thin film transistor (M5), a gate of the seventh thin film transistor (M7) is connected to the gate scan signal of the previous stage, a source of the eighth thin film transistor (M8) is connected to a drain of the fifth thin film transistor (M5), and a gate of the eighth thin film transistor (M8) is connected to a drain of the first thin film transistor (M1), a source of the ninth thin film transistor (M9) is connected to a drain of the sixth thin film transistor (M6), a gate of the ninth thin film transistor (M9) is connected to a gate scan signal of a subsequent stage, a source of the tenth thin film transistor (M10) is connected to a drain of the second thin film transistor (M2), and a gate of the tenth thin film transistor (M10) is connected to a drain of the sixth thin film transistor (M6);
the auxiliary module (6) comprises an eleventh thin film transistor (M11) and a twelfth thin film transistor (M12), wherein the source electrode of the eleventh thin film transistor (M11) is connected with the drain electrode of the first thin film transistor (M1), the grid electrode of the eleventh thin film transistor (M11) is connected with a forward starting signal, the source electrode of the twelfth thin film transistor (M12) is connected with the drain electrode of the first thin film transistor (M1), and the grid electrode of the twelfth thin film transistor (M12) is connected with a reverse starting signal;
the emptying reset module (7) comprises a thirteenth thin film transistor (M13), a fourteenth thin film transistor (M14) and a fifteenth thin film transistor (M15), wherein the source of the thirteenth thin film transistor (M13) is connected with the drain of the first thin film transistor (M1), the source of the fourteenth thin film transistor (M14) is connected with the drain of the third thin film transistor (M3), the source of the fifteenth thin film transistor (M15) is connected with the drain of the fifth thin film transistor (M5), and the gates of the thirteenth thin film transistor (M13), the fourteenth thin film transistor (M14) and the fifteenth thin film transistor (M15) are all connected with an emptying reset signal;
the bootstrap capacitor (8) is connected with the grid electrode and the drain electrode of the third thin film transistor (M3); drains of a fourth thin film transistor (M4), a seventh thin film transistor (M7), an eighth thin film transistor (M8), a ninth thin film transistor (M9), a tenth thin film transistor (M10), an eleventh thin film transistor (M11), a twelfth thin film transistor (M12), a thirteenth thin film transistor (M13), a fourteenth thin film transistor (M14), and a fifteenth thin film transistor (M15) are all connected to the constant voltage low potential; the drain of the third thin film transistor (M3) outputs a gate scan signal.
2. The gate driving circuit having a forward and reverse scanning function according to claim 1, characterized in that: the thirteenth thin film transistor (M13) is eliminated, and the function of the thirteenth thin film transistor (M13) is realized by the combined action of the eleventh thin film transistor (M11) and the twelfth thin film transistor (M12).
3. The gate driving circuit having a forward and reverse scanning function according to claim 1, characterized in that: the gate of the fifth thin film transistor (M5) is controlled by the forward direction scan signal, the source of the fifth thin film transistor (M5) is connected to the clock signal, the gate of the sixth thin film transistor (M6) is controlled by the reverse direction scan signal, and the source of the sixth thin film transistor (M6) is connected to the clock signal.
4. The gate driving circuit having a forward and reverse scanning function according to claim 3, characterized in that: the thirteenth thin film transistor (M13) is eliminated, and the function of the thirteenth thin film transistor (M13) is realized by the combined action of the eleventh thin film transistor (M11) and the twelfth thin film transistor (M12).
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| CN107591136B (en) * | 2017-08-25 | 2019-03-19 | 南京中电熊猫平板显示科技有限公司 | A kind of gated sweep driving circuit and liquid crystal display device |
| CN107833552B (en) * | 2017-11-17 | 2020-09-25 | 合肥鑫晟光电科技有限公司 | Gate driving unit, gate driving circuit, driving method of gate driving circuit and display device |
| CN108154856B (en) * | 2017-12-27 | 2020-10-02 | 南京中电熊猫液晶显示科技有限公司 | Grid scanning driving circuit |
| CN108269541B (en) * | 2017-12-27 | 2019-09-20 | 南京中电熊猫平板显示科技有限公司 | Gated sweep driving circuit |
| CN108242228B (en) * | 2018-01-29 | 2020-08-04 | 南京中电熊猫平板显示科技有限公司 | Grid scanning driving circuit |
| CN109935198B (en) * | 2018-05-31 | 2021-01-22 | 京东方科技集团股份有限公司 | Shift register unit, grid driving circuit, display device and driving method |
| CN109935197B (en) | 2018-02-14 | 2021-02-26 | 京东方科技集团股份有限公司 | Shift register unit, gate drive circuit, display device and drive method |
| CN109935208B (en) * | 2018-02-14 | 2021-03-02 | 京东方科技集团股份有限公司 | Shift register unit, gate drive circuit, display device and drive method |
| JP7433050B2 (en) | 2018-02-14 | 2024-02-19 | 京東方科技集團股▲ふん▼有限公司 | Shift register unit, gate drive circuit, display device and driving method |
| CN109935196B (en) * | 2018-02-14 | 2020-12-01 | 京东方科技集团股份有限公司 | Shift register unit, gate drive circuit, display device and drive method |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1240043A (en) * | 1996-12-09 | 1999-12-29 | 汤姆森多媒体公司 | Bi-directional shift register |
| CN101364392A (en) * | 2007-08-06 | 2009-02-11 | 三星电子株式会社 | Gate driving circuit and display device having the same |
| CN104103244A (en) * | 2013-04-03 | 2014-10-15 | 瀚宇彩晶股份有限公司 | Liquid crystal display and bidirectional shift temporary storage device thereof |
| CN104299583A (en) * | 2014-09-26 | 2015-01-21 | 京东方科技集团股份有限公司 | Shifting register, drive method of shifting register, drive circuit and display device |
| CN204257182U (en) * | 2014-12-15 | 2015-04-08 | 京东方科技集团股份有限公司 | Shift register, gate driver circuit, array base palte, display device |
| CN104537991A (en) * | 2014-12-30 | 2015-04-22 | 深圳市华星光电技术有限公司 | Forward-reverse scanning gate drive circuit |
| CN105206244A (en) * | 2015-10-29 | 2015-12-30 | 武汉华星光电技术有限公司 | GOA circuit and liquid crystal display |
| CN105931602A (en) * | 2016-06-30 | 2016-09-07 | 京东方科技集团股份有限公司 | Shift register, driving method thereof and grid drive circuit |
| CN106098002A (en) * | 2016-08-05 | 2016-11-09 | 武汉华星光电技术有限公司 | Scan drive circuit and there is the flat display apparatus of this circuit |
-
2016
- 2016-11-18 CN CN201611019490.5A patent/CN106652933B/en not_active Expired - Fee Related
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1240043A (en) * | 1996-12-09 | 1999-12-29 | 汤姆森多媒体公司 | Bi-directional shift register |
| CN101364392A (en) * | 2007-08-06 | 2009-02-11 | 三星电子株式会社 | Gate driving circuit and display device having the same |
| CN104103244A (en) * | 2013-04-03 | 2014-10-15 | 瀚宇彩晶股份有限公司 | Liquid crystal display and bidirectional shift temporary storage device thereof |
| CN104299583A (en) * | 2014-09-26 | 2015-01-21 | 京东方科技集团股份有限公司 | Shifting register, drive method of shifting register, drive circuit and display device |
| CN204257182U (en) * | 2014-12-15 | 2015-04-08 | 京东方科技集团股份有限公司 | Shift register, gate driver circuit, array base palte, display device |
| CN104537991A (en) * | 2014-12-30 | 2015-04-22 | 深圳市华星光电技术有限公司 | Forward-reverse scanning gate drive circuit |
| CN105206244A (en) * | 2015-10-29 | 2015-12-30 | 武汉华星光电技术有限公司 | GOA circuit and liquid crystal display |
| CN105931602A (en) * | 2016-06-30 | 2016-09-07 | 京东方科技集团股份有限公司 | Shift register, driving method thereof and grid drive circuit |
| CN106098002A (en) * | 2016-08-05 | 2016-11-09 | 武汉华星光电技术有限公司 | Scan drive circuit and there is the flat display apparatus of this circuit |
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