CN204257182U - Shift register, gate driver circuit, array base palte, display device - Google Patents
Shift register, gate driver circuit, array base palte, display device Download PDFInfo
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- CN204257182U CN204257182U CN201420797059.3U CN201420797059U CN204257182U CN 204257182 U CN204257182 U CN 204257182U CN 201420797059 U CN201420797059 U CN 201420797059U CN 204257182 U CN204257182 U CN 204257182U
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Abstract
The utility model provides a kind of shift register, gate driver circuit, array base palte, display device, belongs to display technique field, and it can solve the problem of the output instability in zone of transition of existing shift register.Shift register of the present utility model, it comprises the shift register cell of multiple cascade, also comprises: detecting unit and reset feedback unit; Wherein, described detecting unit connects at least two shift register cells, for detecting the current potential that shift register cell exports, and this testing result is transferred to described reset feedback unit; Described reset feedback unit is connected with shift register cell described at least one, during for detecting that the current potential that the shift register cell be connected with described detecting unit exports is anticipation power down bit when described detecting unit, the current potential exported described in the shift register cell be connected with reset feedback unit is resetted; Wherein, the current potential that anticipation power down bit exports in zone of transition for each described shift register cell.
Description
Technical field
The utility model belongs to display technique field, is specifically related to a kind of shift register, gate driver circuit, array base palte, display device.
Background technology
TFT-LCD (Thin Film Transistor-Liquid Crystal Display, thin-film transistor LCD device) ultimate principle that realizes a frame picture display is carry out gating to the square wave of every one-row pixels input one fixed width successively from top to bottom by grid (gate) driving circuit, then exported from top to bottom successively by the signal of source electrode (source) driving circuit needed for every one-row pixels.
At present, most TFT-LCD arranges gate driver circuit and source electrode drive circuit in panels outside, but this kind of set-up mode cost compare is high, thus other alternative is created, namely, substrate makes the gate driver circuit that multiple shift register cell forms, namely adopts the design of GOA (Gate Drive On Array) circuit.
Wherein, the output timing in gate driver circuit comprises: effective display area and zone of transition.As shown in Figure 1, concrete, when display one frame picture, export the connected grid line of scanning one by one from first shift register cell to N number of shift register cell in effective display area, after each grid line is completed by scanning, then enter zone of transition, now because each shift register cell does not work in this region, therefore become 0 at the output potential of this each shift register cell of region (output potential due to shift register cell is negative value simultaneously, therefore this process is pull-up process), thus cause the output of each shift register cell unstable.
Utility model content
Technical problem to be solved in the utility model comprises, and for the above-mentioned problem that existing shift register exists, provides a kind of shift register of stable output, gate driver circuit, array base palte, display device.
Solving the technical scheme that the utility model technical matters adopts is a kind of shift register, and it comprises the shift register cell of multiple cascade, itself and detecting unit and reset feedback unit; Wherein,
Described detecting unit connects at least two shift register cells, for detecting the current potential that connected described shift register cell exports, and this testing result is transferred to described reset feedback unit;
Described reset feedback unit is connected with shift register cell described at least one, during for detecting that the current potential that the shift register cell be connected with described detecting unit exports is anticipation power down bit when described detecting unit, the current potential exported described in the shift register cell be connected with described reset feedback unit is resetted; Wherein, the current potential that exports in zone of transition for each described shift register cell of described anticipation power down bit.
Preferably, described reset feedback unit is connected with each described shift register cell, during for detecting that the current potential that the shift register cell be connected with described detecting unit exports is anticipation power down bit when described detecting unit, the current potential exported described in each shift register cell is resetted.
Preferably, described detecting unit comprises modular converter,
Described modular converter is electrically connected with at least two shift register cells and reset feedback unit, whether the current potential for being exported by connected shift register cell is converted to the first current potential, and worked by the feedback unit that resets described in described first control of Electric potentials.
Further preferably, described detecting unit also comprises bi-directional logic level adjusting module, and described bi-directional logic level adjusting module comprises multiple forward transmission channel and at least one reverse channel transmission;
Described bi-directional logic level adjusting module is connected with at least two shift register cells, and is connected with modular converter respectively by different described forward transmission channels from the shift register cell that described bi-directional logic level adjusting module connects; Described bi-directional logic level adjusting module is used for the current potential that connected shift register cell exports to be adjusted to the first intermediate potential, and the first intermediate potential is transferred to modular converter;
Described modular converter is also connected with a reverse channel transmission of described bi-directional logic level adjusting module, for described first intermediate potential is adjusted to the second intermediate potential;
Described reverse channel transmission is used for described second intermediate potential to be adjusted to the first current potential, exports to reset feedback unit.
Preferably, described modular converter is AND circuit.
Preferably, described reset feedback unit comprises: described reset feedback unit comprises: at least one switching transistor,
The grid of each described switching transistor all connects anti-phase output channel, and source electrode connects a shift register cell, and each described shift register cell is connected with the source electrode of a switching transistor at the most, and drain electrode connects reset signal.
Preferably, described reset feedback unit comprises multiple and each shift register cell switching transistor one to one,
The grid of described switching transistor connects anti-phase output channel, and source electrode connects shift register cell, and drain electrode connects reset signal.
Further preferably, described switching transistor is N-type transistor.
Further preferably, described first current potential is high level, and described reset signal is low level.
Preferably, described detecting unit connects two described shift register cells.
Further preferably, two the described shift register cells be connected with described detecting unit be in the shift register cell of multiple cascade first and last.
The technical scheme that solution the utility model technical matters adopts is a kind of gate driver circuit, and it comprises above-mentioned shift register.
The technical scheme that solution the utility model technical matters adopts is a kind of array base palte, and it comprises above-mentioned gate driver circuit.
The technical scheme that solution the utility model technical matters adopts is a kind of display device, and it comprises above-mentioned array base palte.
The utility model has following beneficial effect:
Detecting unit is added in the shift register of utility model, when detecting unit detects that the current potential that each shift register cell connected exports is anticipation power down bit, that is the display of this frame picture is in zone of transition, because each shift register cell is all in idle state, therefore the output potential of each shift register cell can not maintain the output in a moment, thus it is unstable to cause the signal of shift register cell to export, and then it is unstable to cause picture to show.But also comprise reset feedback unit in the present embodiment simultaneously, when detecting unit detect that connected shift register cell exports for anticipation power down bit time, control reset feedback unit by this testing result to reset to the current potential exported described in each shift register cell, stablize to make the current potential exported described in each shift register cell.
Accompanying drawing explanation
Fig. 1 is the structural representation of embodiment 1 shift register of the present utility model;
Fig. 2 is the working timing figure of Fig. 1;
Fig. 3 is the working timing figure of existing shift register.
Wherein Reference numeral is: 10, shift register cell; 20, detecting unit; 21, modular converter; 22, bi-directional logic level adjusting module; 30, reset feedback unit; The current potential that G1, GN, shift register cell export; G1, gN, the first intermediate potential; En, the second intermediate potential; EN, the first current potential.
Embodiment
For making those skilled in the art understand the technical solution of the utility model better, below in conjunction with the drawings and specific embodiments, the utility model is described in further detail.
Embodiment 1:
Shown in composition graphs 1, the present embodiment provides a kind of shift register, and it comprises the shift register cell 10 of multiple cascade, and detecting unit 20 and reset feedback unit 30; Wherein, described detecting unit 20 connects at least two shift register cells 10, for detecting current potential G1, GN that described shift register cell 10 exports, and this testing result is transferred to described reset feedback unit 30; Described reset feedback unit 30 is connected with at least one shift register cell 10, for when described detecting unit 20 detects that current potential G1, GN that the shift register cell 10 be connected with described detecting unit 20 exports are anticipation power down bit Vth, current potential G1, the GN exported described in the shift register cell 10 be connected with reset feedback unit 30 is resetted; Wherein, described anticipation power down bit Vth allows the potential threshold that exports for each described shift register cell 10 in zone of transition.
It will be appreciated by persons skilled in the art that when display one frame picture, the sequential of display comprises effective display area and zone of transition (blank district); Wherein, effective display area refers to that each shift register in shift register exports a square wave successively to the time of connected grid line; Zone of transition refers to that each shift register exports all idle time of each shift register cell 10 after a square wave successively; Briefly, such as display device is when carrying out picture display, and can produce a transition when the first frame picture is transformed into the second frame picture, the moment of this transition is zone of transition, and the time scanning a frame picture is effective display area.Certainly, be understandable that, the moment changed from effective display area to zone of transition and from zone of transition to effective display area, the current potential that each shift register cell 10 exports can not saltus step at once, is the interval that there is certain hour simultaneously; Concrete, each shift register cell 10, after effective display area exports a square-wave signal, namely becomes VGL current potential from VGH current potential and exports, after this when entering into zone of transition, originally each shift register cell 10 will continue to export VGL current potential, just can change from VGL to 0V subsequently.In like manner, it is also like this for entering effective display area change moment in zone of transition.But those skilled in the art should know, when carrying out the selection of anticipation power down bit, usually select in the current potential after the output potential of zone of transition changes, in other words the output potential of zone of transition typically refers to the current potential entering and export after zone of transition current potential changes.
Detecting unit 20 is added in the shift register of the present embodiment, when detecting unit 20 detects that the current potential that each shift register cell 10 connected exports is anticipation power down bit Vth, that is the display of this frame picture is in zone of transition, because each shift register cell 10 is all in idle state, therefore output potential G1, GN of each shift register cell 10 can not maintain the output in a moment, thus it is unstable to cause the signal of shift register cell 10 to export, and then it is unstable to cause picture to show.But also comprise reset feedback unit 30 in the present embodiment simultaneously, when described detecting unit 20 detects that current potential G1, GN that the shift register cell 10 be connected with described detecting unit 20 exports are anticipation power down bit Vth, current potential G1, GN of exporting described in the shift register cell 10 be connected with reset feedback unit 30 are resetted, to make current potential G1, GN that in each shift register cell 10, at least part of shift register cell 10 exports stable.
Preferably, described reset feedback unit is connected with each described shift register cell, during for detecting that the current potential that the shift register cell be connected with described detecting unit exports is anticipation power down bit when described detecting unit, the current potential exported described in each shift register cell is resetted.Therefore, when detecting unit 20 detects that the current potential that connected shift register cell 10 exports is anticipation power down bit Vth, control reset feedback unit 30 by this testing result to reset to current potential G1, GN of exporting described in each shift register cell 10, to make current potential G1, the GN exported described in each shift register cell 10 stablize, thus ensure the stable of whole shift register output.
As a kind of optimal way of the present embodiment, wherein, this detecting unit 20 comprises modular converter 21, this modular converter 21 is electrically connected with at least two shift register cells 10 and reset feedback unit 30, current potential for being exported by connected shift register cell 10 is converted to the first current potential EN, and controls the work of described reset feedback unit 30 by described first current potential EN.
Concrete, connect two shift register cells 10 for detecting unit 20 and be described.Due to the effective display area at display one frame picture, each shift register cell 10 will become low-potential signal after exporting a square-wave signal successively; When zone of transition, each shift register cell 10 will in work, and now the low-potential signal that exports of each shift register cell 10 will by pull-up gradually, until be 0V.Therefore, when one of them register cell exports square-wave signal, then illustrate and now must be in effective display area, the output one of another register cell is decided to be a low-potential signal, after modular converter 21 receives current potential G1, GN of these two shift register outputs the first current potential EN of changing out be electronegative potential, now this first current potential EN controls reset feedback unit 30 and does not carry out work, when current potential G1, GN that one of them register cell exports are low-potential signal, then illustrate and now also must be in effective display area, output potential G1, GN of another register cell are a low-potential signal or are a square-wave signal, and the first current potential EN that after now modular converter 21 receives current potential G1, GN that these two shift register cells 10 export, institute changes out is for being also logic low, as the current potential G1 that described two shift register cells 10 export, when GN is anticipation power down bit Vth, then illustrate and now must be in zone of transition, the current potential that then another shift register cell 10 exports must be similarly anticipation power down bit Vth, because anticipation power down bit Vth is relative to the current potential G1 exported in effective display area of register cell, GN is low-potential signal is raise to some extent, therefore anticipation power down bit Vth is defined as high potential signal, now modular converter 21 receives the current potential G1 that these two shift register cells 10 export, after GN the first current potential EN of changing out be also be logic high, thus control reset feedback unit 30 carries out work, by the current potential G1 of the output of each shift register cell 10, GN resets, that is the output of each shift register cell 10 will be dragged down, and then make this shift register output more stable.Meanwhile, Fig. 2 is sequential chart of the present utility model, and Fig. 3 is existing sequential chart, compare can find out by the sequential chart of Fig. 2 and Fig. 3, that existing output obviously saltus step occurs, and can find out that the output of zone of transition has had obvious improvement in fig. 2 in zone of transition.
Because AND circuit can export a logic-high signal at input two high potential signals, wherein an input low-potential signal then exports and is logic-low signal, and therefore modular converter 21 is preferably AND circuit in the present embodiment.
It should be noted that simultaneously, in the present embodiment, detecting unit 20 also can connect plural shift register cell 10, but it is simple in order to connect up, preferably detecting unit 20 connects two shift register cells 10, further, be connected with described detecting unit 20 two described shift register cells 10 be in the shift register cell 10 of multiple cascade first and last.Setting like this be because, to ensure that each shift register cell 10 has worked all in the effective display area of display one frame picture, more accurate to make in the reset of the output potential to zone of transition.
As the another kind of optimal way of the present embodiment, with above-mentioned optimal way unlike, this detecting unit 20 not only comprises modular converter 21, also comprise bi-directional logic level adjusting module 22, and this bi-directional logic level adjusting module 22 comprises multiple forward transmission channel and at least one reverse channel transmission simultaneously; Described bi-directional logic level adjusting module 22 and at least two shift register cells 10, and be connected with modular converter 21 respectively by different described forward transmission channels from the shift register cell 10 that described bi-directional logic level adjusting module 22 connects; Described bi-directional logic level adjusting module 22 is adjusted to first intermediate potential g1, gN for current potential G1, the GN exported by connected shift register cell 10, and first intermediate potential g1, gN is transferred to modular converter 21; Described modular converter 21 is also connected with a reverse channel transmission of described bi-directional logic level adjusting module 22, for described first intermediate potential g1, gN is adjusted to the second intermediate potential En; Described reverse channel transmission is used for described second intermediate potential En to be adjusted to the first current potential EN, exports to reset feedback unit 30.
Preferably, described reset feedback unit 30 comprises: multiple and each shift register cell 10 is switching transistor (namely a corresponding switching transistor of shift register cell 10) one to one, the grid of each switching transistor links together and connects reverse channel transmission, source electrode connects a shift register cell 10, and drain electrode is shorted together and connects low level current potential.Setting like this is because the structure of switching transistor is simple, easily controls.Further preferably, each switching transistor is N-type transistor, therefore when connected shift register is all exported anticipation power down bit Vth by modular converter 21 or perhaps AND circuit, change out a logic-high signal, thus each switching transistor is opened, simultaneously because the drain electrode of each switching transistor is shorted together and connects low level current potential, therefore the output of each shift register cell 10 can be dragged down, and then make this shift register output more stable.
Certainly, can also be preferred, transposition of partial register cell 10 is only had to be connected with switching transistor, such as say, feedback reset unit 30 only comprises two switching transistors, now namely only have two shift register cells 10 to connect the source electrode with each self-corresponding switching transistor in multiple shift register cell 10, the drain electrode of two switching transistors all connects reset signal, and grid connects reverse channel transmission.Passable understand, the current potential only having these two shift register cells 10 to export will be reset.
Connect two shift register cells 10 for detecting unit 20 to be equally described, now be understandable that, bi-directional logic level adjusting module 22 adopted in this approach can be three-channel bi-directional logic level adjusting module 22, namely comprises two forward transmission channels and a reverse channel transmission.
Concrete, the output potential G1 of one of them shift register cell 10 transfers to first forward transmission channel, the current potential GN of the output of another shift register cell 10 transfers to second forward transmission channel, and by exporting two the first intermediate potential g1 after two transmission channel adjustment, gN, two the first intermediate potential g1, gN converts the second intermediate potential En to through modular converter 21 again, second intermediate potential En transfers in reverse channel transmission and carries out adjusting rear output first current potential EN, now control reset feedback unit 30 by the first current potential EN whether to work.Wherein, when two first intermediate potentials g1, gN exporting are high level, modular converter 21 converts the second intermediate potential En to and is similarly high level again, after adjusting in reverse channel transmission, now export the first current potential EN is high level, therefore switching transistor is all opened, now each shift register cell 10 exports reset signal, because reset signal is low level current potential VGL, also just says that now each shift register cell 10 is reset output low level.
The reason why so arranged is, when two transmission channels all export anticipation power down bit Vth, because the magnitude of voltage of anticipation power down bit Vth is lower, now by forward transmission channel, this magnitude of voltage is amplified, namely become the high level signal that has relatively large magnitude of voltage, be the first intermediate potential g1, gN, now change (namely AND circuit) by modular converter 21 again and export a high level signal, be the second intermediate potential En, this high level signal adjusts (amplified by magnitude of voltage or reduce) further by reverse channel transmission again and obtains a stable high level signal, be the first current potential EN, thus worked by the first current potential EN control reset feedback unit 30, the output of each shift register cell 10 is resetted, namely drag down, to make the stable output of shift register.In like manner, when the output of these two shift register cells 10 is not anticipation power down bit Vth, carry out equally in a manner mentioned above changing, just the final reset feedback unit 30 that controls does not work, and is not described in detail at this.
Accordingly, the present embodiment additionally provides a kind of gate driver circuit, and it comprises above-mentioned shift register.
Accordingly, the present embodiment additionally provides a kind of array base palte, and it comprises above-mentioned gate driver circuit or above-mentioned shift register.
Accordingly, the present embodiment additionally provides a kind of display device, it comprises above-mentioned array base palte or above-mentioned gate driver circuit or above-mentioned shift register, and this display device can be: any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, oled panel, mobile phone, panel computer, televisor, display, notebook computer, digital album (digital photo frame), navigating instrument.
Be understandable that, the illustrative embodiments that above embodiment is only used to principle of the present utility model is described and adopts, but the utility model is not limited thereto.For those skilled in the art, when not departing from spirit of the present utility model and essence, can make various modification and improvement, these modification and improvement are also considered as protection domain of the present utility model.
Claims (14)
1. a shift register, it comprises the shift register cell of multiple cascade, it is characterized in that, described shift register also comprises: detecting unit and reset feedback unit; Wherein,
Described detecting unit connects at least two shift register cells, for detecting the current potential that connected described shift register cell exports, and this testing result is transferred to described reset feedback unit;
Described reset feedback unit is connected with shift register cell described at least one, during for detecting that the current potential that the shift register cell be connected with described detecting unit exports is anticipation power down bit when described detecting unit, the current potential exported described in the shift register cell be connected with described reset feedback unit is resetted; Wherein, the current potential that exports in zone of transition for each described shift register cell of described anticipation power down bit.
2. shift register according to claim 1, it is characterized in that, described reset feedback unit is connected with each described shift register cell, during for detecting that the current potential that the shift register cell be connected with described detecting unit exports is anticipation power down bit when described detecting unit, the current potential exported described in each shift register cell is resetted.
3. shift register according to claim 1, is characterized in that, described detecting unit comprises modular converter,
Described modular converter is electrically connected with at least two shift register cells and reset feedback unit, whether the current potential for being exported by connected shift register cell is converted to the first current potential, and worked by the feedback unit that resets described in described first control of Electric potentials.
4. shift register according to claim 3, is characterized in that, described detecting unit also comprises bi-directional logic level adjusting module, and described bi-directional logic level adjusting module comprises multiple forward transmission channel and at least one reverse channel transmission;
Described bi-directional logic level adjusting module is connected with at least two shift register cells, and is connected with modular converter respectively by different described forward transmission channels from the shift register cell that described bi-directional logic level adjusting module connects; Described bi-directional logic level adjusting module is used for the current potential that connected shift register cell exports to be adjusted to the first intermediate potential, and the first intermediate potential is transferred to modular converter;
Described modular converter is also connected with a reverse channel transmission of described bi-directional logic level adjusting module, for described first intermediate potential is adjusted to the second intermediate potential;
Described reverse channel transmission is used for described second intermediate potential to be adjusted to the first current potential, exports to reset feedback unit.
5. shift register according to claim 4, is characterized in that, described modular converter is AND circuit.
6. shift register according to claim 4, is characterized in that, described reset feedback unit comprises: at least one switching transistor,
The grid of each described switching transistor all connects anti-phase output channel, and source electrode connects a shift register cell, and each described shift register cell is connected with the source electrode of a described switching transistor at the most, and drain electrode connects reset signal.
7. shift register according to claim 6, is characterized in that, described reset feedback unit comprises multiple and each shift register cell switching transistor one to one,
The grid of described switching transistor connects anti-phase output channel, and source electrode connects shift register cell, and drain electrode connects reset signal.
8. the shift register according to claim 6 or 7, is characterized in that, described switching transistor is N-type transistor.
9. the shift register according to claim 6 or 7, is characterized in that, described first current potential is high level, and described reset signal is low level.
10. shift register as claimed in any of claims 1 to 7, is characterized in that, described detecting unit connects two described shift register cells.
11. shift registers according to claim 10, is characterized in that, two the described shift register cells be connected with described detecting unit be in the shift register cell of multiple cascade first and last.
12. 1 kinds of gate driver circuits, is characterized in that, described gate driver circuit comprises the shift register in claim 1 to 11 described in any one.
13. 1 kinds of array base paltes, is characterized in that, described array base palte comprises gate driver circuit according to claim 12.
14. 1 kinds of display device, is characterized in that, described display device comprises array base palte according to claim 13.
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| CN201420797059.3U CN204257182U (en) | 2014-12-15 | 2014-12-15 | Shift register, gate driver circuit, array base palte, display device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104392705A (en) * | 2014-12-15 | 2015-03-04 | 京东方科技集团股份有限公司 | Shifting register, grid driving circuit, array substrate and display device |
| CN106652933B (en) * | 2016-11-18 | 2021-02-26 | 南京中电熊猫液晶显示科技有限公司 | Grid drive circuit with forward and reverse scanning function |
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2014
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104392705A (en) * | 2014-12-15 | 2015-03-04 | 京东方科技集团股份有限公司 | Shifting register, grid driving circuit, array substrate and display device |
| WO2016095544A1 (en) * | 2014-12-15 | 2016-06-23 | Boe Technology Group Co., Ltd. | Shift register, gate driving circuit, array substrate, and display apparatus |
| US10573400B2 (en) | 2014-12-15 | 2020-02-25 | Boe Technology Group Co., Ltd. | Shift register, gate driving circuit, array substrate, and display apparatus |
| CN106652933B (en) * | 2016-11-18 | 2021-02-26 | 南京中电熊猫液晶显示科技有限公司 | Grid drive circuit with forward and reverse scanning function |
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Granted publication date: 20150408 Termination date: 20211215 |