CN108242228B - Grid scanning driving circuit - Google Patents
Grid scanning driving circuit Download PDFInfo
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- CN108242228B CN108242228B CN201810082089.9A CN201810082089A CN108242228B CN 108242228 B CN108242228 B CN 108242228B CN 201810082089 A CN201810082089 A CN 201810082089A CN 108242228 B CN108242228 B CN 108242228B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- General Physics & Mathematics (AREA)
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- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention discloses a grid scanning drive circuit, which comprises N (N is greater than 4, and N is a positive integer) stage drive circuit units; the nth (1 ≦ N, and N is a positive integer) stage driving circuit unit includes a pull-up control module, a pull-up module, a sustain control node generating module, a pull-up control node sustain module, and an output node sustain module; the maintaining control node generating module inputs a forward scanning control signal and a reverse scanning control signal which are mutually reverse, generates the maintaining control signal to control the maintaining control node, and after the scanning signals during forward scanning and reverse scanning are output, the first signal pulse width of the maintaining control node is the same as the preset width, so that the first pulse width of the maintaining control node is prevented from being narrowed, the pull-up control node maintaining module can immediately perform intermittent low potential maintaining on the pull-up control node, the scanning signals are prevented from being started mistakenly, and the reliability of the circuit is improved.
Description
Technical Field
The invention relates to the field of liquid crystal display, in particular to a grid scanning driving circuit.
Background
The Gate scan lines of the flat panel display are usually driven by a Gate IC (integrated circuit), and the integrated Gate scan driving circuit (GDM) is a technology of directly constructing the Gate scan driving circuit on the array substrate by using the existing thin film transistor array substrate manufacturing process, and has the effects of reducing the cost, reducing the process flow and reducing the panel frame width. With the development of products and technologies, the requirements of flat panel displays on gate scan driving circuits are increasing, and one of them is to have both forward scan and reverse scan functions.
As shown in fig. 1, the circuit diagram of a conventional bidirectional scan gate driving circuit includes a pull-up control module 1, a pull-up module 2, a sustain control node generation module 3, a pull-up control node sustain module 4, an output node sustain module 5, an auxiliary sustain module 6, a clearing module 7, and a bootstrap capacitor C1. The pull-up control module 1 and the maintaining control node generating module 3 are controlled by signals in the front-stage and the rear-stage driving circuit units at the same time, the thin film transistors M1 and M9 in the pull-up control module 1 are symmetrical, and the thin film transistors M5 and M7 in the maintaining control node generating module 3 are symmetrical. The scanning direction of the gate scan driving circuit is controlled by a pair of constant voltage signals of a forward scan control signal U2D and a reverse scan control signal D2U, which are opposite to each other, and the forward scan is performed when U2D is at a high level and D2U is at a low level, and the reverse scan is performed otherwise.
During the operation of the gate scan driving circuit, it is necessary to inhibit the holding of the control node netBn output during the two phases of the precharge (Gn-2 output phase for the forward scan) and the pull-up (Gn output phase) of the pull-up control node netAn in order to prevent the netAn from being pulled down by the netBn during the precharge and pull-up phases to affect the output of the scan signal Gn. As shown in fig. 2 and 3, during the forward scan, M6 in the sustain control node generating module 3 of the gate scan driving circuit is responsible for prohibiting the sustain control node netBn output during the high-level period of the pull-up control node netAn (i.e. the forward scan precharge Gn-2 output and the pull-up Gn output), M6A prohibits the sustain control node netBn output during the forward scan precharge (Gn-2 output), and M6B prohibits the sustain control node netBn output during the period after the scan signal output (Gn +2 output); in the reverse scan, M6 is responsible for prohibiting the output of the sustain control node netBn during the high-potential period of the pull-up control node netAn (i.e., the reverse scan precharge Gn +2 output and the pull-up Gn output), M6B prohibits the output of the sustain control node netBn during the forward scan precharge (Gn +2 output), and M6A prohibits the output of the sustain control node netBn during the period after the scan signal is output (Gn-2 output). M6A and M6B additionally generate unnecessary actions due to the symmetrical design of the sustain control node generating module 3 for the forward and backward scan function, and this action causes the first netBn pulse width after the output of the scan signal Gn to become narrow, as shown in fig. 2, the signal pulse width of the sustain control node netBn is preset to a, which is the first pulse width after the output of the scan signal Gn is b, where b < a. This phenomenon affects the function of the pull-up control node sustain module 4, and causes the sustain capability of the driving circuit unit after outputting the scan signal Gn to be weak, which may cause the scan signal Gn to be turned on erroneously, thereby causing the reliability of the circuit to be poor.
Disclosure of Invention
In order to solve the above technical problem, the present invention provides a gate scan driving circuit, which makes the first pulse width of the sustain control node after the scan signal is output be the same as the preset width, thereby improving the reliability of the circuit.
The technical scheme provided by the invention is as follows:
the invention discloses a grid scanning driving circuit, which comprises N (N is greater than 4, and N is a positive integer) level driving circuit units; the nth (1 ≦ N, and N is a positive integer) stage driving circuit unit includes a pull-up control module, a pull-up module, a sustain control node generating module, a pull-up control node sustain module, and an output node sustain module; the pull-up control module, the pull-up module, the maintenance control node generation module and the pull-up control node maintenance module are connected with the pull-up control node; the maintaining control node generating module, the pull-up control node maintaining module and the output node maintaining module input low level in specific working time; the pull-up module and the output node maintaining module are connected with the scanning signal line of the current stage, and the scanning signal line outputs a scanning signal; the maintaining control node generating module and the pull-up control node maintaining module are connected with the maintaining control node; the sustain control node generating module of the nth stage driving circuit unit inputs a forward scan control signal and a reverse scan control signal which are mutually reverse, generates a sustain control signal to control the sustain control node, and after the scan signals during forward scan and reverse scan are output, the pulse width of the first signal of the sustain control node is the same as the preset width.
Preferably, the sustain control node generating module of the nth stage driving circuit unit includes a fifth thin film transistor, a sixth thin film transistor, and a seventh thin film transistor; a control end of the fifth thin film transistor inputs a first clock signal, and two path ends of the fifth thin film transistor are respectively connected with a forward scanning control signal and a maintaining control node of the nth-stage drive circuit unit; the control end of the sixth thin film transistor is connected with the pull-up control node of the nth-stage drive circuit unit, and two path ends of the sixth thin film transistor are respectively connected with the maintaining control node and the low level of the nth-stage drive circuit unit; the control end of the seventh thin film transistor inputs the third clock signal, and two path ends of the seventh thin film transistor are respectively connected with the maintaining control node of the nth-stage driving circuit unit and the reverse scanning control signal.
Preferably, the sustain control node generating module of the nth stage driving circuit unit further includes a fourteenth thin film transistor and a fifteenth thin film transistor; a control end of the fourteenth thin film transistor inputs a first control signal, and two path ends of the fourteenth thin film transistor are respectively connected with a maintaining control node and a reverse scanning control signal of the nth-stage driving circuit unit; the control end of the fifteenth thin film transistor inputs the second control signal, and two path ends of the fifteenth thin film transistor are respectively connected with the maintaining control node of the nth-stage driving circuit unit and the forward scanning control signal.
Preferably, the pull-up control module of the nth stage driving circuit unit includes a first thin film transistor and a ninth thin film transistor; a control end of the first thin film transistor inputs a first control signal, and two path ends of the first thin film transistor are respectively connected with a forward scanning control signal and a pull-up control node of the nth-stage drive circuit unit; and the control end of the ninth thin film transistor inputs a second control signal, and two path ends of the ninth thin film transistor are respectively connected with the reverse scanning control signal and the pull-up control node of the nth-stage drive circuit unit.
Preferably, when the nth-stage driving circuit unit is a first-stage driving circuit unit, the first control signal is a first start signal; when the nth-stage driving circuit unit is not the first-stage driving circuit unit, the first control signal is a gate scanning signal of the preceding-stage driving circuit unit;
when the nth-stage driving circuit unit is a tail-stage driving circuit unit, the second control signal is a second starting signal; when the nth stage driving circuit unit is not the tail stage driving circuit unit, the second control signal is a gate scanning signal of the rear stage driving circuit unit.
Preferably, the pull-up control node maintaining module of the nth stage driving circuit unit includes an eighth thin film transistor; and the control end of the eighth thin film transistor is connected with the maintaining control node of the nth-stage drive circuit unit, and two path ends of the eighth thin film transistor are respectively connected with the pull-up control node and the low level of the nth-stage drive circuit unit.
Preferably, the pull-up module of the nth stage driving circuit unit includes a tenth thin film transistor; and the control end of the tenth thin film transistor is connected with the maintaining control node of the nth stage driving circuit unit, and two channel ends of the tenth thin film transistor are respectively connected with the second clock signal and the scanning signal line of the nth stage driving circuit unit.
Preferably, the output node maintaining module of the nth stage driving circuit unit includes an eleventh thin film transistor; a control end of the eleventh thin film transistor is used for inputting a fourth clock signal, and two path ends of the eleventh thin film transistor are respectively connected with a scanning signal line and a low level of the nth-stage driving circuit unit.
Preferably, the nth stage driving circuit unit further includes a clearing module; the emptying module comprises a second thin film transistor, a third thin film transistor and a twelfth thin film transistor; the control end of the second thin film transistor inputs an emptying signal, and two path ends of the second thin film transistor are respectively connected with a pull-up control node and a low level of the nth-stage drive circuit unit; the control end of the third thin film transistor inputs an emptying signal, and two path ends of the third thin film transistor are respectively connected with a maintaining control node and a low level of the nth-stage driving circuit unit; and the control end of the twelfth thin film transistor inputs an emptying signal, and two path ends of the twelfth thin film transistor are respectively connected with a scanning signal line and a low level of the nth-stage driving circuit unit.
Preferably, the nth stage driving circuit unit further includes an auxiliary sustain module including a fourth thin film transistor and a thirteenth thin film transistor; a control end of the fourth thin film transistor inputs a first starting signal, and two path ends of the fourth thin film transistor are respectively connected with a pull-up control node and a low level; the control end of a fourth thin film transistor in the 1 st, 2 nd and 3 rd stage driving circuit unit inputs low level; a control end of the thirteenth thin film transistor inputs a second starting signal, and two path ends of the thirteenth thin film transistor are respectively connected with the upper pull control node and the low level; wherein, the control end of the thirteenth thin film transistor in the N-2, N-1 and N-stage driving circuit unit inputs low level.
Compared with the prior art, the invention can bring at least one of the following beneficial effects:
1. the first pulse width is the same as the preset width after the scanning signals are output during reverse scanning and forward scanning, so that the first pulse width of the maintaining control node is prevented from being narrowed, an upward control node maintaining module can immediately perform intermittent low potential maintenance on the upward control node, and the reliability of the circuit is improved;
2. the output of the maintenance control node netBn can be forbidden only in the stages of forward scan precharge (Gn-2 output) and reverse scan precharge (Gn +2 output) and can not be forbidden after the scan signal is output by M6A and M6B in the maintenance control node generation module in the forward scan process, so that the signal pulse width of the maintenance control node netBn is prevented from narrowing;
3. the display panel can support bidirectional scanning, the number of the thin film transistors is small, the layout space is saved, and the display panel is favorably narrowed.
Drawings
The present invention will be further described in the following detailed description of preferred embodiments, which is to be read in connection with the accompanying drawings.
FIG. 1 is a circuit diagram of a conventional bidirectional scan gate driving circuit;
FIG. 2 is a schematic diagram of driving waveforms of the gate driving circuit shown in FIG. 1 during forward scanning;
FIG. 3 is a schematic diagram of driving waveforms of the gate driving circuit shown in FIG. 1 during a reverse scan;
FIG. 4 is a schematic diagram of a gate scan driving circuit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of another embodiment of a gate scan driving circuit according to the present invention;
FIG. 6 is a circuit diagram of a first embodiment of a gate scan driving circuit according to the present invention;
FIG. 7 is a schematic diagram of driving waveforms of the circuit shown in FIG. 6 during forward scanning;
FIG. 8 is a schematic diagram of the driving waveforms of the circuit shown in FIG. 6 during a reverse scan;
FIG. 9 is a circuit diagram of a second embodiment of a gate scan driving circuit according to the present invention;
fig. 10 is a schematic structural diagram of a display device using the gate driving circuit of the present invention.
The reference numbers illustrate:
1. the system comprises an upper pulling control module, 2, an upper pulling module, 3, a maintaining control node generating module, 4, an upper pulling control node maintaining module, 5, an output node maintaining module, 6, an auxiliary maintaining module, 7 and an emptying module;
m1, a first thin film transistor, M2, a second thin film transistor, M3, a third thin film transistor, M5, a fifth thin film transistor, M6, a sixth thin film transistor, M7, a seventh thin film transistor, M8, an eighth thin film transistor, M10, a tenth thin film transistor, M11, an eleventh thin film transistor, M12, a twelfth thin film transistor, M4A, a fourth thin film transistor, M4B, a thirteenth thin film transistor, M6A, a fourteenth thin film transistor, M6B, a fifteenth thin film transistor, C1, a bootstrap capacitor;
gn, a scan signal of the nth-stage driving circuit unit, netAn, a pull-up control node, netBn, a sustain control node, VGH, high level, VSS, low level, CKm-1, a first clock signal, CKm, a second clock signal, CKm +1, a third clock signal, CKm +2, a fourth clock signal, a scan signal of the Gn-2, an n-2 th-stage driving circuit unit, a scan signal of the Gn +2, an n +2 th-stage driving circuit unit,
c L R, clear reset signal, U2D, forward scan control signal, D2U, reverse scan control signal, GSP1, first enable signal, GSP3, second enable signal.
Detailed Description
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will be made with reference to the accompanying drawings. It is obvious that the drawings in the following description are only some examples of the invention, and that for a person skilled in the art, other drawings and embodiments can be derived from them without inventive effort.
For the sake of simplicity, the drawings only schematically show the parts relevant to the present invention, and they do not represent the actual structure as a product. In addition, in order to make the drawings concise and understandable, components having the same structure or function in some of the drawings are only schematically illustrated or only labeled. In this document, "one" means not only "only one" but also a case of "more than one".
The gate scan driving circuit of the present invention includes N (N >4, where N is a positive integer) stage driving circuit units, and as shown in fig. 4, the nth stage (1 ≦ N, where N is a positive integer) driving circuit unit includes a pull-up control module 1, a pull-up module 2, a sustain control node generating module 3, a pull-up control node sustain module 4, and an output node sustain module 5.
The pull-up control module 1, the pull-up module 2, the maintenance control node generation module 3 and the pull-up control node maintenance module 4 are connected to the pull-up control node netAn; the maintaining control node generating module 3, the pull-up control node maintaining module 4 and the output node maintaining module 5 all input low level VSS; the pull-up module 2 and the output node maintaining module 5 are connected to a scanning signal line of the current stage, and the scanning signal line outputs a scanning signal Gn; the maintenance control node generating module 3 and the pull-up control node maintaining module 4 are connected to the maintenance control node netBn.
Each thin film transistor includes a control terminal and two via terminals, in the following embodiments, the control terminal is a gate, one of the via terminals is a source, and the other via terminal is a drain. When the control terminal is given a high level, the source and the drain are connected through the semiconductor layer, and the thin film transistor is in an on state.
It should be noted that, the circuit diagrams in the following embodiments are all left-side gate scan driving circuits or right-side gate scan driving circuits under a non-left-right staggered (interlace) driving architecture, but the application of the gate scan driving circuit in the present invention is not limited to this manner, and the gate scan driving circuit can be applied to any mode of driving architecture, including a non-left-right staggered double-side driving architecture, a single-side driving architecture, and the like.
Under the non-left-right staggered double-side driving architecture, the clock signals adopted by the gate scanning driving circuits on both sides are the same and are M, and the clock signals are represented as CKm (M is 1, 2, … … and M); the following embodiments adopt a left-right staggered driving scheme, where the number of clock signals in a single-side gate scan driving circuit is M, the total number of clock signals on both sides is 2M, and the single-side clock signal is represented by CKm (M is 1, 3, … …, 2M-1, or M is 2, 4, … …, 2M).
Waveforms of the 4 clock signals CK1, CK3, CK5, CK7, CK1, CK3, CK5 and CK7 selected in the following embodiments are shown in fig. 7 and 8, and when waveforms of CK1, CK3, CK5 and CK7 are sequentially generated, the clock signal input mode is called as clock signal positive sequence input; when the waveforms of CK1, CK3, CK5 and CK7 are generated in a reverse order, this clock signal input mode is referred to as clock signal reverse order input. It should be noted that the conventional functional modifications of selecting other numbers and waveforms of clock signals and other clock signal input modes on the basis of the present invention are all within the scope of the present invention.
As shown in fig. 4, the sustain control node generating module 3 of the nth stage driving circuit unit is controlled by a pair of mutually inverted signals, i.e., a forward scan control signal U2D and a reverse scan control signal D2U, and is responsible for generating a sustain control signal to control the sustain control node netBn. After the scanning signal Gn is output during the reverse scanning and the forward scanning, the first signal pulse width of the maintenance control node netBn is the same as the preset width a, and the first pulse width of the maintenance control node netBn is prevented from being narrowed, so that the pull-up control node maintenance module 4 can immediately perform intermittent low potential maintenance on the pull-up control node netAn, and the reliability of the circuit is improved.
The pull-up control module 1 is controlled by a pair of mutually inverted signals, i.e., a forward scan control signal U2D and a reverse scan control signal D2U, and performs charging and discharging for controlling forward and reverse scanning.
The pull-up module 2 is controlled by a pull-up control node netAn, receives the first clock signal CKm as an input, and is connected to a scanning signal line of the present stage driving circuit unit, and the scanning signal line outputs a scanning signal Gn.
The pull-up control node maintaining module 4 is controlled by the maintaining control node netBn to maintain the pull-up control node netAn.
The output node sustain module 5 is responsible for sustaining the scan signal Gn of the nth stage driving circuit unit.
Preferably, the technical solution is improved to obtain an improved solution, and the gate scan driving circuit further includes an auxiliary sustain module 6 and an emptying module 7.
The auxiliary maintaining module 6 is responsible for maintaining the pull-up control node netAn during the startup phase in the forward scan and reverse scan pictures.
The clearing module 7 is responsible for performing clearing reset operations on the pull-up control node netAn, the maintenance control node netBn and the scan signal Gn at this level after each frame is finished.
It should be noted that, in the present invention, the auxiliary maintaining module 6 and the clearing module 7 are additional functional modules according to actual use requirements, whether the circuit includes the above modules is not limited, and other functional modules may be added to meet the actual requirements, and conventional functional improvements on this basis should fall into the protection scope of the present invention.
Based on the same inventive concept, another gate scan driving circuit of the present invention has a structure as shown in fig. 5. The gate scan driving circuit shown in fig. 5 is improved on the basis of the gate scan driving circuit shown in fig. 4, and the specific improvement point is that the sustain control node generating module 3 of the nth stage driving circuit unit further includes: the fourteenth thin film transistor M6A for disabling the output of the sustain control node during the period when the n-2 th stage circuit unit outputs the scan signal in the forward scan process, and the fifteenth thin film transistor M6B for disabling the output of the sustain control node during the period when the n +2 th stage circuit unit outputs the scan signal in the reverse scan process can assist the sixth thin film transistor M6 and more effectively prevent the scan signal Gn from being turned on erroneously.
The grid scanning driving circuit can support bidirectional scanning; after the scanning signal Gn during forward scanning and reverse scanning is output, the first signal pulse width of the control node netBn is maintained to be the same as the preset width a, so that the pull-up control node maintaining module 4 can immediately perform intermittent low potential maintenance on the pull-up control node netAn, the scanning signal Gn is prevented from being started by mistake, and the reliability of the circuit is improved; and the number of the thin film transistors is small, so that the layout space is saved, and the frame of the display panel is favorably narrowed.
The circuit structures of each stage of driving circuit units in the present invention are the same, and the difference is only that the signals input by some thin film transistors are different, and the circuit structure of the nth (1 ≦ N) stage is mainly described in detail below.
In the left-right interleaved driving scheme, the first-stage driving circuit unit in the following embodiments refers to: a first-stage drive circuit unit (a 1 st-stage drive circuit unit) of the left-side gate scanning drive circuit and a first-stage drive circuit unit (a 2 nd-stage drive circuit unit) of the right-side gate scanning drive circuit; the tail stage driving circuit unit referred to in the following embodiments refers to: a tail stage driving circuit unit (an N-1 th stage driving circuit unit) of the left side gate scanning driving circuit and a tail stage driving circuit unit (an nth stage driving circuit unit) of the right side gate scanning driving circuit.
In the non-left-right staggered dual-edge driving scheme, the first-stage driving circuit unit in the following embodiments refers to: a first-stage drive circuit unit (a 1 st-stage drive circuit unit) of the left-side gate scanning drive circuit and a first-stage drive circuit unit (a 1 st-stage drive circuit unit) of the right-side gate scanning drive circuit; the tail stage driving circuit unit referred to in the following embodiments refers to: a tail stage driving circuit unit (nth stage driving circuit unit) of the left side gate scanning driving circuit and a tail stage driving circuit unit (nth stage driving circuit unit) of the right side gate scanning driving circuit.
The present invention will be described in detail with reference to specific examples.
The first embodiment is as follows:
as shown in fig. 6, which is a circuit diagram of a first embodiment of a gate scan driving circuit, the nth stage driving circuit unit includes a pull-up control module 1, a pull-up module 2, a sustain control node generation module 3, a pull-up control node sustain module 4, an output node sustain module 5, and a bootstrap capacitor C1.
The pull-up control module 1, the pull-up module 2, the maintenance control node generation module 3 and the pull-up control node maintenance module 4 are connected to the pull-up control node netAn; the maintaining control node generating module 3, the pull-up control node maintaining module 4 and the output node maintaining module 5 all input low level VSS; the pull-up module 2 and the output node maintaining module 5 are connected to a scanning signal line of the current stage, and the scanning signal line outputs a scanning signal Gn; the maintenance control node generating module 3 and the pull-up control node maintaining module 4 are connected to the maintenance control node netBn.
As shown in fig. 6, in detail, the sustain control node generating module 3 includes a fifth thin film transistor M5, a sixth thin film transistor M6, and a seventh thin film transistor M7.
The control terminal of the fifth thin film transistor M5 inputs the first clock signal CKm-1, two path terminals of the fifth thin film transistor M5 are respectively connected to the forward scan control signal U2D and the sustain control node netBn, and the fifth thin film transistor M5 intermittently charges the sustain control node netBn during the forward scan and intermittently discharges the sustain control node netBn during the reverse scan.
The control terminal of the seventh thin film transistor M7 inputs the third clock signal CKm +1, two path terminals of the seventh thin film transistor M7 are respectively connected to the reverse scan control signal D2U and the sustain control node netBn, the seventh thin film transistor M7 intermittently discharges the sustain control node netBn during the forward scan process and intermittently charges the sustain control node netBn during the reverse scan process.
The control terminal of the sixth tft M6 is connected to the pull-up control node netAn, two path terminals of the sixth tft M6 are respectively connected to the sustain control node netBn and the low level VSS, and the sixth tft M6 is configured to disable the output of the sustain control node netBn during the operation of the current stage of the circuit unit.
During forward scanning, the forward scanning control signal U2D is a high level signal, and the reverse scanning control signal D2U is a low level signal; in the reverse scan, the forward scan control signal U2D is a low signal, and the reverse scan control signal D2U is a high signal.
As shown in fig. 6, in detail, the pull-up control module 1 includes a first thin film transistor M1 and a ninth thin film transistor M9.
A control end of the first thin film transistor M1 inputs a first control signal, and two path ends of the first thin film transistor M1 are respectively connected with the forward direction scanning control signal U2D and the pull-up control node netAn of the nth stage driving circuit unit; the first thin film transistor M1 charges the pull-up control node netAn in the forward direction scan and discharges the pull-up control node netAn in the reverse direction scan.
A control end of the ninth thin film transistor M9 inputs the second control signal, and two path ends of the ninth thin film transistor M9 are respectively connected to the reverse scan control signal D2U and the pull-up control node netAn of the nth stage driving circuit unit; the ninth thin film transistor M9 discharges the pull-up control node netAn in the forward direction scan and charges the pull-up control node netAn in the reverse direction scan.
When the nth-stage driving circuit unit is a first-stage driving circuit unit, the first control signal is a first start signal GSP 1; when the nth-stage driving circuit unit is not the first-stage driving circuit unit, the first control signal is a gate scanning signal of the preceding-stage driving circuit unit;
when the nth stage driving circuit unit is a tail stage driving circuit unit, the second control signal is a second start signal GSP 3; when the nth stage driving circuit unit is not the tail stage driving circuit unit, the second control signal is a gate scanning signal of the rear stage driving circuit unit.
Specifically, in the left-right staggered driving architecture, when n is less than or equal to 2, the first control signal is the first start signal GSP 1; when n >2, the first control signal is a gate scan signal of a previous stage driving circuit unit, preferably, a gate scan signal Gn-2 of an n-2 th stage driving circuit unit. When N < N-1, the second control signal is a gate scan signal of the subsequent stage driving circuit unit, preferably, a gate scan signal Gn +2 of the (N + 2) th stage driving circuit unit; when N ≧ N-1, the second control signal is the second start signal GSP 3.
In the non-left-right staggered dual-edge driving scheme, when n is equal to 1, the first control signal is the first start signal GSP 1; when n >1, the first control signal is a gate scan signal of a previous stage driving circuit unit, preferably, a gate scan signal Gn-1 of an n-1 th stage driving circuit unit. When N < N, the second control signal is a gate scan signal of the subsequent stage driving circuit unit, preferably, a gate scan signal Gn +1 of the (N + 1) th stage driving circuit unit; when N is equal to N, the second control signal is the second start signal GSP 3.
It should be noted that, on the basis of the present invention, the conventional functional improvement of selecting the (n-a) th stage gate scan signal as the gate scan signal of the previous stage driving circuit unit and selecting the (n + a) th stage gate scan signal as the gate scan signal of the next stage driving circuit unit (a can be set according to the circuit design and the driving architecture) should fall into the protection scope of the present invention.
The scanning direction of the gate scan driving circuit is controlled by a pair of constant voltage signals of opposite phases, i.e., a forward scan control signal U2D and a reverse scan control signal D2U, and forward scanning is performed when the forward scan control signal U2D is at a high level and the reverse scan control signal D2U is at a low level, and reverse scanning is performed otherwise.
As shown in fig. 6, in particular, the pull-up module 2 includes a tenth thin film transistor M10. A control terminal of the tenth tft M10 is connected to the pull-up control node netAn, and two path terminals of the tenth tft M10 are respectively connected to the second clock signal CKm and the scan signal line of the current stage. The tenth thin film transistor M10 is used for the output of the present-stage scan signal Gn.
As shown in fig. 6, in particular, the pull-up control node maintaining module 4 includes an eighth tft M8. The control terminal of the eighth tft M8 is connected to the sustain control node netBn, and the two pass terminals of the eighth tft M8 are respectively connected to the pull control node netAn and the low level VSS. The eighth thin film transistor M8 maintains the potential of the pull-up control node netAn under the control of the maintenance control node netBn.
As shown in fig. 6, in detail, the output node maintaining module 5 includes an eleventh thin film transistor M11. A control terminal of the eleventh thin film transistor M11 receives the fourth clock signal CKm +2, and two path terminals of the eleventh thin film transistor M11 are connected to the low level VSS and the present-stage scanning signal line, respectively. The eleventh thin film transistor M11 is used to maintain the present-stage scan signal Gn.
As shown in fig. 6, in particular, the nth stage driving circuit unit further includes an auxiliary sustain module 6, and the auxiliary sustain module 6 includes a fourth thin film transistor M4A and a thirteenth thin film transistor M4B.
The control terminal of the fourth tft M4A receives the first start signal GSP1, and two path terminals of the fourth tft M4A are connected to the pull-up control node netAn and the low level VSS, respectively. The control terminal of the fourth thin film transistor M4A in the 1 st, 2 nd, 3 rd stage driving circuit unit inputs the low level VSS. The fourth thin film transistor M4A is used to maintain the pull-up control node netAn during the start-up phase in the forward scan.
The second start signal GSP3 is inputted to a control terminal of the thirteenth thin film transistor M4B, and two path terminals of the thirteenth thin film transistor M4B are connected to the pull-up control node netAn and the low level VSS, respectively. The control terminal of the thirteenth thin film transistor M4B in the nth-2, nth-1 and nth-stage driving circuit units is inputted with the low level VSS. The thirteenth thin film transistor M4B is used to sustain the pull-up control node netAn during the start-up phase in the reverse scan.
As shown in fig. 6, the nth stage driving circuit unit further includes a clearing module 7, and the clearing module 7 includes a second thin film transistor M2, a third thin film transistor M3, and a twelfth thin film transistor M12.
The control terminal of the second thin film transistor M2 inputs the blanking signal C L R, two path terminals of the second thin film transistor M2 are respectively connected to the low level VSS and the pull-up control node netAn, and the second thin film transistor M2 is configured to perform a blanking reset operation on the pull-up control node netAn after each frame of the picture is finished.
The control terminal of the third tft M3 inputs the blanking signal C L R, two path terminals of the third tft M3 are respectively connected to the low level VSS and the sustain control node netBn, and the third tft M3 is configured to perform a blanking reset operation on the sustain control node netBn after each frame is finished.
The control terminal of the twelfth tft M12 inputs the clear signal C L R, two path terminals of the twelfth tft M12 are respectively connected to the low level VSS and the scan signal line of the current stage, and the twelfth tft M12 is configured to perform a clear reset operation on the scan signal Gn of the current stage after each frame of the image is finished.
As shown in fig. 6, a bootstrap capacitor C1 is connected between the pull-up control node netAn and the present-stage scan signal line, and is used for raising and stabilizing the potential of the pull-up control node netAn during the action.
Fig. 7 is a schematic diagram of a driving waveform of the circuit shown in fig. 6 during forward scanning:
GSP1 is the first enable signal, and is also responsible for enabling in the forward scan;
GSP3 is the second enable signal, and is responsible for enabling during the reverse scan;
CK1, CK2, CK3 and CK4 are clock signals and are output in a positive sequence during forward scanning;
c L R is a clear reset signal, which is mainly responsible for clearing charges from the internal nodes of the circuit when each frame is finished and the circuit is turned on and off;
VSS is a low level VSS, which is mainly responsible for providing a low level of the scanning signal Gn;
U2D is a forward scanning control signal, which is a constant voltage high potential signal during forward scanning;
D2U is a reverse scan control signal, which is a constant voltage low potential signal during forward scan;
the other waveforms shown, such as netAn and netBn, are output waveforms of nodes inside the circuit, and Gn-2, Gn, and Gn +2 are waveforms of a scan signal of a preceding stage driver circuit unit, a scan signal of the present stage, and a scan signal of a subsequent stage driver circuit unit corresponding to the nth stage driver circuit unit, respectively.
Fig. 8 is a schematic diagram of a driving waveform of the circuit shown in fig. 6 at the time of reverse scanning:
GSP1 is the first enable signal, and is also responsible for enabling in the forward scan;
GSP3 is the second enable signal, and is responsible for enabling during the reverse scan;
CK1, CK2, CK3 and CK4 are clock signals, and are output in reverse order when scanning is performed reversely;
c L R is a clear reset signal, which is mainly responsible for clearing charges from the internal nodes of the circuit when each frame is finished and the circuit is turned on and off;
VSS is a low level VSS, which is mainly responsible for providing a low level of the scanning signal Gn;
U2D is a forward direction scanning control signal, and is a constant voltage low potential signal during reverse direction scanning;
D2U is a reverse scan control signal, which is a constant voltage high potential signal during reverse scan;
the other waveforms shown, such as netAn and netBn, are output waveforms of nodes inside the circuit, and Gn-2, Gn, and Gn +2 are waveforms of a scan signal of a preceding stage driver circuit unit, a scan signal of the present stage, and a scan signal of a subsequent stage driver circuit unit corresponding to the nth stage driver circuit unit, respectively.
Example two:
fig. 9 is a circuit diagram of a second embodiment of a gate scan driving circuit according to the invention. The second embodiment is improved on the basis of the first embodiment, and the specific improvement points are as follows:
the sustain control node generating module 3 further includes a fourteenth thin film transistor M6A and a fifteenth thin film transistor M6B.
A control terminal of the fourteenth thin film transistor M6A receives the first control signal, and two path terminals of the fourteenth thin film transistor M6A are respectively connected to the net bn of the nth stage driving circuit unit and the reverse scan control signal D2U. The fourteenth thin film transistor M6A is used to disable the sustain control node netBn output during the operation of the n-2 th stage circuit unit in the positive scan, i.e., during the precharge phase of the positive scan.
The control terminal of the fifteenth tft M6B receives the second control signal, and two path terminals of the fifteenth tft M6B are respectively connected to the net bn of the nth stage driving circuit unit and the forward direction scan control signal U2D. The fifteenth tft M6B is used to disable the sustain control node netBn output during the operation of the (n + 2) th stage circuit unit in the reverse scan, i.e., during the precharge phase of the reverse scan.
Compared with the prior art, the second embodiment of the present invention not only maintains the symmetry of the sustain control node generating module 3, but also is suitable for the gate scan driving circuit with the forward and reverse scan functions, and simultaneously avoids the unnecessary operations caused by the symmetric design and the additional operations, i.e. the fourteenth tft M6A and the fifteenth tft M6B do not prohibit the output of the sustain control node netBn after the scan signal Gn is output (during the period when Gn +2 is at the high level during the forward scan, and during the period when Gn-2 is at the high level during the reverse scan), so as not to narrow the first pulse width of the sustain control node netBn after the scan signal Gn is output.
The invention also discloses a liquid crystal display device which comprises the grid scanning driving circuit, wherein the grid scanning driving circuit can be a single-side driving framework, a left-right staggered driving framework or a non-left-right staggered double-side driving framework. Fig. 10 shows an lcd device with integrated gate driving circuits, wherein an area AA indicates a display area, and the lcd device adopts a left-right staggered driving scheme, including a left gate scanning driving circuit, a right gate scanning driving circuit, and other driving circuits.
It should be noted that the above embodiments can be freely combined as necessary. The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (8)
1. A gate scan driving circuit, comprising: comprises an N-stage drive circuit unit; the nth-stage driving circuit unit comprises a pull-up control module, a pull-up module, a maintaining control node generating module, a pull-up control node maintaining module and an output node maintaining module, wherein N is greater than 4, 1 is less than or equal to N, and N and N are positive integers;
the pull-up control module, the pull-up module, the maintenance control node generation module and the pull-up control node maintenance module are connected with the pull-up control node; the maintaining control node generating module, the pull-up control node maintaining module and the output node maintaining module input low level in specific working time; the pull-up module and the output node maintaining module are connected with the scanning signal line of the current stage, and the scanning signal line outputs a scanning signal; the maintaining control node generating module and the pull-up control node maintaining module are connected with the maintaining control node;
a maintaining control node generating module of the nth stage driving circuit unit inputs a forward scanning control signal and a reverse scanning control signal which are mutually reverse, generates a maintaining control signal to control the maintaining control node, and maintains that the pulse width of a first signal of the maintaining control node is the same as the preset width after the scanning signals during forward scanning and reverse scanning are output;
the maintaining control node generating module of the nth-stage driving circuit unit comprises a fifth thin film transistor, a sixth thin film transistor and a seventh thin film transistor;
a control end of the fifth thin film transistor inputs a first clock signal, and two path ends of the fifth thin film transistor are respectively connected with a forward scanning control signal and a maintaining control node of the nth-stage drive circuit unit;
the control end of the sixth thin film transistor is connected with the pull-up control node of the nth-stage drive circuit unit, and two path ends of the sixth thin film transistor are respectively connected with the maintaining control node and the low level of the nth-stage drive circuit unit;
a control end of the seventh thin film transistor inputs a third clock signal, and two path ends of the seventh thin film transistor are respectively connected with a maintaining control node and a reverse scanning control signal of the nth-stage driving circuit unit; the maintenance control node generating module of the nth-stage driving circuit unit further comprises a fourteenth thin film transistor and a fifteenth thin film transistor;
a control end of the fourteenth thin film transistor inputs a first control signal, and two path ends of the fourteenth thin film transistor are respectively connected with a maintaining control node and a reverse scanning control signal of the nth-stage driving circuit unit;
the control end of the fifteenth thin film transistor inputs the second control signal, and two path ends of the fifteenth thin film transistor are respectively connected with the maintaining control node of the nth-stage driving circuit unit and the forward scanning control signal.
2. The gate scan driving circuit according to claim 1, wherein: the pull-up control module of the nth-stage driving circuit unit comprises a first thin film transistor and a ninth thin film transistor;
a control end of the first thin film transistor inputs a first control signal, and two path ends of the first thin film transistor are respectively connected with a forward scanning control signal and a pull-up control node of the nth-stage drive circuit unit;
and the control end of the ninth thin film transistor inputs a second control signal, and two path ends of the ninth thin film transistor are respectively connected with the reverse scanning control signal and the pull-up control node of the nth-stage drive circuit unit.
3. The gate scan driving circuit according to claim 2, wherein:
when the nth-stage driving circuit unit is a first-stage driving circuit unit, the first control signal is a first starting signal; when the nth-stage driving circuit unit is not the first-stage driving circuit unit, the first control signal is a gate scanning signal of the preceding-stage driving circuit unit;
when the nth-stage driving circuit unit is a tail-stage driving circuit unit, the second control signal is a second starting signal; when the nth stage driving circuit unit is not the tail stage driving circuit unit, the second control signal is a gate scanning signal of the rear stage driving circuit unit.
4. The gate scan driving circuit according to claim 1, wherein: the pull-up control node maintaining module of the nth-stage driving circuit unit comprises an eighth thin film transistor;
and the control end of the eighth thin film transistor is connected with the maintaining control node of the nth-stage drive circuit unit, and two path ends of the eighth thin film transistor are respectively connected with the pull-up control node and the low level of the nth-stage drive circuit unit.
5. The gate scan driving circuit according to claim 1, wherein the pull-up module of the nth stage driving circuit unit includes a tenth thin film transistor;
and the control end of the tenth thin film transistor is connected with the maintaining control node of the nth stage driving circuit unit, and two channel ends of the tenth thin film transistor are respectively connected with the second clock signal and the scanning signal line of the nth stage driving circuit unit.
6. The gate scan driving circuit according to claim 1, wherein: the output node maintaining module of the nth stage driving circuit unit comprises an eleventh thin film transistor;
a control end of the eleventh thin film transistor is used for inputting a fourth clock signal, and two path ends of the eleventh thin film transistor are respectively connected with a scanning signal line and a low level of the nth-stage driving circuit unit.
7. The gate scan driving circuit according to claim 1, wherein: the nth-stage drive circuit unit also comprises an emptying module; the emptying module comprises a second thin film transistor, a third thin film transistor and a twelfth thin film transistor;
the control end of the second thin film transistor inputs an emptying signal, and two path ends of the second thin film transistor are respectively connected with a pull-up control node and a low level of the nth-stage drive circuit unit;
the control end of the third thin film transistor inputs an emptying signal, and two path ends of the third thin film transistor are respectively connected with a maintaining control node and a low level of the nth-stage driving circuit unit;
and the control end of the twelfth thin film transistor inputs an emptying signal, and two path ends of the twelfth thin film transistor are respectively connected with a scanning signal line and a low level of the nth-stage driving circuit unit.
8. The gate scan driving circuit of claim 1, wherein the nth stage driving circuit unit further comprises an auxiliary sustain module including a fourth thin film transistor and a thirteenth thin film transistor;
a control end of the fourth thin film transistor inputs a first starting signal, and two path ends of the fourth thin film transistor are respectively connected with a pull-up control node and a low level; the control end of a fourth thin film transistor in the 1 st, 2 nd and 3 rd stage driving circuit unit inputs low level;
a control end of the thirteenth thin film transistor inputs a second starting signal, and two path ends of the thirteenth thin film transistor are respectively connected with the upper pull control node and the low level; wherein, the control end of the thirteenth thin film transistor in the N-2, N-1 and N-stage driving circuit unit inputs low level.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810082089.9A CN108242228B (en) | 2018-01-29 | 2018-01-29 | Grid scanning driving circuit |
| PCT/CN2018/122442 WO2019144737A1 (en) | 2018-01-29 | 2018-12-20 | Gate drive unit circuit, gate drive circuit and display apparatus |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810082089.9A CN108242228B (en) | 2018-01-29 | 2018-01-29 | Grid scanning driving circuit |
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| CN108242228B true CN108242228B (en) | 2020-08-04 |
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| CN108242228B (en) * | 2018-01-29 | 2020-08-04 | 南京中电熊猫平板显示科技有限公司 | Grid scanning driving circuit |
| CN109192156B (en) * | 2018-09-25 | 2020-07-07 | 南京中电熊猫平板显示科技有限公司 | Grid driving circuit and display device |
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| CN106601169A (en) * | 2016-12-29 | 2017-04-26 | 南京华东电子信息科技股份有限公司 | Bidirectional scanning gate drive circuit |
| CN106652933A (en) * | 2016-11-18 | 2017-05-10 | 南京华东电子信息科技股份有限公司 | Grid drive circuit having forward and reverse scanning functions |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR102072214B1 (en) * | 2013-07-09 | 2020-02-03 | 삼성디스플레이 주식회사 | Scan driver and display device comprising the same |
| CN108242228B (en) * | 2018-01-29 | 2020-08-04 | 南京中电熊猫平板显示科技有限公司 | Grid scanning driving circuit |
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2018
- 2018-01-29 CN CN201810082089.9A patent/CN108242228B/en active Active
- 2018-12-20 WO PCT/CN2018/122442 patent/WO2019144737A1/en active Application Filing
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| CN106251821A (en) * | 2016-09-23 | 2016-12-21 | 南京华东电子信息科技股份有限公司 | Gate driver circuit |
| CN106448588A (en) * | 2016-10-09 | 2017-02-22 | 深圳市华星光电技术有限公司 | GOA drive circuit and liquid crystal display device |
| CN106652933A (en) * | 2016-11-18 | 2017-05-10 | 南京华东电子信息科技股份有限公司 | Grid drive circuit having forward and reverse scanning functions |
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| WO2019144737A1 (en) | 2019-08-01 |
| CN108242228A (en) | 2018-07-03 |
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Effective date of registration: 20200828 Address after: No.7 Tianyou Road, Qixia District, Nanjing City, Jiangsu Province Patentee after: NANJING CEC PANDA LCD TECHNOLOGY Co.,Ltd. Address before: Nanjing Crystal Valley Road in Qixia District of Nanjing City Tianyou 210033 Jiangsu province No. 7 Co-patentee before: NANJING CEC PANDA LCD TECHNOLOGY Co.,Ltd. Patentee before: NANJING CEC PANDA FPD TECHNOLOGY Co.,Ltd. Co-patentee before: Nanjing East China Electronic Information Technology Co.,Ltd. |