CN106649157B - SDRAM control system based on FPGA - Google Patents
SDRAM control system based on FPGA Download PDFInfo
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- CN106649157B CN106649157B CN201611168517.7A CN201611168517A CN106649157B CN 106649157 B CN106649157 B CN 106649157B CN 201611168517 A CN201611168517 A CN 201611168517A CN 106649157 B CN106649157 B CN 106649157B
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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Abstract
The present invention relates to the SDRAM control systems based on FPGA, including RAM Read-write Catrol module, interface modular converter and sdram controller IP module；The interface modular converter includes a RAM Read-write Catrol interface, a selection submodule and at least two transform subblocks, and the sdram controller IP module includes at least two controller IP submodules；At least two controllers IP submodule is different, at least two transform subblock is respectively used to realize the conversion of RAM Interface specification and different types of sdram controller IP interface specification, and at least two transform subblock and at least two controllers IP submodule correspond.Present invention realization can conveniently and efficiently use SDRAM memory in the FPGA of different vendor, extend the versatility that FPGA controls SDRAM.
Description
Technical Field
The invention relates to the technical Field of Field Programmable Gate Arrays (FPGA), in particular to an SDRAM control system based on an FPGA.
Background
Synchronous Dynamic Random Access Memory (SDRAM), which locks a CPU and a RAM together through a same clock, so that the RAM and the CPU can share a clock cycle and synchronously work at the same speed, and the speed can be improved by 50% compared with that of an EDO Memory. The SDRAM is based on a double-memory-bank structure and comprises two staggered memory arrays, when a CPU accesses data from one memory bank or array, the other memory bank or array is ready for reading and writing the data, and the reading efficiency can be improved in multiples by tightly switching the two memory arrays. In the fields of image acquisition, data analysis and the like, a large amount of data is cached and processed by using a mode of FPGA and SDRAM.
Generally, there are two methods for implementing SDRAM control within an FPGA: one is designed by utilizing FPGA resources, and the other is calling an SDRAM controller IP (Intellectual Property) interface provided by an FPGA manufacturer. Although the SDRAM interface has a uniform standard, the SDRAM controller IP interface of each FPGA vendor is different. And the data read-write control mode in the FPGA must be matched with the standard of an IP interface of the SDRAM controller to finish correct data read-write. Therefore, for the users of the FPGA and the SDRAM, it is very inconvenient to use the FPGA of different manufacturers to design the SDRAM control, and each time the FPGA is replaced, a data read-write control program needs to be redesigned, so the product portability is poor, and a lot of time is wasted.
Disclosure of Invention
Based on this, the embodiment of the invention provides the SDRAM control system based on the FPGA, which can expand the universality of the SDRAM control by the FPGA.
The invention provides an SDRAM control system based on FPGA on the one hand, comprising an RAM read-write control module, an interface conversion module and an SDRAM controller IP module;
the interface conversion module comprises an RAM read-write control interface, a selection submodule and at least two conversion submodules, and the SDRAM controller IP module comprises at least two controller IP submodules; the at least two controller IP sub-modules are different from each other, the at least two conversion sub-modules are respectively used for realizing the conversion between the RAM interface specification and the SDRAM controller IP interface specifications of different types, and the at least two conversion sub-modules correspond to the at least two controller IP sub-modules one by one;
the RAM read-write control module sends a control instruction to the interface conversion module according to the RAM interface specification;
the interface conversion module receives the control instruction through the RAM read-write control interface and distributes a corresponding conversion sub-module for the received control instruction through the selection sub-module; converting the control instruction specified by the RAM interface into a corresponding control instruction specified by the IP interface of the SDRAM controller through the conversion submodule, and sending the control instruction specified by the IP interface of the SDRAM controller to the IP module of the SDRAM controller;
and the corresponding controller IP sub-module in the SDRAM controller IP module carries out read-write operation on the SDRAM according to the control instruction specified by the SDRAM controller IP interface.
Based on the SDRAM control system based on FPGA provided in the above embodiment, the IP interfaces of different SDRAM controllers of different FPGA manufacturers are converted into a general RAM (Random access memory) interface through an interface conversion module, so that the SDRAM memories can be conveniently and quickly used in the FPGAs of different manufacturers, and the versatility of the FPGA is expanded.
Drawings
FIG. 1 is a schematic diagram of an FPGA-based SDRAM control system of an embodiment;
FIG. 2 is a timing diagram of RAM write control;
FIG. 3 is a timing diagram of RAM read control;
FIG. 4 is a diagram illustrating an interface conversion module according to an embodiment;
FIG. 5 is a schematic flow chart of an SDRAM write data performed by an FPGA-based SDRAM control system according to an embodiment;
FIG. 6 is a schematic flow chart of an SDRAM read data by an FPGA-based SDRAM control system according to an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
FIG. 1 is a schematic diagram of an FPGA-based SDRAM control system of an embodiment; as shown in fig. 1, the SDRAM control system based on FPGA in this embodiment includes: the device comprises an RAM read-write control module, an interface conversion module and an SDRAM controller IP module. The interface conversion module comprises an RAM read-write control interface, a selection submodule and at least two conversion submodules, and the SDRAM controller IP module comprises at least two controller IP submodules; the at least two controller IP sub-modules are different from each other, the at least two conversion sub-modules are respectively used for realizing the conversion between the RAM interface specification and the SDRAM controller IP interface specifications of different types, and the at least two conversion sub-modules correspond to the at least two controller IP sub-modules one to one.
The principle of the SDRAM control system based on FPGA of this embodiment is: the RAM read-write control module sends a control instruction to the interface conversion module according to the RAM interface specification; the interface conversion module receives the control instruction through the RAM read-write control interface and distributes a corresponding conversion sub-module for the received control instruction through the selection sub-module; converting the control instruction specified by the RAM interface into a corresponding control instruction specified by the IP interface of the SDRAM controller through the conversion submodule, and sending the control instruction specified by the IP interface of the SDRAM controller to the IP module of the SDRAM controller; and the corresponding controller IP sub-module in the SDRAM controller IP module carries out read-write operation on the SDRAM according to the control instruction specified by the SDRAM controller IP interface.
In a preferred embodiment, the operation of the SDRAM control system based on the FPGA on the SDRAM includes a write operation and a read operation, correspondingly, the control instruction sent by the RAM read-write control module may be a write operation instruction or a read operation instruction, and information in the read operation instruction includes: address information Addr and a read instruction RD, the write operation instruction including: address information Addr, write instruction WE, and write data WrData.
It is understood that the control command issued by the RAM read-write control module may also include other relevant information, such as a read data valid RdValid signal.
In a preferred embodiment, each conversion sub-module in the interface conversion module may specifically include: RAM address and command conversion unit and SDRAM controller IP address and command interface.
Each conversion sub-module converts the address information and the read/write command specified by the RAM interface into the address and the read/write command specified by the IP of the corresponding SDRAM controller through the RAM address and command conversion unit; sending address information and read/write commands of the SDRAM controller IP specification to an SDRAM controller IP module through an SDRAM controller IP address and command interface;
each conversion submodule further comprises: the data writing system comprises a RAM writing data conversion unit and an SDRAM controller IP writing data interface;
each conversion sub-module converts the write data specified by the RAM interface into the write data specified by the corresponding SDRAM controller IP through the RAM write data conversion unit; sending the writing data specified by the IP of the SDRAM controller to the IP module of the SDRAM controller through an IP writing data interface of the SDRAM controller;
and for the read operation, the SDRAM controller IP module receives the address information and the read command of the SDRAM controller IP specification through the corresponding controller IP sub-module, and reads the SDRAM according to the received address information and the read command. Or, for the write operation, the SDRAM controller IP module receives the address information, the write command and the write data of the SDRAM controller IP specification through the corresponding controller IP sub-module, and performs the write operation on the SDRAM according to the received address information, the write command and the write data.
In another preferred embodiment, each conversion sub-module further comprises: address and command caching and write data caching. Correspondingly, each conversion sub-module caches the address information and the read/write command of the SDRAM controller IP specification obtained by the RAM address and command conversion unit through the address and command cache, and reads the address and the read/write command of the SDRAM controller IP specification from the address and command cache through the SDRAM controller IP address and command interface. Each conversion submodule caches the writing data of the SDRAM controller IP specification obtained by the RAM writing data conversion unit through the writing data cache; and reading the write data of the SDRAM controller IP specification from the write data cache through the SDRAM controller IP write data interface. And the SDRAM controller IP data writing interface reads data from a corresponding cache synchronously with the SDRAM controller IP address and the command interface, and sends the address, the writing command and the writing data of the SDRAM controller IP specification to an SDRAM controller IP module.
In another preferred embodiment, the address and command buffer and the write data buffer are both FIFO (First In First out) buffers.
In another preferred embodiment, each conversion sub-module further comprises: the device comprises a RAM read data conversion unit and an IP read data interface of an SDRAM controller. Correspondingly, the SDRAM controller IP module sends the read data read from the SDRAM to the interface conversion module. Correspondingly, the corresponding conversion sub-module in the interface conversion module receives the read data through the SDRAM controller IP read data interface, converts the received read data specified by the SDRAM controller IP into read data specified by the RAM read data conversion unit, and sends the read data specified by the RAM interface to the RAM read-write control module through the RAM read-write control interface. Correspondingly, the RAM read-write control module receives and outputs the read data specified by the RAM interface.
In a preferred embodiment, the SDRAM controller IP block includes three controller IP sub-blocks, which are: the device comprises a Xilinx SDRAM controller IP sub-module, an Altera SDRAM controller IP sub-module and a Lattice SDRAM controller IP sub-module. The interface conversion module comprises three conversion sub-modules which are respectively: the first conversion submodule is used for realizing conversion between the RAM interface specification and the Xilinx SDRAM controller IP interface specification; the second conversion submodule is used for realizing the conversion between the RAM interface specification and the AlterasDRAM controller IP interface specification; and the third conversion submodule is used for realizing the conversion between the RAM interface specification and the Lattice SDRAM controller IP interface specification.
It can be understood that other conversion sub-modules and controller IP sub-modules can be further provided according to actual needs.
With reference to fig. 2 to 5 in conjunction with the above embodiments, the SDRAM writing operation flow and SDRAM reading operation flow are combined below to further describe the SDRAM control system based on FPGA of the present invention.
The RAM read-write control module is responsible for sending read-write commands and data according to the general RAM interface specification. The information sent by the RAM read-write control module comprises signals such as an address Addr, a read command RD, a write command WE, write data WrData, read data RdData and read data valid RdValid. The read and write timing of the RAM is also very simple, and is divided into a write control timing and a read control timing. Fig. 2 and 3 are a RAM write timing diagram and a RAM read timing diagram, respectively. When data is to be written, WE is pulled high, and the address Addr and the write data WrData are sent at the same time, so that the write data are written into the corresponding address. When reading data, the RD is pulled high, the address Addr is sent at the same time, and then the read data RdData can be obtained after delaying the TCL time.
Further, the interface conversion module is used for realizing the conversion from the RAM read-write control interface to the corresponding SDRAM controller IP controller interface. The conversion of the timing of the two types of interfaces can be done internally by FIFO buffering. As shown in FIG. 4, the interface conversion module can be further divided into three parts, namely address and command conversion, write data conversion and read data conversion.
Referring to fig. 5, when writing data, the RAM address and command interface conversion unit converts the RAM address and write command into an SDRAM controller IP address and command format, and then stores into an address and command FIFO. The RAM write data interface conversion unit converts the RAM write data format into the SDRAM controller IP write data format and then stores the data into the write data FIFO. And then reading the address, the command and the write data from the two FIFOs together, sending the read data to an IP interface module of the SDRAM controller, and writing the write data into the SDRAM by the IP interface module of the SDRAM controller. This completes the operation of writing data.
Referring to fig. 6, when reading data, the RAM address and command interface conversion unit converts the RAM address and read command format into the SDRAM controller IP address command format and then stores it in the address and command FIFO. Then, the address command is read out from the FIFO and sent to the IP interface module of the SDRAM controller, and then the read operation is carried out on the SDRAM by the IP module of the SDRAM controller. And after receiving the read command, the SDRAM outputs the data to an IP interface module of the SDRAM controller, and finally, the RAM read data interface conversion submodule directly acquires the read data from the IP interface of the SDRAM controller, converts the read data into an RAM read data format and sends the RAM read data format to the RAM read-write control interface. This completes the read data operation.
Through the SDRAM control system based on the FPGA of the embodiment, the IP interfaces of different types of SDRAM controllers of different FPGA manufacturers can be converted into a universal RAM interface by designing an interface conversion module, so that the SDRAM memory can be conveniently and quickly used in the FPGAs of different manufacturers, and the problem that the SDRAM memory is poor in universality when the SDRAM memory is controlled due to the fact that the IP interfaces of the SDRAM controllers of different FPGA manufacturers are different is solved.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The above-described examples merely represent several embodiments of the present invention and should not be construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (8)
1. An SDRAM control system based on FPGA, comprising: the device comprises an RAM read-write control module, an interface conversion module and an SDRAM controller IP module;
the interface conversion module comprises an RAM read-write control interface, a selection submodule and at least two conversion submodules, and the SDRAM controller IP module comprises at least two controller IP submodules; the at least two controller IP sub-modules are different from each other, the at least two conversion sub-modules are respectively used for realizing the conversion between the RAM interface specification and the SDRAM controller IP interface specifications of different types, and the at least two conversion sub-modules correspond to the at least two controller IP sub-modules one by one;
the RAM read-write control module sends a control instruction to the interface conversion module according to the RAM interface specification;
the interface conversion module receives the control instruction through the RAM read-write control interface and distributes a corresponding conversion sub-module for the received control instruction through the selection sub-module; converting the control instruction specified by the RAM interface into a corresponding control instruction specified by the IP interface of the SDRAM controller through the conversion submodule, and sending the control instruction specified by the IP interface of the SDRAM controller to the IP module of the SDRAM controller;
and the corresponding controller IP sub-module in the SDRAM controller IP module carries out read-write operation on the SDRAM according to the control instruction specified by the SDRAM controller IP interface.
2. The FPGA-based SDRAM control system of claim 1, wherein the information in the control instructions comprises: address information and a read instruction, and/or comprising: address information, write instructions, and write data.
3. The FPGA-based SDRAM control system of claim 2,
each conversion submodule includes: RAM address and order conversion unit and SDRAM controller IP address and order interface;
each conversion sub-module converts the address information and the read/write command specified by the RAM interface into the address and the read/write command specified by the IP of the corresponding SDRAM controller through the RAM address and command conversion unit; sending address information and read/write commands of the SDRAM controller IP specification to an SDRAM controller IP module through an SDRAM controller IP address and command interface;
each conversion submodule further comprises: the data writing system comprises a RAM writing data conversion unit and an SDRAM controller IP writing data interface;
each conversion sub-module converts the write data specified by the RAM interface into the write data specified by the corresponding SDRAM controller IP through the RAM write data conversion unit; sending the writing data specified by the IP of the SDRAM controller to the IP module of the SDRAM controller through an IP writing data interface of the SDRAM controller;
the SDRAM controller IP module receives address information and a read command of the SDRAM controller IP specification through a corresponding controller IP sub-module, and reads the SDRAM according to the received address information and the read command; or,
and the SDRAM controller IP module receives the address information, the write command and the write data of the SDRAM controller IP specification through the corresponding controller IP sub-module, and performs write operation on the SDRAM according to the received address information, the write command and the write data.
4. The FPGA-based SDRAM control system of claim 3, wherein each conversion submodule further comprises: address and command caching and write data caching;
each conversion submodule caches address information and read/write commands of the SDRAM controller IP specification obtained by the RAM address and command conversion unit through the address and command cache, and reads the address and read/write commands of the SDRAM controller IP specification from the address and command cache through the SDRAM controller IP address and command interface;
each conversion submodule caches the writing data of the SDRAM controller IP specification obtained by the RAM writing data conversion unit through the writing data cache; reading the write data of the SDRAM controller IP specification from the write data cache through the SDRAM controller IP write data interface;
and the SDRAM controller IP data writing interface reads data from a corresponding cache synchronously with the SDRAM controller IP address and the command interface, and sends the address, the writing command and the writing data of the SDRAM controller IP specification to an SDRAM controller IP module.
5. The FPGA-based SDRAM control system of claim 4,
the address and command cache and the write data cache are both FIFO caches.
6. The FPGA-based SDRAM control system of claim 3, wherein each conversion submodule further comprises: the device comprises a RAM read data conversion unit and an SDRAM controller IP read data interface;
the SDRAM controller IP module sends read data read from the SDRAM to the interface conversion module;
the corresponding conversion sub-module in the interface conversion module receives the read data through the SDRAM controller IP read data interface, converts the received read data specified by the SDRAM controller IP into read data specified by the RAM interface through the RAM read data conversion unit, and sends the read data specified by the RAM interface to the RAM read-write control module through the RAM read-write control interface;
and the RAM read-write control module receives and outputs the read data specified by the RAM interface.
7. The FPGA-based SDRAM control system of claim 1, wherein the interface conversion module comprises three conversion sub-modules and the SDRAM controller IP module comprises three controller IP sub-modules.
8. The FPGA-based SDRAM control system of claim 7, wherein the three controller IP sub-modules are respectively: the Xilinx SDRAM controller IP submodule, the Altera SDRAM controller IP submodule and the Lattice SDRAM controller IP submodule;
the three conversion submodules are respectively:
the first conversion submodule is used for realizing conversion between the RAM interface specification and the Xilinx SDRAM controller IP interface specification;
the second conversion submodule is used for realizing the conversion between the RAM interface specification and the IP interface specification of the Altera SDRAM controller;
and the third conversion submodule is used for realizing the conversion between the RAM interface specification and the IP interface specification of the Lattice SDRAM controller.
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| US6076152A (en) * | 1997-12-17 | 2000-06-13 | Src Computers, Inc. | Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem |
| CN101213533A (en) * | 2005-05-04 | 2008-07-02 | Nxp股份有限公司 | Memory controller and method for controlling access to a memory, as well as system comprising a memory controller |
| CN102339261B (en) * | 2011-09-16 | 2015-09-30 | 上海智翔信息科技股份有限公司 | A kind of DDR2SDRAM controller |
| CN105279116B (en) * | 2015-10-08 | 2017-12-01 | 中国电子科技集团公司第四十一研究所 | DDR controller and control method based on FPGA |
| CN105677594B (en) * | 2016-01-20 | 2018-08-10 | 中国人民解放军国防科学技术大学 | Reset, read-write calibration method and the equipment of FPGA device in DDR3 interfaces |
| CN105868134B (en) * | 2016-04-14 | 2018-12-28 | 烽火通信科技股份有限公司 | More mouthfuls of DDR controllers of high-performance and its implementation |
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