CN106649157B - SDRAM control system based on FPGA - Google Patents
SDRAM control system based on FPGA Download PDFInfo
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- CN106649157B CN106649157B CN201611168517.7A CN201611168517A CN106649157B CN 106649157 B CN106649157 B CN 106649157B CN 201611168517 A CN201611168517 A CN 201611168517A CN 106649157 B CN106649157 B CN 106649157B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
Abstract
The present invention relates to the SDRAM control systems based on FPGA, including RAM Read-write Catrol module, interface modular converter and sdram controller IP module；The interface modular converter includes a RAM Read-write Catrol interface, a selection submodule and at least two transform subblocks, and the sdram controller IP module includes at least two controller IP submodules；At least two controllers IP submodule is different, at least two transform subblock is respectively used to realize the conversion of RAM Interface specification and different types of sdram controller IP interface specification, and at least two transform subblock and at least two controllers IP submodule correspond.Present invention realization can conveniently and efficiently use SDRAM memory in the FPGA of different vendor, extend the versatility that FPGA controls SDRAM.
Description
Technical field
The present invention relates to FPGA (Field Programmable Gate Array, field programmable gate array) technology necks
Domain, more particularly to a kind of SDRAM control system based on FPGA.
Background technique
SDRAM:Synchronous Dynamic Random Access Memory, i.e. synchronous DRAM,
It locks together CPU and RAM by an identical clock, so that RAM and CPU is shared a clock cycle, with identical
Speed sync work, speed can improve 50% compared with EDO memory.SDRAM is based on double bank structures, includes two staggeredly
Storage array, as soon as when CPU is from memory bank or array accesses data, another be read-write data get ready,
By the close switching of the two storage arrays, reading efficiency can be increased exponentially.Analyzed in Image Acquisition, data etc.
Caching and the processing that field often uses FPGA that the mode of SDRAM is added to carry out mass data.
In general, there are two types of methods for control of the realization to SDRAM in FPGA: one is set using FPGA resource oneself
Meter, another kind are that the sdram controller IP (Intellectual Property, intellectual property) for calling FPGA manufacturer to provide connects
Mouthful.Although sdram interface has unified standard, the sdram controller IP interface of each FPGA manufacturer is different.And
Data read-write control mode must could complete correct data reading with the matches criteria of sdram controller IP interface in FPGA
It writes.Therefore, for the user of FPGA and SDRAM, using the FPGA of different vendor do SDRAM control design case be one extremely
Inconvenient thing changes a FPGA often it is necessary to redesign a data read-write control program, and the portability of product is poor,
Cause to waste a large amount of time.
Summary of the invention
Based on this, the embodiment of the invention provides the SDRAM control systems based on FPGA, can expand FPGA to SDRAM
Versatility when being controlled.
One aspect of the present invention provides the SDRAM control system based on FPGA, including RAM Read-write Catrol module, interface conversion
Module and sdram controller IP module；
The interface modular converter includes a RAM Read-write Catrol interface, a selection submodule and at least two conversion submodules
Block, the sdram controller IP module include at least two controller IP submodules；At least two controllers IP submodule
Different, at least two transform subblock is respectively used to realize RAM Interface specification and different types of sdram controller
The conversion of IP interface specification, at least two transform subblock and at least two controllers IP submodule correspond；
The RAM Read-write Catrol module issues control instruction to the interface modular converter according to RAM Interface specification；
The interface modular converter by control instruction described in RAM Read-write Catrol interface, by select submodule for
The control instruction received distributes a corresponding transform subblock；The control of RAM Interface specification is referred to by the transform subblock
The control instruction for being converted to corresponding sdram controller IP interface specification is enabled, by the control of the sdram controller IP interface specification
System instruction is sent to sdram controller IP module；
Corresponding controller IP submodule is according to the sdram controller IP interface in the sdram controller IP module
The control instruction of specification is written and read SDRAM.
The SDRAM control system based on FPGA provided based on the above embodiment is realized by an interface modular converter
By the different sdram controller IP interface conversions of different FPGA manufacturers at a kind of general RAM (Random Access
Memory, random access memory) interface, so that realizing can conveniently and efficiently use in the FPGA of different vendor
SDRAM memory extends the versatility of FPGA.
Detailed description of the invention
Fig. 1 is the schematic diagram of the SDRAM control system based on FPGA of an embodiment；
Fig. 2 is RAM write control sequential figure；
Fig. 3 is that RAM reads control sequential figure；
Fig. 4 is the schematic diagram of the interface modular converter of an embodiment；
Fig. 5 is that the SDRAM control system based on FPGA of an embodiment carries out the schematic flow diagram that SDRAM writes data；
Fig. 6 is that the SDRAM control system based on FPGA of an embodiment carries out the schematic flow diagram that SDRAM reads data.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
Fig. 1 is the schematic diagram of the SDRAM control system based on FPGA of an embodiment；As shown in Figure 1, in the present embodiment
SDRAM control system based on FPGA includes: RAM Read-write Catrol module, interface modular converter and sdram controller IP mould
Block.Wherein, the interface modular converter includes a RAM Read-write Catrol interface, a selection submodule and at least two conversion submodules
Block, the sdram controller IP module include at least two controller IP submodules；At least two controllers IP submodule
Different, at least two transform subblock is respectively used to realize RAM Interface specification and different types of sdram controller
The conversion of IP interface specification, at least two transform subblock and at least two controllers IP submodule correspond.
The principle of the SDRAM control system based on FPGA of the present embodiment are as follows: the RAM Read-write Catrol module is according to RAM
Interface specification issues control instruction to the interface modular converter；The interface modular converter is connect by RAM Read-write Catrol interface
The control instruction is received, the control instruction received by selecting submodule distributes a corresponding transform subblock；By this
The control instruction of RAM Interface specification is converted to the control instruction of corresponding sdram controller IP interface specification by transform subblock,
The control instruction of the sdram controller IP interface specification is sent to sdram controller IP module；The sdram controller
In IP module corresponding controller IP submodule according to the control instruction of the sdram controller IP interface specification to SDRAM into
Row read-write operation.
In a preferred embodiment, the SDRAM control system based on FPGA includes write operation to the operation of SDRAM and reads to grasp
Make, corresponding, the control instruction that the RAM Read-write Catrol module issues can refer to for write operation instruction or read operation
It enables, it includes: address information in write operation instruction that the information in read operation instruction, which includes: address information Addr and reading instruction RD,
Addr, write command WE and write data WrData.
It should be understood that it is relevant to may also include other in the control instruction that the RAM Read-write Catrol module issues
Information, such as read the effective RdValid signal of data.
In a preferred embodiment, specific in each transform subblock in interface modular converter can include: address ram and
Order converting unit and sdram controller IP address and command interface.
Each transform subblock passes through address ram and order converting unit for the address information and read/write of RAM Interface specification
Order is converted into address and the read/write command of corresponding sdram controller IP specification；And by sdram controller IP address and
The sdram controller IP address information standardized and read/write command are sent to sdram controller IP module by command interface；
Each transform subblock further include: RAM write Date Conversion Unit and sdram controller IP write data-interface；
Each transform subblock by RAM write Date Conversion Unit by RAM Interface specification write data be converted to it is corresponding
Sdram controller IP specification writes data；And data-interface is write by sdram controller IP and advises the sdram controller IP
The data of writing of model are sent to the sdram controller IP module；
For read operation, the sdram controller IP module receives the SDRAM by corresponding controller IP submodule
The address information and read command of controller IP specification carry out read operation to SDRAM according to the address information and read command received.
Alternatively, the sdram controller IP module receives the SDRAM control by corresponding controller IP submodule for write operation
The address information of device IP processed specification, write order and data are write, according to the address information received, write order and writes data pair
SDRAM carries out write operation.
In another preferred embodiment, each transform subblock further include: address and order caching and write data buffer storage.It is right
It answers, each transform subblock obtains the address ram and order converting unit by the address and order caching
The address information and read/write command of sdram controller IP specification are cached, and the sdram controller IP address and life are passed through
Interface is enabled to read address and the read/write command of the sdram controller IP specification from the address and order caching.Each turn
It changes submodule and is write by write data caching to what the sdram controller IP that the RAM write Date Conversion Unit obtains was standardized
Data are cached；By the sdram controller IP write data-interface from write data caching in read sdram controller
IP specification writes data.Wherein, the sdram controller IP writes data-interface and the sdram controller IP address and order
Interface synchronization reads data from corresponding caching, by the address of sdram controller IP specification, write order and writes data together
It is sent to sdram controller IP module.
In another preferred embodiment, the address and order caching, write data caching are FIFO (First In
First Out) caching.
In another preferred embodiment, each transform subblock further include: RAM reads Date Conversion Unit and SDRAM control
Device IP reads data-interface.Corresponding, the reading data read from SDRAM are sent to described by the sdram controller IP module
Interface modular converter.Corresponding, corresponding transform subblock reads data by the sdram controller IP in interface modular converter
Data are read described in interface, and the reading that Date Conversion Unit standardizes the sdram controller IP received is read by the RAM
It is sent out according to the reading data for being converted to RAM Interface specification, and by the reading data of the RAM Interface specification by RAM Read-write Catrol interface
It send to RAM Read-write Catrol module.Corresponding, RAM Read-write Catrol module receives the reading data of RAM Interface specification and exports.
In a preferred embodiment, the sdram controller IP module includes three controller IP submodules, is respectively as follows:
Xilinx sdram controller IP submodule, Altera sdram controller IP submodule and Lattice sdram controller
IP submodule.The interface modular converter include three transform subblocks, be respectively as follows: for realizing RAM Interface specification with
First transform subblock of Xilinx sdram controller IP interface specification conversion；For realizing RAM Interface specification and Altera
Second transform subblock of sdram controller IP interface specification conversion；And for realizing RAM Interface specification and Lattice
The third transform subblock of sdram controller IP interface specification conversion.
It should be understood that according to actual needs, other also settable transform subblocks and controller IP submodule.
In conjunction with above-described embodiment, with reference to Fig. 2~Fig. 5, below with reference to SDRAM write operation process and SDRAM read operation process,
SDRAM control system of the invention based on FPGA is described further.
RAM Read-write Catrol module is responsible for sending read write command and data according to general RAM Interface specification.RAM read-write control
Molding block issue information include address Addr, read command RD, write order WE, write data WrData, read data RdData and
Read the signals such as the effective RdValid of data.The read-write sequence of RAM is also very simple, is divided into and writes control sequential and reading control sequential.Figure
2 and Fig. 3 is that RAM write timing diagram and RAM read timing diagram respectively.When writing data, WE is drawn high, while sending address Addr and writing number
According to WrData, appropriate address just is written with data are write.When reading data, RD is drawn high, while sending address Addr, be then delayed
It can be obtained by after the TCL time and read data RdData.
Further, interface modular converter is used to realize and control from RAM Read-write Catrol interface to corresponding sdram controller IP
The conversion of device interface processed.The conversion of two style interface timing can be completed by FIFO caching in inside.As shown in figure 4, connecing
It can be further separated into address and order conversion in mouth conversion module, write data conversion, read data conversion three parts to handle.
Refering to what is shown in Fig. 5, address ram and command interface converting unit convert address ram and write order when writing data
At sdram controller IP address and command format, it is then stored in address and order FIFO.RAM write data-interface converting unit handle
RAM write Data Format Transform writes data format at sdram controller IP, and then data FIFO is write in deposit.Later again together from two
In a FIFO by address, order and write data reading, sdram controller IP interface module is sent to, then by sdram controller IP
Interface module will be write in data write-in SDRAM.The operation for writing data is completed in this way.
Refering to what is shown in Fig. 6, when data are read, address ram and command interface converting unit are address ram and read command format
It is converted into sdram controller IP address command format, is then stored in address and order FIFO.Address is ordered from the FIFO later
It enables and reading, be sent in sdram controller IP interface module, read operation then is carried out to SDRAM by sdram controller IP module.
After SDRAM receives read command, data are exported and give sdram controller IP interface module, data interface conversion is finally read by RAM
Submodule obtains directly from sdram controller IP interface reads data, is then converted into RAM reading data format and is sent to RAM read-write
Control interface.The operation for reading data is completed in this way.
The SDRAM control system based on FPGA through the foregoing embodiment can be incited somebody to action by designing an interface modular converter
The different type sdram controller IP interface conversion of different FPGA manufacturers is at a general RAM Interface, to realize in different factories
SDRAM memory can be conveniently and efficiently used in the FPGA of quotient, overcome different FPGA manufacturer sdram controller IP interfaces
Difference, when controlling SDRAM memory the problem of poor universality.
In the above-described embodiments, it all emphasizes particularly on different fields to the description of each embodiment, there is no the portion being described in detail in some embodiment
Point, it may refer to the associated description of other embodiments.
The embodiments described above only express several embodiments of the present invention, should not be understood as to the invention patent range
Limitation.It should be pointed out that for those of ordinary skill in the art, without departing from the inventive concept of the premise,
Various modifications and improvements can be made, and these are all within the scope of protection of the present invention.Therefore, the scope of protection of the patent of the present invention
It should be determined by the appended claims.
Claims (8)
1. a kind of SDRAM control system based on FPGA characterized by comprising RAM Read-write Catrol module, interface conversion mould
Block and sdram controller IP module；
The interface modular converter includes a RAM Read-write Catrol interface, a selection submodule and at least two transform subblocks, institute
Stating sdram controller IP module includes at least two controller IP submodules；At least two controllers IP submodule is mutually not
Identical, at least two transform subblock is respectively used to realize that RAM Interface specification connects with different types of sdram controller IP
The conversion of mouth specification, at least two transform subblock and at least two controllers IP submodule correspond；
The RAM Read-write Catrol module issues control instruction to the interface modular converter according to RAM Interface specification；
The interface modular converter is received by control instruction described in RAM Read-write Catrol interface by selecting submodule
The control instruction arrived distributes a corresponding transform subblock；The control instruction of RAM Interface specification is turned by the transform subblock
It is changed to the control instruction of corresponding sdram controller IP interface specification, the control of the sdram controller IP interface specification is referred to
Order is sent to sdram controller IP module；
Corresponding controller IP submodule is according to the sdram controller IP interface specification in the sdram controller IP module
Control instruction SDRAM is written and read.
2. the SDRAM control system according to claim 1 based on FPGA, which is characterized in that in the control instruction
Information includes: address information and reading instruction, and/or includes: address information, write command and write data.
3. the SDRAM control system according to claim 2 based on FPGA, which is characterized in that
Each transform subblock includes: address ram and order converting unit and sdram controller IP address and command interface；
Each transform subblock passes through address ram and order converting unit for the address information and read/write command of RAM Interface specification
It is converted into address and the read/write command of corresponding sdram controller IP specification；And pass through sdram controller IP address and order
The sdram controller IP address information standardized and read/write command are sent to sdram controller IP module by interface；
Each transform subblock further include: RAM write Date Conversion Unit and sdram controller IP write data-interface；
The data of writing of RAM Interface specification are converted to corresponding SDRAM by RAM write Date Conversion Unit by each transform subblock
Controller IP specification writes data；And data-interface is write by sdram controller IP and is write what the sdram controller IP was standardized
Data are sent to the sdram controller IP module；
The sdram controller IP module receives the sdram controller IP specification by corresponding controller IP submodule
Address information and read command carry out read operation to SDRAM according to the address information and read command received；Alternatively,
The sdram controller IP module receives the sdram controller IP specification by corresponding controller IP submodule
Address information, write order and data are write, according to the address information received, write order and writes data write operation is carried out to SDRAM.
4. the SDRAM control system according to claim 3 based on FPGA, which is characterized in that each transform subblock is also
Include: address and order caching and writes data buffer storage；
Each transform subblock obtains the address ram and order converting unit by the address and order caching
The address information and read/write command of sdram controller IP specification are cached, and the sdram controller IP address and life are passed through
Interface is enabled to read address and the read/write command of the sdram controller IP specification from the address and order caching；
Each transform subblock caches the sdram controller obtained to the RAM write Date Conversion Unit by write data
The data of writing of IP specification are cached；By the sdram controller IP write data-interface from write data caching in read
Sdram controller IP specification writes data；
Wherein, it is synchronous with the sdram controller IP address and command interface from right to write data-interface by the sdram controller IP
Data are read in should caching, by the address of sdram controller IP specification, write order and data is write and is sent to SDRAM together
Controller IP module.
5. the SDRAM control system according to claim 4 based on FPGA, which is characterized in that
The address and order caching, write data caching are FIFO caching.
6. the SDRAM control system according to claim 3 based on FPGA, which is characterized in that each transform subblock is also
It include: that RAM reads Date Conversion Unit and sdram controller IP reading data-interface；
The reading data read from SDRAM are sent to the interface modular converter by the sdram controller IP module；
Corresponding transform subblock is read to read described in data interface by the sdram controller IP in interface modular converter
According to reading Date Conversion Unit by the RAM and the sdram controller IP received the reading data standardized be converted to RAM Interface
The reading data of specification, and the reading data of the RAM Interface specification are sent to RAM Read-write Catrol by RAM Read-write Catrol interface
Module；
RAM Read-write Catrol module receives the reading data of RAM Interface specification and exports.
7. the SDRAM control system according to claim 1 based on FPGA, which is characterized in that the interface modular converter
Including three transform subblocks, the sdram controller IP module includes three controller IP submodules.
8. the SDRAM control system according to claim 7 based on FPGA, which is characterized in that three controller IP
Submodule is respectively as follows: Xilinx sdram controller IP submodule, Altera sdram controller IP submodule and Lattice
Sdram controller IP submodule；
Three transform subblocks are respectively as follows:
For realizing the first transform subblock of RAM Interface specification and the conversion of Xilinx sdram controller IP interface specification；
For realizing the second transform subblock of RAM Interface specification and the conversion of Altera sdram controller IP interface specification；
And submodule is converted for realizing the third of RAM Interface specification and the conversion of Lattice sdram controller IP interface specification
Block.
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| US6076152A (en) * | 1997-12-17 | 2000-06-13 | Src Computers, Inc. | Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem |
| CN101213533A (en) * | 2005-05-04 | 2008-07-02 | Nxp股份有限公司 | Memory controller and method for controlling access to a memory, as well as system comprising a memory controller |
| CN102339261B (en) * | 2011-09-16 | 2015-09-30 | 上海智翔信息科技股份有限公司 | A kind of DDR2SDRAM controller |
| CN105279116B (en) * | 2015-10-08 | 2017-12-01 | 中国电子科技集团公司第四十一研究所 | DDR controller and control method based on FPGA |
| CN105677594B (en) * | 2016-01-20 | 2018-08-10 | 中国人民解放军国防科学技术大学 | Reset, read-write calibration method and the equipment of FPGA device in DDR3 interfaces |
| CN105868134B (en) * | 2016-04-14 | 2018-12-28 | 烽火通信科技股份有限公司 | More mouthfuls of DDR controllers of high-performance and its implementation |
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