CN106292544B - Based on PCIE interface hardware board and its bus control method and system - Google Patents
Based on PCIE interface hardware board and its bus control method and system Download PDFInfo
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- CN106292544B CN106292544B CN201610679826.4A CN201610679826A CN106292544B CN 106292544 B CN106292544 B CN 106292544B CN 201610679826 A CN201610679826 A CN 201610679826A CN 106292544 B CN106292544 B CN 106292544B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/18—Numerical control [NC], i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form
- G05B19/414—Structure of the control system, e.g. common controller or multiprocessor systems, interface to servo, programmable interface controller
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Abstract
The invention discloses based on PCIE interface hardware board and its bus control method and system, which comprises setting has PCIE interface hardware board；Mechatrolink-III bus protocol data transmit-receive is completed based on PCIE interface, realizes PCIE interface communication protocol with FPGA；The address ram of asic chip is mapped in the address PCIE；After control FPGA captures the communication cycle interrupt signal of asic chip generation, converts the signal into PCIE interrupt signal and issue digital control system mainboard；Digital control system receives communication cycle interrupt signal, response data and order data after being mapped by PCIE in address read-write ASIC RAM.The present invention realizes Mechatrolink-III bus protocol by PCIE bus interface, improves the control mode of digital control system；Enhance the real-time and more efficient task schedule of digital control system.
Description
Technical field
The present invention relates to numerically-controlled machine tool bus marco field, more particularly to it is a kind of based on PCIE interface hardware board and
Mechatrolink-III (hereinafter referred to as M-III) bus control method and system based on PCIE.
Background technique
PCI-E, definition: PCI Express is the bus interface of a new generation.Basic conception: the interface root of PCI Express
It is different according to bus bit wide and difference, including X1, X4, X8 and X16(X2 mode will be used for internal interface rather than slot mould
Formula).Shorter PCI Express card, which can be inserted in longer PCI Express slot, to be used.PCI Express interface energy
Enough support hot-swappable, this is also a no small leap.Three kinds of voltages that PCI Express card is supported respectively+3.3V,
3.3Vaux and+12V.
Mechatrolink is the open communications protocol for being used in industrial automation.Mechatrolink-III (with
Lower abbreviation M-III) it is a kind of bus.
Digital control system more and more uses bus mastering mode, since domestic peace river servo occupies staple market at present,
M-III bus will play great role；It is common interfaces for digital control system in open type PCIE interface, is designed based on PCIE
M-III bus control method will not change the hardware configuration of original digital control system, it is easy to accomplish.
Therefore, the existing technology needs to be improved and developed.
Summary of the invention
The technical problem to be solved in the present invention is that in view of the above drawbacks of the prior art, providing one kind and being connect based on PCIE
Mouth hardware board and Mechatrolink-III (hereinafter referred to as M-III) bus control method and system based on PCIE.This hair
Bright purpose is to realize Mechatrolink-III bus protocol by PCIE bus interface, improves the controlling party of digital control system
Formula；The real-time and more efficient task schedule of digital control system can be enhanced in the present invention.
The technical proposal for solving the technical problem of the invention is as follows:
A kind of Mechatrolink-III bus control method based on PCIE, wherein comprising steps of
A, be arranged it is a have PCIE interface hardware board, wherein it is described have PCIE interface hardware board include FPGA
Chip, Mechatrolink-III bus asic chip, network interface chip, multiple network interfaces and ferroelectric memory；The ferroelectricity is deposited
Reservoir is connect with the fpga chip, the fpga chip, and Mechatrolink-III bus asic chip, network interface chip is successively
Connection, and the multiple network interface is respectively connected to the network interface chip；
B, PCIE interface communication protocol is realized with fpga chip on board, wherein PCIE uses internal memory operation mode, interrupts
Using level triggers mode；
C, the address ram of Mechatrolink-III bus asic chip is mapped in the address PCIE, data use 32
Bit data format；
D, after control FPGA captures the communication cycle interrupt signal that Mechatrolink-III bus asic chip generates,
PCIE interrupt signal is converted the signal into, digital control system mainboard is sent to；
E, after digital control system receives communication cycle interrupt signal, address is read and write after being mapped by PCIE
Response data and order data in Mechatrolink-III bus ASIC RAM；
F, the read-only timer register that communication cycle interrupt signal enables board 32 resets, then with the clock of setting
It starts counting, and controls and do not spilt in control period internal timer register；
G, digital control system reads above-mentioned timer register before the arrival of communication cycle interrupt signal, completes digital control system
Task schedule.
The Mechatrolink-III bus control method based on PCIE, wherein further comprise the steps of:
Control periodic sync signals are generated by Mechatrolink-III ASIC, through FPGA acquisition process, are then generated
PCIE tradition level interrupt is sent to after digital control system receives interruption and generates interrupt clear signal, then will receive feedback data
And new instruction is sent, terminate a complete control period in this way.
The Mechatrolink-III bus control method based on PCIE, wherein the method is connect based on PCIE
Mouth completes Mechatrolink-III bus protocol data transmit-receive.
The Mechatrolink-III bus control method based on PCIE, wherein the step C further include: logical
It crosses and data address in Mechatrolink-III bus asic chip is mapped in the address PCIE, digital control system passes through operation
PCIE address date reads and writes M-III ASIC address date.
The Mechatrolink-III bus control method based on PCIE, wherein further include: by realizing board
Timer will control cycle time, and digital control system reads timer time, obtain the locating time location within the control period, with
Carry out the task schedule of digital control system.
The Mechatrolink-III bus control method based on PCIE, wherein the step A further include:
The fpga chip will be written for carrying out the parsing of PCIE interface protocol data after data conversion
In Mechatrolink-III bus asic chip, then by Mechatrolink-III bus asic chip by data with bus lattice
Formula be sent to it is each from the device；
Data address in Mechatrolink-III bus asic chip is mapped in PCIE data address, digital control system
The data read and write in Mechatrolink-III bus asic chip by the read-write address PCIE.
The Mechatrolink-III bus control method based on PCIE, wherein the asic chip is a kind of
IC chip
A kind of Mechatrolink-III bus control system based on PCIE, wherein include:
Module is preset, it is a with PCIE interface hardware board for being arranged, wherein described to have PCIE interface hard
Part board includes fpga chip, and Mechatrolink-III bus asic chip, network interface chip, multiple network interfaces and ferroelectricity are deposited
Reservoir；The ferroelectric memory is connect with the fpga chip, the fpga chip, Mechatrolink-III bus ASIC core
Piece, network interface chip are sequentially connected, and the multiple network interface is respectively connected to the network interface chip；
FPGA control module realizes PCIE interface communication protocol for fpga chip on control board, and wherein PCIE is adopted
With internal memory operation mode, interrupts and use level triggers mode；
Address mapping module, for by the address ram of Mechatrolink-III bus asic chip with being mapped to PCIE
In location, data use 32 bit data formats；
Capture module captures the communication cycle of Mechatrolink-III bus asic chip generation for controlling FPGA
After interrupt signal, PCIE interrupt signal is converted the signal into, is sent to digital control system mainboard；
Module for reading and writing, for controlling after digital control system receives communication cycle interrupt signal, address after being mapped by PCIE
Read and write the response data and order data in M-III ASIC RAM；
Read control module, the read-only timer register for enabling board 32 for communication control cycle interruption signal are multiple
Position, is then started counting with the clock of setting, and is controlled and do not spilt in control period internal timer register；
Timer register reads control unit, for controlling digital control system before the arrival of communication cycle interrupt signal, reads
Above-mentioned timer register is taken, the task schedule of digital control system is completed.
One kind being based on PCIE interface hardware board, wherein including fpga chip, Mechatrolink-III bus ASIC core
Piece, network interface chip, multiple network interfaces and ferroelectric memory；The ferroelectric memory is connect with the fpga chip, the FPGA
Chip, Mechatrolink-III bus asic chip, network interface chip is sequentially connected, and the multiple network interface is respectively connected to
The network interface chip,
The fpga chip will be written for carrying out the parsing of PCIE interface protocol data after data conversion
In Mechatrolink-III bus asic chip, then by Mechatrolink-III bus asic chip by data with bus lattice
Formula be sent to it is each from the device；
Data address in Mechatrolink-III bus asic chip is mapped in PCIE data address, digital control system
The data read and write in Mechatrolink-III bus asic chip by the read-write address PCIE.
It is described based on PCIE interface hardware board, wherein the asic chip is a kind of IC chip
Mechatrolink-III (following letter provided by the present invention based on PCIE interface hardware board and based on PCIE
Claim M-III) bus control method and system, the purpose of the present invention is realize Mechatrolink-III by PCIE bus interface
Bus protocol improves the control mode of digital control system；The present invention can be enhanced the real-time of digital control system and more efficient appoint
Business scheduling.
Detailed description of the invention
Fig. 1 is a kind of Mechatrolink-III bus control method flow chart based on PCIE that the present invention is implemented.
Fig. 2 is a kind of structural schematic diagram of the preferred embodiment based on PCIE interface hardware board of the present invention.
Fig. 3 show the address PCIE and M-III ASIC address relationship structural schematic diagram.
It is to control period position structure at digital control system current time to show that Fig. 4, which is shown in the method embodiment,
It is intended to.
Fig. 5 is a kind of Mechatrolink-III bus control system principle of work and power frame based on PCIE that the present invention is implemented
Figure.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer and more explicit, right as follows in conjunction with drawings and embodiments
The present invention is further described.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and do not have to
It is of the invention in limiting.
Fig. 2 is referred to, Fig. 2 is a kind of structural representation of the preferred embodiment based on PCIE interface hardware board of the present invention
Figure.As shown in Fig. 2, one kind that first embodiment of the invention provides is based on PCIE interface hardware board, including (scene can compile FPGA
Journey gate array) chip, M-III asic chip, network interface chip, multiple network interfaces and FRAM memory,
Wherein, fpga chip is field programmable gate array, and M-III asic chip is Mechatrolink-III bus
Asic chip.Wherein ASIC is the english abbreviation of Application Specific Integrated Circuit, in integrated electricity
Road circle is considered as a kind of integrated circuit designed for special purpose.FRAM memory is ferroelectric memory.
In the present invention, the FRAM memory is connect with the fpga chip, the fpga chip, M-III ASIC core
Piece, network interface chip are sequentially connected, and multiple network interfaces are respectively connected to the network interface chip, and FPGA completion PCIE connects in the present invention
The parsing of mouthful protocol data will be written in M-III asic chip after data conversion, then by M-III asic chip by data with total
Line format be sent to it is each from the device.
Data address in M-III asic chip is mapped in PCIE data address in present invention design, therefore numerical control system
The data that system will be read and write in M-III ASIC by the read-write address PCIE.
The timer based on onboard clock is completed in present invention design, digital control system can read the timer by PCIE
The time in positioned control period is judged with this.
Referring to Fig.1, Fig. 1 is a kind of Mechatrolink-III bus control method stream based on PCIE that the present invention is implemented
Cheng Tu.As shown in Figure 1, present invention implementation additionally provides a kind of Mechatrolink-III (hereinafter referred to as M- based on PCIE
III) bus control method, the method for the present invention specific implementation the following steps are included:
S10, setting are a with PCIE interface hardware board, wherein described to include with PCIE interface hardware board
Fpga chip, Mechatrolink-III bus asic chip, network interface chip, multiple network interfaces and ferroelectric memory；The iron
Electrical storage is connect with the fpga chip, the fpga chip, Mechatrolink-III bus asic chip, network interface chip
It is sequentially connected, and the multiple network interface is respectively connected to the network interface chip；As shown in Fig. 2, the present invention is in the specific implementation
It needs to preset based on PCIE interface hardware board described in a Fig. 2 embodiment, specifically as described above.
S20, PCIE interface communication protocol is realized with fpga chip on board, wherein PCIE uses internal memory operation mode, in
It is disconnected to use level triggers mode；
S30, the address ram of Mechatrolink-III bus asic chip is mapped in the address PCIE, data use
32 bit data formats.M-III asic chip (Mechatrolink-III bus asic chip) address ram is mapped to
In the address PCIE, data use 32 bit data formats；
S40, control FPGA capture the communication cycle interrupt signal of Mechatrolink-III bus asic chip generation
Afterwards, PCIE interrupt signal is converted the signal into, digital control system mainboard is sent to；
After S50, digital control system receive communication cycle interrupt signal, address is read and write after being mapped by PCIE
Response data and order data in Mechatrolink-III bus ASIC RAM；
S60, communication cycle interrupt signal enable board 32 read-only timer register reset, then with setting when
Clock starts counting, and controls and do not spill in control period internal timer register；
S70, digital control system read above-mentioned timer register, complete numerical control system before the arrival of communication cycle interrupt signal
The task schedule of system.
According to M-III after using PCIE protocol, board to parse data between digital control system in present invention implementation
Bus data format is sent to respectively from the device.
Fig. 2 is a kind of structural schematic diagram of the preferred embodiment based on PCIE interface hardware board of the present invention, wherein data
It is generated by open control system, is sent to the present invention by PCIE interface and implements in the board, converting by FPGA will
Data are sent in Mechatrolink-III asic chip, then are sent to respectively from the device by asic chip by network interface；Control
Periodic sync signals processed are generated by Mechatrolink-III ASIC, through FPGA acquisition process, then generate PCIE tradition level
It interrupts, digital control system generates interrupt clear signal after receiving interruption, then will receive feedback data and send new instruction, in this way
Terminate a complete control period.
Fig. 3 show the address PCIE and M-III ASIC address relationship structural schematic diagram, when digital control system reads and writes M-III
In ASIC when data, as long as read-write PCIE corresponding address.Wherein:
First: 0xFC00-0xFCFF, correspond to address of cache parameter；
Second: 0xFB00-0xFBFF corresponds to communications parameter；
Third: 0x8034+rbadr corresponds to response data start address；
4th: 0x8034+cbadr corresponds to order data start address；
5th: 0x0036C, correspond to response first address register (rbadr)；
6th: 0x0038, correspond to order first address register (cbadr)；
And Fig. 4 is shown when digital control system needs to know and controls period position at current time, can be carried with read plate
The subdivision of control period can be facilitated the task schedule of digital control system by timer time, this method.
Mechatrolink-III bus control method described in the embodiment of the present invention based on PCIE, using based on PCIE
Interface completes M-III bus protocol data transmit-receive.By by M-III ASIC data address of cache into the address PCIE, numerical control system
System reads and writes M-III ASIC address date by operation PCIE address date.And by realizing that board timer will control
Cycle time refinement, digital control system, which reads timer time, can accurately know the locating time location within the control period, have
Help the task schedule of digital control system.
Based on above method embodiment, the present invention also provides a kind of total line traffic controls of the Mechatrolink-III based on PCIE
System processed, as shown in figure 5, the system comprises:
Module 210 is preset, it is a with PCIE interface hardware board for being arranged, wherein described to be connect with PCIE
Mouth hardware board includes fpga chip, Mechatrolink-III bus asic chip, network interface chip, multiple network interfaces, Yi Jitie
Electrical storage；The ferroelectric memory is connect with the fpga chip, the fpga chip, Mechatrolink-III bus
Asic chip, network interface chip are sequentially connected, and the multiple network interface is respectively connected to the network interface chip；Specific institute as above
It states.
FPGA control module 220 realizes PCIE interface communication protocol for fpga chip on control board, wherein PCIE
Using internal memory operation mode, interrupts and use level triggers mode；As detailed above.
Address mapping module 230, for the address ram of Mechatrolink-III bus asic chip to be mapped to PCIE
In address, data use 32 bit data formats；As detailed above.
Capture module 240 captures the communication of Mechatrolink-III bus asic chip generation for controlling FPGA
After cycle interruption signal, PCIE interrupt signal is converted the signal into, is sent to digital control system mainboard；As detailed above.
Module for reading and writing 250, for controlling after digital control system receives communication cycle interrupt signal, after being mapped by PCIE
Response data and order data in M-III ASIC RAM are read and write in location；As detailed above.
Read control module 260 enables the read-only timer deposit of board 32 for communication control cycle interruption signal
Device resets, and is then started counting with the clock of setting, and controls and do not spill in control period internal timer register；It is specific as above
It is described.
Timer register reads control unit 270, for controlling digital control system before the arrival of communication cycle interrupt signal,
Above-mentioned timer register is read, the task schedule of digital control system is completed；As detailed above.
In conclusion provided by the present invention based on PCIE interface hardware board and based on the Mechatrolink- of PCIE
III (hereinafter referred to as M-III) bus control method and system, the purpose of the present invention is realized by PCIE bus interface
Mechatrolink-III bus protocol improves the control mode of digital control system；The reality of digital control system can be enhanced in the present invention
When property and more efficient task schedule.
Certainly, those of ordinary skill in the art will appreciate that realizing all or part of the process in above-described embodiment method,
It is that related hardware (such as processor, controller etc.) can be instructed to complete by computer program, the program can store
In a computer-readable storage medium, which may include the process such as above-mentioned each method embodiment when being executed.Its
Described in storage medium can be for memory, magnetic disk, CD etc..
It should be understood that the application of the present invention is not limited to the above for those of ordinary skills can
With improvement or transformation based on the above description, all these modifications and variations all should belong to the guarantor of appended claims of the present invention
Protect range.
Claims (10)
1. a kind of Mechatrolink-III bus control method based on PCIE, which is characterized in that comprising steps of
A, be arranged it is a have PCIE interface hardware board, wherein it is described have PCIE interface hardware board include fpga chip,
Mechatrolink-III bus asic chip, network interface chip, multiple network interfaces and ferroelectric memory；The ferroelectric memory
It is connect with the fpga chip, the fpga chip, Mechatrolink-III bus asic chip, network interface chip successively connects
It connects, and the multiple network interface is respectively connected to the network interface chip；
B, PCIE interface communication protocol is realized with fpga chip on board, wherein PCIE uses internal memory operation mode, interrupts and uses
Level triggers mode；
C, the address ram of Mechatrolink-III bus asic chip is mapped in the address PCIE, data use 32 digits
According to format；
D, after control FPGA captures the communication cycle interrupt signal that Mechatrolink-III bus asic chip generates, by this
Signal is converted into PCIE interrupt signal, is sent to digital control system mainboard；
E, after digital control system receives communication cycle interrupt signal, Mechatrolink-III is read and write in address after being mapped by PCIE
Response data and order data in bus ASIC RAM；
F, the read-only timer register that communication cycle interrupt signal enables board 32 resets, and is then started with the clock of setting
It counts, and controls and do not spilt in control period internal timer register；
G, digital control system reads above-mentioned timer register before the arrival of communication cycle interrupt signal, completes appointing for digital control system
Business scheduling.
2. the Mechatrolink-III bus control method according to claim 1 based on PCIE, which is characterized in that also
Comprising steps of
Control periodic sync signals are generated by Mechatrolink-III ASIC, through FPGA acquisition process, are then generated PCIE and are passed
System level interrupt is sent to after digital control system receives interruption and generates interrupt clear signal, then will reception feedback data and transmission
New instruction terminates a complete control period in this way.
3. the Mechatrolink-III bus control method according to claim 1 based on PCIE, which is characterized in that institute
It states method and is based on PCIE interface completion Mechatrolink-III bus protocol data transmit-receive.
4. the Mechatrolink-III bus control method according to claim 1 based on PCIE, which is characterized in that institute
State step C further include: by the way that data address in Mechatrolink-III bus asic chip is mapped in the address PCIE, number
Control system reads and writes Mechatrolink-III ASIC address date by operation PCIE address date.
5. the Mechatrolink-III bus control method according to claim 1 based on PCIE, which is characterized in that also
It include: by realizing that board timer will control cycle time, digital control system reads timer time, obtains in the control period
Interior locating time location, to carry out the task schedule of digital control system.
6. the Mechatrolink-III bus control method according to claim 1 based on PCIE, which is characterized in that institute
State step A further include:
For carrying out the parsing of PCIE interface protocol data Mechatrolink-III will be written after data conversion in the fpga chip
In bus asic chip, then by Mechatrolink-III bus asic chip sent data to bus format each from setting
In standby；
Data address in Mechatrolink-III bus asic chip is mapped in PCIE data address, digital control system passes through
The data for reading and writing the address PCIE to read and write in Mechatrolink-III bus asic chip.
7. the Mechatrolink-III bus control method according to claim 1 based on PCIE, which is characterized in that institute
Stating asic chip is a kind of IC chip.
8. a kind of Mechatrolink-III bus control system based on PCIE characterized by comprising
Module is preset, it is a with PCIE interface hardware board for being arranged, wherein described that there is PCIE interface hardware plate
Card includes fpga chip, Mechatrolink-III bus asic chip, network interface chip, multiple network interfaces and ferroelectric memory；
The ferroelectric memory is connect with the fpga chip, the fpga chip, Mechatrolink-III bus asic chip, net
Mouth chip is sequentially connected, and the multiple network interface is respectively connected to the network interface chip；
FPGA control module realizes PCIE interface communication protocol for fpga chip on control board, wherein in PCIE use
Operation mode is deposited, interrupts and uses level triggers mode；
Address mapping module, for the address ram of Mechatrolink-III bus asic chip to be mapped in the address PCIE,
Data use 32 bit data formats；
Capture module, the communication cycle that the generation of Mechatrolink-III bus asic chip is captured for controlling FPGA interrupt
After signal, PCIE interrupt signal is converted the signal into, is sent to digital control system mainboard；
Module for reading and writing, for controlling after digital control system receives communication cycle interrupt signal, address is read and write after being mapped by PCIE
Response data and order data in Mechatrolink-III ASIC RAM；
Read control module, the read-only timer register for enabling board 32 for communication control cycle interruption signal reset,
Then it is started counting with the clock of setting, and controls and do not spilt in control period internal timer register；
Timer register reads control unit, for controlling digital control system before the arrival of communication cycle interrupt signal, in reading
Timer register is stated, the task schedule of digital control system is completed.
9. one kind is based on PCIE interface hardware board, which is characterized in that including fpga chip, Mechatrolink-III bus
Asic chip, network interface chip, multiple network interfaces and ferroelectric memory；The ferroelectric memory is connect with the fpga chip, institute
Fpga chip, Mechatrolink-III bus asic chip are stated, network interface chip is sequentially connected, and the multiple network interface is distinguished
It is connected to the network interface chip,
For carrying out the parsing of PCIE interface protocol data Mechatrolink-III will be written after data conversion in the fpga chip
In bus asic chip, then by Mechatrolink-III bus asic chip sent data to bus format each from setting
In standby；PCIE interface communication protocol is realized with fpga chip on board, and wherein PCIE uses internal memory operation mode, interrupts using electricity
Flat triggering mode；
Data address in Mechatrolink-III bus asic chip is mapped in PCIE data address, data use 32
Data format；The data that digital control system is read and write in Mechatrolink-III bus asic chip by the read-write address PCIE；
After control FPGA captures the communication cycle interrupt signal of Mechatrolink-III bus asic chip generation, by the letter
Number it is converted into PCIE interrupt signal, is sent to digital control system mainboard.
10. according to claim 9 be based on PCIE interface hardware board, which is characterized in that the asic chip is a kind of
IC chip.
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| CN113341841B (en) * | 2021-06-28 | 2022-05-31 | 哈尔滨工业大学 | Real-time motion control system and method based on PCIe bus protocol |
| CN116055243A (en) * | 2022-09-27 | 2023-05-02 | 上海创贤半导体有限公司 | Method for controlling system address mapping of power semiconductor wire bonding machine |
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