CN113341841B - Real-time motion control system and method based on PCIe bus protocol - Google Patents
Real-time motion control system and method based on PCIe bus protocol Download PDFInfo
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- CN113341841B CN113341841B CN202110719911.XA CN202110719911A CN113341841B CN 113341841 B CN113341841 B CN 113341841B CN 202110719911 A CN202110719911 A CN 202110719911A CN 113341841 B CN113341841 B CN 113341841B
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Abstract
A real-time motion control system and method based on PCIe bus protocol belongs to the technical field of high-speed data transmission and real-time motion control in modern motion control. The invention solves the problems of closed control structure, poor compatibility and lack of real-time motion control function of the traditional motion control system. The real-time motion control system comprises the industrial personal computer, the bottom layer motion control module, the user interface module, the PCIe board card designed based on the PCIe bus protocol and the PCIe adapter board, the designed system is high in data transmission rate, strong in motion control real-time performance, excellent in compatibility with traditional bus equipment, open in control system and capable of conveniently adding other peripheral equipment or being linked with the traditional PCI bus system. The invention can be applied to the fields of high-speed data transmission and real-time motion control in motion control.
Description
Technical Field
The invention belongs to the technical field of high-speed data transmission and real-time motion control in modern motion control, and particularly relates to a real-time motion control system and method based on a PCIe bus protocol.
Background
With the development of automation and intellectualization of modern industrial control systems, the requirements on the real-time performance, stability and the like of motion control are higher and higher, and how to realize higher-speed data acquisition and transmission is a difficult point of real-time motion control in the fields of numerical control processing, chemical engineering, intelligent manufacturing, national defense guidance and the like.
The PCIe bus protocol adopts point-to-point high-speed serial transmission, and can realize data transmission with high performance, high bandwidth, high reliability and high expandability by using modes of differential low-voltage signals, embedded clocks and the like. At present, the PCIe bus has replaced the traditional parallel bus to become the mainstream interconnection bus in the microcomputer system, and is widely applied to the interconnection of computers and communication peripherals. Compared with the common LAN bus, the PCIe bus has greater transmission advantages within a certain distance, larger data transmission bandwidth and more stable data transmission process. And the bandwidth of each channel of the PCIe bus is independent, so that the PCIe bus can be suitable for multiple interface occasions, and the field system maintenance is more convenient. Therefore, the research of the real-time motion control scheme based on PCIe high-speed data transmission is developed, the possibility is provided for solving the defects of closed control structure, poor compatibility, lack of real-time function and the like of the traditional motion control system, and the development of domestic modern industrial control and autonomous intelligent control is facilitated.
Disclosure of Invention
The invention aims to solve the problems of closed control structure, poor compatibility and lack of a real-time motion control function of the traditional motion control system, and provides a real-time motion control system and a real-time motion control method based on a PCIe bus protocol.
The technical scheme adopted by the invention for solving the technical problems is as follows:
the utility model provides a real-time motion control system based on PCIe bus protocol, the system includes industrial computer, bottom layer motion control module, user interface module, PCIe integrated circuit board and PCIe keysets based on PCIe bus protocol design, wherein:
the PCIe board card is used for mapping all control interfaces of the bottom layer motion control module to an address space of an industrial personal computer, and completing the analysis of a PCIe bus protocol, the generation of motion control signals and the filtering and frequency doubling processing of photoelectric coded disc signals;
the PCIe patch board is used for summarizing and transforming data fed back by the bottom layer motion control module, and the transformed data are transmitted to the industrial personal computer through the PCIe board card;
the user interface module is used for setting a motion control target, the industrial personal computer generates a motion control command according to the motion control target, the PCIe board card generates a control signal according to the motion control command of the industrial personal computer, and the control signal is transmitted to the bottom layer motion control module through the PCIe adapter plate.
Furthermore, the PCIe adapter plate is used for converting data fed back by the bottom layer motion control module, and the conversion mode comprises level conversion of an output signal of the photoelectric encoder and optical coupling isolation of the output signal of the photoelectric switch.
Furthermore, the system also comprises a CAN bus which is used as a standby mode for the communication between the industrial personal computer and the bottom layer motion control module, and when the PCIe bus communication fails, the CAN bus is used for completing the communication and the motion control.
Further, the PCIe board is provided with the MCU-XE164FN, and when PCIe bus communication fails, the control center is moved down to the MCU-XE164FN from the industrial personal computer.
Further, a chip used for analyzing a bus protocol and used for the PCIe bus is PEX8311, the PCIe board generates a control signal according to a motion control command of the industrial personal computer, and the chip used is a motion control chip X7043.
Furthermore, the system adopts an FPGA-XC3S500E chip to analyze signals of a PEX8311 local side bus, generate control signals of a chip X7043 and filter and frequency-doubling photoelectric code disc signals.
Further, an X7043 chip of the PCIe board card generates a control signal according to a motion control command of the industrial personal computer, and the specific process is as follows:
step S1, judging the state of the address effective signal ADS of the X7043, if the address effective signal ADS is in high level, keeping the initial state idle, waiting for the low level of the address effective signal ADS, and judging the level of the read-write operation signal WR when the address effective signal ADS is in low level;
if WR is high, go to step S2;
if WR is low, go to step S3;
step S2, judging whether the enable signal of the X7043 is effective;
if the enable signal is valid, then the write operation to X7043 is valid;
the write sequence includes three states in total: write _ one, Write _ two, and Write _ three; waiting for a data preparation completion signal BLAST to be effective in a Write _ one state, entering a Write _ two state when data preparation is completed, enabling chip selection of the X7043 in the Write _ two state, starting to Write data to the X7043, continuing to Write in the Write _ three state to meet the requirement of pulse width, jumping to a finish state after the Write operation is finished, initializing all output registers, and returning to an initial state idle;
if the enable signal is invalid, judging whether the write operation is valid again, if the result of the judgment again is that the write operation is valid, executing the write sequence process, otherwise, keeping an initial state idle, and waiting for operation X7043 or the write operation to be valid;
step S3, judging whether the enable signal of the X7043 is effective;
if the enable signal is valid, then the read operation for X7043 is valid;
the read timing includes three states in total: waiting for address stabilization in a Read _ one state, then transferring to a Read _ ready state, performing chip selection enabling on the X7043 in the Read _ ready state, enabling a Read enable pin of the X7043 to be effective, starting reading data from the X7043 when jumping to the Read _ two state data stabilization, then jumping to a finish state, and initializing all output registers;
if the enable signal is invalid, judging whether the operation of reading the register is valid, if the judged result is that the operation of reading the register is invalid, keeping an initial state idle, and waiting for the operation X7043 or the signal of reading the register to be valid; if the judged result is that the register reading operation is effective, the state jumps to a Read _ reg state, the content in the register is copied to an output register, then the state is switched to a finish state, all output registers are initialized, and the initial state idle is jumped back;
step S4, if none of the above states can respond to the external event, enter default state, initialize all output registers and jump back to initial state idle.
Further, the filtering and frequency doubling processing are performed on the photoelectric coded disc signal, and the specific process of the filtering processing is as follows:
establishing an array with fixed length, assigning the value with phase updating into the array in a way that new data enters from low position and old data exits from high position, counting the high and low level states in the whole array, setting the current phase value high when the high level in the array accounts for the majority, and setting the current phase value low when the low level in the array accounts for the majority.
Furthermore, the filtering and frequency doubling processing are performed on the photoelectric coded disc signal, and the specific process of the frequency doubling processing is as follows:
the state of the filtered signal is coded by level signals of A and B phases of the photoelectric code disc, and the state jumps to: 00- >10- >11- >01- >00, and the counter counts up at this time; the state jumps to: 00- >01- >11- >10- >00, and the counter counts down at this time; and all other state jumps are invalid jumps and no counting operation is carried out.
A real-time motion control method based on PCIe bus protocol specifically comprises the following steps:
loading rtdll by using a LoadLibrary () function;
obtaining addresses of PCIe _ Search (), PCIe _ Init (), PCIe _ RegAddr () and PCIe _ Cleanup () functions from rtdll;
and searching and initializing PCIe equipment by using PCIe _ Search (), PCIe _ Init (), PCIe _ RegAddr () and PCIe _ Cleanup () functions, mapping addresses of the PCIe equipment to a virtual space of the RTX process, starting PCIe configuration, interrupt configuration and motor initialization configuration after mapping is finished, and then opening a shared memory to obtain a data command transmitted from a user display interface and executing a corresponding task.
The beneficial effects of the invention are: the invention provides a real-time motion control system and a method based on PCIe bus protocol, and the method of the invention has the following advantages:
1. the real-time motion control scheme based on the PCIe bus protocol has the main advantages of high data transmission rate, strong real-time motion control, long effective distance of the control scheme, low power consumption and the like.
2. The effective transmission bandwidth of the PCIe bus adopted by the invention is far higher than that of the traditional PCI bus, and the data is transmitted in a serial data packet mode, so each pin of the PCIe bus interface can obtain more bandwidth than that of the traditional I/O standard, and the production cost and the volume of a PCIe device can be reduced.
3. Since the PCIe bus is developed from the inheritance of the PCI/PCI-X bus, the PCIe bus scheme of the present invention is almost a fully compatible PCI/PCI-X device at the application layer (in software); on the hardware level, interfacing with PCIe to PCI/PCI-X bridges may be accomplished via the PCIe to PCI/PCI-X bridges. Therefore, the invention has excellent compatibility with the traditional bus equipment and is more beneficial to the application and the expansion of the motion control scheme.
4. Compared with the single-ended signal of the traditional bus, the PCIe differential bus signal used by the invention has stronger anti-interference capability. Because the differential signals require equal length, equal width and close proximity during wiring and are on the same layer, external interference noise is loaded on the two differential signals by equal value and at the same time, the difference is 0 under the ideal condition, and the interference influence on the signal logic value is small.
5. The PCIe bus scheme of the invention can effectively inhibit electromagnetic interference, and the device and the equipment thereof have little electromagnetic interference to the outside and are environment-friendly. Because the two differential signals are very close in distance, the amplitudes of the signals are equal, the polarities of the signals are opposite, the amplitudes of the coupling electromagnetic fields between the two lines and the ground line are equal, and the coupling electromagnetic fields are mutually offset, so that the electromagnetic interference to the outside is small.
6. The PCIe bus researched by the invention also has a network communication technology, supports various data routing modes and data transmission modes based on multiple channels, effectively simplifies the use process and is convenient for users to transplant and develop different platforms. The control system of the invention is open, and other peripheral devices can be conveniently added or the traditional PCI bus system can be conveniently linked.
Drawings
FIG. 1 is an overall block diagram of a real-time motion control system based on the PCIe bus protocol;
FIG. 2 is a PCIe multi-axis motion control panel card design block diagram;
FIG. 3 is a state transition diagram of a three-stage state machine of the FPGA;
FIG. 4 is a diagram of AB phase state transition and quad frequency counting;
fig. 5 is a control flow diagram of a real-time motion control system based on PCIe bus protocol.
Detailed Description
In a first specific embodiment, the real-time motion control system based on the PCIe bus protocol in this embodiment includes an industrial personal computer, a bottom motion control module, a user interface module, a PCIe board card designed based on the PCIe bus protocol, and a PCIe patch board, where:
the PCIe board card is used for mapping all control interfaces (motor drivers and motion axis sensors) of the bottom layer motion control module to an address space of the industrial personal computer, and completing analysis of a PCIe bus protocol, generation of multi-axis motion control signals and filtering and frequency multiplication processing of photoelectric coded disc signals;
the PCIe patch board is used for summarizing and transforming data fed back by the bottom layer motion control module, and the transformed data are transmitted to the industrial personal computer through the PCIe board card;
the user interface module is used for setting a motion control target, the industrial personal computer generates a motion control command according to the motion control target, the PCIe board card generates a control signal according to the motion control command of the industrial personal computer, and the control signal is transmitted to the bottom layer motion control module through the PCIe adapter plate.
The industrial personal computer is the central pivot of the whole real-time motion control system, and a user can control the bottom layer motion control module in real time through the industrial personal computer, including the trajectory planning and tracking control of the robot.
The second embodiment is as follows: the PCIe interposer is configured to convert data fed back by the bottom layer motion control module, and the conversion mode includes performing level conversion on an output signal of the photoelectric encoder and performing optical coupling isolation on an output signal of the photoelectric switch.
The third concrete implementation mode: the difference between the second embodiment and the second embodiment is that the system further comprises a CAN bus, the CAN bus is used as a standby mode for the communication between the industrial personal computer and the bottom layer motion control module, and when the PCIe bus communication fails, the CAN bus is used for completing the communication and the motion control.
The fourth concrete implementation mode: the third difference between the embodiment and the specific embodiment is that the PCIe board card is configured with the MCU-XE164FN, the MCU-XE164FN is a control system of a standby fuse, and when the PCIe bus high-speed communication fails under an uncontrollable condition, the control hub is moved down from the industrial personal computer to the MCU-XE164FN, thereby ensuring absolute feasibility of the hardware platform motion.
The fifth concrete implementation mode: the difference between this embodiment and the specific embodiment is that the PCIe bus uses a chip for analyzing a bus protocol as PEX8311, the PCIe board generates a control signal according to a motion control command of the industrial personal computer, and the used chip is a motion control chip X7043.
The PCIe bus protocol resolution scheme adopts a PCIe protocol analysis chip PEX8311 to convert a complex PCIe bus protocol into a simple local high-speed serial bus similar to a PCI bus protocol. The solution of the bottom layer motion control module adopts a motion control chip X7043 to realize the motion control of the multi-axis motion system. The logic analysis of the local side bus of the PEX8311 and the processing of the X7043 control interface are realized by the FPGA-XC3S 500E.
The difference between the sixth specific embodiment and the fifth specific embodiment is that the system adopts an FPGA-XC3S500E chip to perform signal analysis on the PEX8311 local side bus, generate a control signal on the chip X7043, and perform filtering and frequency doubling processing on a photoelectric encoder signal.
A seventh specific implementation mode and a sixth specific implementation mode of the present invention are different in that the X7043 chip of the PCIe board generates a control signal according to a motion control command of the industrial personal computer, and a specific process of the control signal is as follows:
step S1, judging the state of the address effective signal ADS of the X7043, if the address effective signal ADS is in high level, keeping the initial state idle, waiting for the low level of the address effective signal ADS, and judging the level of the read-write operation signal WR when the address effective signal ADS is in low level;
if WR is high, go to step S2;
if WR is low, go to step S3;
step S2, judging whether the enable signal of the X7043 is effective;
if the enable signal is valid, then the write operation to X7043 is valid;
the write sequence includes three states in total: write _ one, Write _ two, and Write _ three; waiting for a data preparation completion signal BLAST to be effective in a Write _ one state, entering a Write _ two state when data preparation is completed, enabling chip selection of the X7043 in the Write _ two state, starting to Write data to the X7043, continuing to Write in the Write _ three state to meet the requirement of pulse width, jumping to a finish state after the Write operation is finished, initializing all output registers, and returning to an initial state idle;
because the minimum Write pulse width is 16ns, and the clock period of the board card is 15ns, the Write operation needs to be continued in the Write _ three state to meet the time requirement;
if the enable signal is invalid, judging whether the write operation is valid again, if the result of the judgment again is that the write operation is valid, executing the write sequence process, otherwise, keeping an initial state idle, and waiting for operation X7043 or the write operation to be valid;
step S3, judging whether the enable signal of the X7043 is effective;
if the enable signal is valid, then the read operation for X7043 is valid;
the read timing includes three states in total: the method comprises the steps that Read _ one, Read _ ready and Read _ two, address stabilization is waited under a Read _ one state, waiting for 15ns in one period is completed, then the Read _ ready state is switched to, under the Read _ ready state, X7043 is enabled by chip selection, a Read enable pin of X7043 is enabled, and the reason that reading operation is not carried out immediately is to wait for data on a data bus to be stable (about 20ns), so that data is Read from X7043 when the data is switched to the Read _ two state and is stabilized, then the data is switched to a finish state, and all output registers are initialized;
if the enabling signal is invalid, judging whether the register reading operation is valid, if the judging result is that the register reading operation is invalid, keeping an initial state idle, and waiting for operation X7043 or the register reading signal to be valid; if the judged result is that the register reading operation is effective, the state jumps to a Read _ reg state, the content in the register is copied to an output register, then the state is switched to a finish state, all output registers are initialized, and the initial state idle is jumped back;
step S4, if none of the above states can respond to the external event, enter default state, initialize all output registers and jump back to initial state idle.
The eighth specific embodiment and the seventh specific embodiment are different in that the filtering and frequency doubling processing is performed on the photoelectric encoder signal, and the specific process of the filtering processing is as follows:
establishing an array with fixed length, assigning the value of phase update into the array in a way that new data enters from low position and old data exits from high position, thus ensuring the phase update value with a certain length, counting the high and low level states in the whole array, setting the current phase value high when the high level in the array accounts for most, and setting the current phase value low when the low level in the array accounts for most. By the operation, clutter to a certain degree can be filtered, particularly clutter with a small period can be filtered, the signal processing efficiency is effectively improved, and the processing cost is saved.
The ninth specific embodiment and the eighth specific embodiment are different in that the filtering and frequency doubling processing are performed on the photoelectric encoder signal, and the specific process of the frequency doubling processing is as follows:
the state of the filtered signal is coded by the level signals of A and B phases of the photoelectric code disc, and as can be seen from FIG. 4, the state jumps to: 00- >10- >11- >01- >00, and the counter counts up at this time; the state jumps to: 00- >01- >11- >10- >00, and the counter counts down at this time; and all other state jumps are invalid jumps and no counting operation is carried out.
The pulse output capacity of the motor is improved through frequency multiplication, so that the pulse resolution of the photoelectric code disc and the control precision of the scheme are effectively improved, and the scheme performs quadruple frequency processing on the photoelectric code disc signals.
A PCIe bus protocol-based real-time motion control method described in the fifth embodiment specifically includes the following steps:
loading rtdll by using a LoadLibrary () function;
then obtaining addresses of PCIe _ Search (), PCIe _ Init (), PCIe _ RegAddr () and PCIe _ Cleanup () functions from rtdll so as to facilitate subsequent calling operation;
and searching and initializing PCIe equipment by using PCIe _ Search (), PCIe _ Init (), PCIe _ RegAddr () and PCIe _ Cleanup () functions, mapping addresses of the PCIe equipment to a virtual space of an RTX process, starting PCIe configuration, interrupt configuration and motor initialization configuration after mapping is completed, and then opening a shared memory to obtain a data command transmitted from a Win32 user display interface and executing a corresponding task.
The PCIe _ Search () function is used for addressing and positioning the board card; the PCIe _ Init () function is used for base address mapping and device initialization; the PCIe _ RegAddr () function is used for register address setting; the PCIe _ Cleanup () function is used to end the board process and exit the program, and rtdll is the form of the dynamic link library of the RTX system.
Example 1:
the embodiment is described with reference to fig. 1 to fig. 5, and a real-time trajectory planning control scheme of an R-Theta type silicon wafer transfer robot based on PCIe bus protocol is described in the embodiment. The silicon wafer transmission mechanical arm system has three-axis freedom degree, can realize radial motion (R axis), rotational motion (Theta axis) and up-and-down motion (Z axis), and is one of core technologies of the silicon wafer automatic transmission system based on the three-axis motion trajectory planning. On one hand, the running speed of the mechanical arm can directly influence the transmission speed of the silicon wafer, and the production efficiency is determined; on the other hand, the trajectory planning of the mechanical arm needs to consider the real-time performance and stability of the control scheme, and the unstable trajectory may cause the vibration of the tail end of the mechanical arm, which may cause the collision between the wafer and the wafer cassette. Therefore, an effective real-time multi-axis motion control scheme is researched, and the method has important significance for the trajectory planning control of the R-Theta type silicon wafer transmission mechanical arm.
A real-time trajectory planning control scheme of an R-Theta type silicon wafer transmission mechanical arm based on a PCIe bus protocol is shown in fig. 1, and the scheme is to design a PCIe board card for controlling multi-joint motion of the mechanical arm based on the PCIe bus protocol, as shown in fig. 2, and develop an FPGA three-stage state machine program and a quadruple frequency counting state machine, as shown in fig. 3 and fig. 4. The PCIe board card can generate an S-shaped speed planning pulse signal, and the motor can be controlled quickly and stably. The scheme adopts an RTX real-time operating system to develop a driver of a PCIe bus protocol to complete an RTX real-time motion control program, as shown in fig. 5. And finally, based on an R-Theta type silicon wafer transmission mechanical arm system, the researched real-time trajectory planning algorithm is tested, and the rapid and stable trajectory planning control of the silicon wafer transmission mechanical arm can be realized.
Example 2:
the embodiment is described with reference to fig. 1 to fig. 5, and the embodiment describes a real-time contour tracking control scheme for a gantry type X-Y linear motor platform based on PCIe bus protocol. The gantry type X-Y linear motor platform is provided with an X axis and two Y axes to realize positioning and tracking on a plane, and the contour tracking control problem belongs to multi-axis tracking control. In an actual platform system, parameters between the axes are often not well matched, and single-axis tracking control cannot reasonably control the axes to work in cooperation, so that a more effective multi-axis motion control scheme is needed to further improve the contour tracking precision of the platform system.
The real-time contour tracking control scheme of the gantry type X-Y linear motor platform based on the PCIe bus protocol is shown in figure 1, and the scheme controls the PCIe board card based on the multi-axis motion of the PCIe bus protocol, as shown in figure 2, so that the requirement of the linear motor platform on the motion control of X-Y multi-axis can be met. The FPGA-based three-stage state machine and the filtering and frequency doubling program can complete motion control generation and signal processing of the X7043 to implement a multi-axis cooperative control strategy while analyzing PCIe local side bus signals, as shown in fig. 3 and 4. The scheme employs an RTX real-time operating system to develop a driver for PCIe bus protocol to complete an RTX real-time motion control procedure, as shown in fig. 5. And finally, based on a gantry type X-Y linear motor platform, the real-time contour tracking algorithm to be researched is tested, and the real-time contour tracking control of the given contour on the machining platform can be completed.
The above-described calculation examples of the present invention are merely to describe the calculation model and the calculation flow of the present invention in detail, and are not intended to limit the embodiments of the present invention. It will be apparent to those skilled in the art that other variations and modifications of the present invention can be made based on the above description, and it is not intended to be exhaustive or to limit the invention to the precise form disclosed, and all such modifications and variations are possible and contemplated as falling within the scope of the invention.
Claims (6)
1. The utility model provides a real-time motion control system based on PCIe bus protocol, a serial communication port, the system includes industrial computer, bottom motion control module, user interface module, PCIe integrated circuit board and PCIe keysets based on PCIe bus protocol design, wherein:
the PCIe board card is used for mapping all control interfaces of the bottom layer motion control module to an address space of an industrial personal computer, and completing the analysis of a PCIe bus protocol, the generation of motion control signals and the filtering and frequency doubling processing of photoelectric coded disc signals;
the PCIe patch board is used for summarizing and transforming data fed back by the bottom layer motion control module, and the transformed data are transmitted to the industrial personal computer through the PCIe board card;
the PCIe board card generates a control signal according to the motion control command of the industrial personal computer, and the control signal is transmitted to the bottom layer motion control module through the PCIe adapter board;
the PCIe bus adopts a chip for analyzing a bus protocol as PEX8311, the PCIe board card generates a control signal according to a motion control command of the industrial personal computer, and the adopted chip is a motion control chip X7043;
the system adopts an FPGA-XC3S500E chip to analyze signals of a PEX8311 local side bus, generate control signals of a chip X7043 and filter and frequency-doubling photoelectric coded disc signals;
the X7043 chip of the PCIe board card generates a control signal according to a motion control command of the industrial personal computer, and the specific process is as follows:
step S1, judging the state of the address effective signal ADS of the X7043, if the address effective signal ADS is in high level, keeping the initial state idle, waiting for the low level of the address effective signal ADS, and judging the level of the read-write operation signal WR when the address effective signal ADS is in low level;
if WR is high, go to step S2;
if WR is low, go to step S3;
step S2, judging whether the enable signal of the X7043 is effective;
if the enable signal is valid, then the write operation to X7043 is valid;
the write sequence includes three states in total: write _ one, Write _ two, and Write _ three; waiting for a data preparation completion signal BLAST to be effective in a Write _ one state, entering a Write _ two state when data preparation is completed, enabling chip selection of the X7043 in the Write _ two state, starting to Write data to the X7043, continuing to Write in the Write _ three state to meet the requirement of pulse width, jumping to a finish state after the Write operation is finished, initializing all output registers, and returning to an initial state idle;
if the enable signal is invalid, judging whether the write operation is valid again, if the result of the judgment again is that the write operation is valid, executing the write sequence process, otherwise, keeping an initial state idle, and waiting for operation X7043 or the write operation to be valid;
step S3, determining whether the enable signal of X7043 is valid;
if the enable signal is valid, then the read operation for X7043 is valid;
the read timing includes three states in total: waiting for address stabilization in a Read _ one state, then transferring to a Read _ ready state, performing chip selection enabling on the X7043 in the Read _ ready state, enabling a Read enable pin of the X7043 to be effective, starting reading data from the X7043 when jumping to the Read _ two state data stabilization, then jumping to a finish state, and initializing all output registers;
if the enable signal is invalid, judging whether the operation of reading the register is valid, if the judged result is that the operation of reading the register is invalid, keeping an initial state idle, and waiting for the operation X7043 or the signal of reading the register to be valid; if the judged result is that the register reading operation is effective, the state jumps to a Read _ reg state, the content in the register is copied to an output register, then the state is switched to a finish state, all output registers are initialized, and the initial state idle is jumped back;
step S4, if none of the states can respond to the external event, entering a default state, initializing all output registers and jumping back to an initial state idle;
the photoelectric encoder signal is subjected to filtering and frequency multiplication, and the specific process of the filtering comprises the following steps:
establishing an array with fixed length, assigning the value with phase updating into the array in a way that new data enters from low position and old data exits from high position, counting the high and low level states in the whole array, setting the current phase value high when the high level in the array accounts for the majority, and setting the current phase value low when the low level in the array accounts for the majority.
2. The real-time motion control system based on the PCIe bus protocol as claimed in claim 1, wherein the PCIe patch board is configured to transform data fed back by the underlying motion control module, and the transformation manner includes performing level transformation on an output signal of the optoelectronic encoder and performing optical coupling isolation on an output signal of the optoelectronic switch.
3. The real-time motion control system based on the PCIe bus protocol as claimed in claim 2, further comprising a CAN bus, wherein the CAN bus is used as a backup mode for the communication between the industrial personal computer and the underlying motion control module, and when the PCIe bus communication fails, the CAN bus is used to complete the communication and the motion control.
4. The real-time motion control system based on the PCIe bus protocol of claim 3, wherein the PCIe board is configured with MCU-XE164FN, and when PCIe bus communication fails, the control center is moved from the industrial personal computer to MCU-XE164 FN.
5. The real-time motion control system based on the PCIe bus protocol of claim 4, wherein the filtering and frequency doubling processing are performed on the optoelectronic code disc signal, and the specific process of the frequency doubling processing is as follows:
the state of the filtered signal is coded by level signals of A and B phases of the photoelectric code disc, and the state jumps to: 00- >10- >11- >01- >00, and the counter counts up at this time; the state jumps to: 00- >01- >11- >10- >00, and the counter counts down at this time; and all other state jumps are invalid jumps and no counting operation is carried out.
6. A real-time motion control method based on PCIe bus protocol is characterized by comprising the following steps:
loading rtdll by using a LoadLibrary () function; rtdll is a dynamic link library form of the RTX real-time operating system;
then obtaining addresses of functions of PCIe _ Search (), PCIe _ Init (), PCIe _ RegAddr () and PCIe _ Cleanup () from rtdll;
the PCIe _ Search () function is used for addressing and positioning a PCIe board card, the PCIe _ Init () function is used for base address mapping and equipment initialization, the PCIe _ RegAddr () function is used for register address setting, and the PCIe _ Cleanup () function is used for ending a PCIe board card process;
and searching and initializing PCIe equipment by using PCIe _ Search (), PCIe _ Init (), PCIe _ RegAddr () and PCIe _ Cleanup () functions, mapping addresses of the PCIe equipment to a virtual space of the RTX process, starting PCIe configuration, interrupt configuration and motor initialization configuration after mapping is finished, and then opening a shared memory to obtain a data command transmitted from a user display interface and executing a corresponding task.
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