CN105843755B - A kind of timing array with wide scope and high resoluting characteristic - Google Patents
A kind of timing array with wide scope and high resoluting characteristic Download PDFInfo
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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Abstract
The present invention relates to a kind of timing array implementation methods with wide scope and high resoluting characteristic for using programmable logic device.Module occurs including Read-write Catrol module, memory module, wide scope counting module, wide scope timing configured module, wide scope timing comparison module, high-resolution counting module, high-resolution timing configured module, high-resolution timing comparison module and timing signal.Using the long clock cycle wide scope counting module realize wide scope timing, in combination with use short clock-cycle high-resolution counting module realize high-resolution timing, and can reduce programmable logic device logical resource occupancy.In scientific instrument operational process, can timing configured data and timing data be set by Read-write Catrol module, meet the timing requirements of different scientific experiments.
Description
Technical field
The present invention relates to scientific instrument fields, and in particular to a kind of timing array with wide scope and high resoluting characteristic.
Background technology
In scientific instrument, it is often necessary to scientific experiment is completed according to scheduled time sequencing, to need a large amount of timings
Device exports timing signal in timing point, for triggering actuator work or trigger sensor gathered data.Scientific experiment
Timing feature is that timing range is wide, the timing point mostly high feature with local timing point timing resolution.Timing sequence
Including several time points t0, t1, t2 ..., tn needs to export timing pip at every point of time,.In the time series
Some time points need to export high-resolution timing signal.In order to meet the requirement of local timing's time point high resolution, just
Reduce the clock cycle of timer conter, while in order to meet the wide requirement of timing range, it is necessary to increase the length of timer
Degree, can increase the occupancy of logical resource in this way.
Invention content
The problem of present invention aim to address scientific instrument while wide scope and high-resolution timings, the method for the invention
It is combined using wide scope timing and high-resolution timing, reduces the occupancy of programmable logic device logical resource.
The specific technical solution of the present invention is as follows：
A kind of timing array with wide scope and high resoluting characteristic, feature are, including Read-write Catrol module, storage
Module, wide scope counting module, wide scope timing configured module, wide scope timing comparison module, high-resolution counting module, high score
Distinguish that module occurs for timing configured module, high-resolution timing comparison module and timing signal；
The Read-write Catrol module be equipped with receiver port, and the Read-write Catrol module respectively with the storage mould
Block, wide scope counting module, wide scope timing configured module, high-resolution counting module are connected with high-resolution timing configured module；
The wide scope counting module, wide scope timing configured module are connect with the wide scope timing comparison module respectively；Institute
The high-resolution counting module stated, high-resolution timing configured module are connect with the high-resolution timing comparison module respectively, institute
Wide scope timing comparison module, the high-resolution timing comparison module stated occur module with the timing signal and connect；
The Read-write Catrol module by receiver port receive outside timing configured data and timing data, and
It is written in the memory module, the memory module is for storing timing configured data and timing data, the reading
It writes control module and reads data in the memory module, and classify and be transferred to wide scope counting module, wide scope timing configured
Module, high-resolution counting module and high-resolution timing configured module, the wide scope counting module are tired for exporting wide scope
Add and count down to wide scope timing comparison module, the wide scope timing configured module is fixed to wide scope for exporting timing data
When comparison module, the wide scope timing comparison module be used for than wider range counting module and wide scope timing configured module
The wide scope accumulated counts and timing data of output, and time equal signal is transferred to timing signal, module occurs, it is described
High-resolution counting module is for exporting high-resolution accumulated counts to high-resolution timing comparison module, the high-resolution timing configured
Module is for exporting timing data to high-resolution timing comparison module, and the high-resolution timing comparison module is for comparing high score
Distinguish the high-resolution accumulated counts and timing data of counting module and the output of high-resolution timing configured module, and by time equal signal
It is transferred to timing signal and module occurs, the timing signal occurs module and exports timing pip.
The memory module includes width for storing timing configured data and timing data, the timing configured data
Range timing cycle data, wide scope timing count out, high-resolution timing cycle data；The timing data includes width
Range timing data, high-resolution timing are counted out, high-resolution timing data.
The wide scope counting module includes wide scope summing elements and wide scope timing cycle register；The reading
It writes control module and reads wide scope timing cycle data in memory module to wide scope timing cycle register.It is wide every 1
The range clock cycle, the wide scope summing elements+1, wide scope summing elements initial value is zero, and timing signal opens by
Dynamic, described wide scope clock cycle=master clock cycle × wide scope timing cycle data, wherein master clock cycle is described
The operating clock cycle with wide scope and high-resolution timing array.
The wide scope timing configured module includes wide scope timing configured register and the deposit of wide scope timing number
Device, the Read-write Catrol module read the wide scope timing data in memory module to wide scope timing configured register, read
Take wide scope timing number in memory module to wide scope timing number register.
The wide scope timing comparison module is for the relatively more described wide scope summing elements and wide scope timing configured
Register exports wide scope time equal signal if the two is equal, and module output occurs for triggering the timing signal
The wide scope timing pip at corresponding time point；When the completion of wide scope timing comparison module compares number equal to wide scope timing
When number, wide scope summing elements stop counting and resetting.
The high-resolution counting module includes high-resolution summing elements and high-resolution timing cycle register；The reading
It writes control module and reads high-resolution timing cycle data in memory module to high-resolution timing cycle register.Every 1 height
The clock cycle is differentiated, the high-resolution summing elements+1, high-resolution summing elements initial value is zero, and timing signal opens by
Dynamic, described high-resolution clock cycle=master clock cycle × high-resolution timing cycle data, wherein master clock cycle is described
The operating clock cycle with wide scope and high-resolution timing array.
The high-resolution timing configured module includes high-resolution timing configured register and the deposit of high-resolution timing number
Device, the Read-write Catrol module read the high-resolution timing data in memory module to high-resolution timing configured register, read
Take high-resolution timing number in memory module to high-resolution timing number register.
The high-resolution timing comparison module is for the relatively more described high-resolution summing elements and high-resolution timing configured
Register exports HIGH RESOLUTION TIME equal signal if the two is equal, and module output occurs for triggering the timing signal
The high-resolution timing pip at corresponding time point；When the completion of high-resolution timing comparison module compares number equal to high-resolution timing
When number, high-resolution summing elements stop counting and resetting.
The Read-write Catrol module reads the wide scope timing cycle data in memory module to wide scope timing cycle
Register reads the wide scope timing number in memory module to wide scope timing number register, reads high-resolution timing week
Issue evidence arrives wide scope timing cycle register.
The wide scope summing elements enumeration data initial value is zero, timing signal the wide scope received by outside
Start and counts；It is zero that high-resolution accumulated unit, which counts initial value,.
After timing starts, the Read-write Catrol module reads the 1st wide scope timing data in memory module to width
Range timing configured register, every 1 wide scope clock cycle, the wide scope summing elements enumeration data+1；It is described
The relatively described wide scope summing elements output of wide scope timing comparison module wide scope accumulated counts data and wide scope
The timing data of timing configured register output continues to compare if the two is unequal, if the two is equal, exports wide model
Time equal signal is enclosed, the timing pip that module the output phase answers time point occurs for triggering the timing signal.
Meanwhile the next wide model of the reading of Read-write Catrol module 1 memory module that the triggering of wide scope time equal signal is described
Timing data is enclosed to wide scope timing configured register, is repeated the above process, until the timing pip number of output is equal to
Wide scope timing number, wide scope summing elements stop counting and resetting；
Meanwhile the Read-write Catrol module described in the triggering of wide scope time equal signal reads the high-resolution in memory module and determines
When number do not start high-resolution summing elements, such as if high-resolution timing number is zero to high-resolution timing number register
Fruit high-resolution timing number is not zero, then generates high-resolution and start timing signal startup high-resolution summing elements, every 1 high score
Distinguish that clock cycle, the high-resolution summing elements enumeration data+1, the Read-write Catrol module 1 read first high-resolution
For timing data to high-resolution timing configured register, it is cumulative that the high-resolution timing comparison module 8 compares the high-resolution
High-resolution accumulated counts data and the high-resolution timing configured register of unit output export timing data, if the two not phase
Deng, then continue to compare, if the two is equal, output HIGH RESOLUTION TIME equal signal, for triggering the timing signal generation
Module the output phase answers the timing pip at time point；The module for reading and writing reads next high-resolution timing data to high score
It distinguishes timing configured register, repeats the above process, until the timing pip number of output is equal to high-resolution timing number, institute
High-resolution summing elements are stated to stop counting and resetting.
Beneficial effects of the present invention：The present invention provides a kind of timing array with wide scope and high resoluting characteristic, can be same
Shi Shixian wide scopes, high-resolution timing effectively reduce logical resource occupancy, and are realized and answered by communication interface data interaction
With configurable, timing sequence processing.Time configuration is more convenient, and easily operated, stability is good.
Description of the drawings
Fig. 1 is the structure diagram for the timing array that the present invention has wide scope and high resoluting characteristic
Specific implementation mode
With reference to experimental example and specific implementation mode, the present invention is further illustrated, but cannot should be interpreted as this
The range of the above-mentioned theme of the present invention is only limitted to following embodiment, all to belong to the present invention based on the technology that the content of present invention is realized
Range.
Referring to Fig. 1, Fig. 1 is the structure diagram for the timing array that the present invention has wide scope and high resoluting characteristic, such as scheme
Shown, a kind of timing array with wide scope and high resoluting characteristic includes Read-write Catrol module 1, memory module 2, wide scope meter
Digital-to-analogue block 3, wide scope timing configured module 4, high-resolution counting module 5, high-resolution timing configured module 6, wide scope timing ratio
Module 9 occurs compared with module 7, high-resolution timing comparison module 8 and timing signal；The Read-write Catrol module 1 is received equipped with signal
Port, and the Read-write Catrol module respectively with the memory module 2, wide scope counting module 3, wide scope timing configured module
4, high-resolution counting module 5 and high-resolution timing configured module 6 connect；The wide scope counting module 3, wide scope timing are matched
Module 4 is set to connect with the wide scope timing comparison module 7 respectively；The high-resolution counting module 5, high-resolution timing are matched
It sets module 6 to connect with the high-resolution timing comparison module 8 respectively, the wide scope timing comparison module 7, high-resolution calibration
When comparison module 8 and the timing signal module 9 occur connect；The Read-write Catrol module 1 is connect by receiver port
Timing configured data and timing data outside receiving, and be written in the memory module 2, the memory module 2 is used for
Timing configured data and timing data are stored, the Read-write Catrol module 1 reads the data in the memory module 2, and divides
Class is transferred to wide scope counting module 3, wide scope timing configured module 4, high-resolution counting module 5 and high-resolution timing configured mould
Block 6, the wide scope counting module 3 is for exporting wide scope accumulated counts to wide scope timing comparison module 7, the width
For range timing configured module 4 for exporting timing data to wide scope timing comparison module 7, mould is compared in wide scope timing
The wide scope accumulated counts and timing number that block 7 is used to export than wider range counting module 3 and wide scope timing configured module 4
According to, and time equal signal is transferred to timing signal, module 9 occurs, the high-resolution counting module 5 is for exporting high score
Accumulated counts are distinguished to high-resolution timing comparison module 8, the high-resolution timing configured module 6 is for exporting timing data to height
Timing comparison module 8 is differentiated, the high-resolution timing comparison module 8 is fixed for comparing high-resolution counting module 5 and high-resolution
When configuration module 6 the high-resolution accumulated counts and timing data that export, and time equal signal is transferred to timing signal
Module 9, the timing signal occur module 9 and export timing pip.
For memory module 2 for storing timing configured data and timing data, the timing configured data include wide scope
Timing cycle data, wide scope timing number, high-resolution timing cycle data；The timing data includes wide scope timing number
According to, high-resolution timing number and high-resolution timing data.
Wide scope counting module 3 includes wide scope summing elements 3-1 and wide scope timing cycle register 3-2；The present invention
The wide scope timing configured module 4 includes wide scope timing configured register 4-1 and wide scope timing number register 4-
2, high-resolution counting module 5 includes high-resolution summing elements 5-1 and high-resolution timing cycle register 5-2；High-resolution timing is matched
It includes high-resolution timing configured register 6-1 and high-resolution timing number register 6-2 to set module 6.
Embodiment 1
The operating clock cycle 50ns with wide scope and high-resolution timing array in the present embodiment.
If the wide scope clock cycle is 1ms, then corresponding wide scope timing cycle data are 20000, timing range
65.536s。
If high-resolution timing cycle is 100ns, then corresponding high-resolution timing cycle data are 2, temporal resolution
For 100ns.
If wide scope timing number is 3, wide scope timing data is respectively t1, t2, t3, wide scope timing point t1's
High-resolution timing number is 0；The high-resolution timing number of wide scope timing point t2 is 2, and high-resolution timing data is t2_1,
t2_2；The high-resolution timing number of wide scope timing point t3 is 1, and high-resolution timing data is t3_1.
The Read-write Catrol module 1 reads the wide scope timing cycle data in memory module 2 to wide scope timing week
Phase register 3-2 reads the wide scope timing number in memory module 2 to wide scope timing number register 4-2, reads high score
Distinguish timing cycle data to high-resolution timing cycle register 5-2.
It is zero that the wide scope summing elements 3-1, which counts initial value, timing signal the wide scope received by outside
Start and counts；It is zero that high-resolution accumulated unit 5-1, which counts initial value,.
After timing starts, the Read-write Catrol module 1 reads the 1st wide scope timing data t1 in memory module 2
To wide scope timing configured register 4-1, every 1 wide scope clock cycle 1ms, the wide scope summing elements count+
1；The wide scope accumulated counts of the relatively more described wide scope summing elements 3-1 outputs of the wide scope timing comparison module 7 with
The timing data of wide scope timing configured register 4-1 outputs continues to compare if the two is unequal, if the two is equal,
Wide scope time equal signal is exported, the wide scope that 9 the output phase of module answers time point occurs for triggering the timing signal
Timing pip trig_t1.It is 1 that the wide scope timing pip number that module 9 exports, which occurs, for timing signal, not equal to width
Range timing number is 3, and next wide scope timing data t2 that the Read-write Catrol module 1 is read in memory module 2 is arrived
Wide scope timing configured register 4-1；Meanwhile Read-write Catrol module 1 reads the 1st high-resolution timing number in memory module 2
Mesh 0 arrives high-resolution timing number register 6-2, since the 1st high-resolution timing number is 0, does not start high-resolution summing elements
5-1。
The wide scope of the relatively more described wide scope summing elements 3-1 outputs of the wide scope timing comparison module 7 is cumulative
Enumeration data and the timing data t2 of wide scope timing configured register 4-1 outputs continue to compare if the two is unequal,
If the two is equal, wide scope time equal signal is exported, timing signal generation 9 the output phase of module for triggering described is seasonable
Between the wide scope timing pip trig_t2 that puts.The wide scope timing pip number that module 9 exports occurs for timing signal
It is 2, is 3 not equal to wide scope timing number, the Read-write Catrol module 1 reads next wide scope in memory module 2
Timing data t3 to wide scope timing configured register 4-1；Meanwhile Read-write Catrol module 1 reads the 2nd in memory module 2
High-resolution timing number is 2 to high-resolution timing number register 6-2, since the 2nd high-resolution timing number is not 0, is generated
High-resolution starts timing signal and starts high-resolution summing elements 5-1, and every 1 high-resolution clock cycle, the high-resolution is tired
Element count+1, the Read-write Catrol module 1 is added to read first high-resolution timing data t2_1 to high-resolution timing configured
The high-resolution of register 6-1, the relatively more described high-resolution summing elements 5-1 outputs of the high-resolution timing comparison module 8 are tired
Counting is added to continue to compare if the two is unequal with high-resolution timing configured register 6-1 outputs timing data, if two
Person is equal, exports HIGH RESOLUTION TIME equal signal, and timing signal generation 9 the output phase of module for triggering described answers time point
High-resolution timing pip trig_t2_1.It is 1 that the high-resolution timing pip number that module 9 exports, which occurs, for timing signal,
It is 2 not equal to high-resolution timing number, the Read-write Catrol module 1 reads the 2nd wide scope timing number in memory module 2
According to t2_2 to high-resolution timing configured register 6-1；The relatively more described high-resolution of the high-resolution timing comparison module 8 is cumulative
The timing data t2 of the high-resolution accumulated counts data of unit 5-1 outputs and the 6-1 outputs of high-resolution timing configured register, if
The two is unequal, then continues to compare, and when the two is equal, output HIGH RESOLUTION TIME equal signal is believed for triggering the timing
Number 9 the output phase of module occurs answers the high-resolution timing pip trig_t2_2 at time point.Timing signal occurs module 9 and exports
High-resolution timing pip number be 2, it is 2 to be equal to high-resolution timing number, and high-resolution summing elements 5-1 stops counting simultaneously
It resets.
The wide scope of the relatively more described wide scope summing elements 3-1 outputs of the wide scope timing comparison module 7 is cumulative
Enumeration data and the timing data t3 of wide scope timing configured register 4-1 outputs continue to compare if the two is unequal,
When the two is equal, export wide scope time equal signal, for trigger the timing signal occur 9 the output phase of module it is seasonable between
The wide scope timing pip trig_t3 of point.The wide scope timing pip number that module 9 exports occurs for timing signal
3, it is 3 to be equal to wide scope timing number, and wide scope summing elements 3-1 stops counting and resetting；Meanwhile Read-write Catrol module 1 is read
It is 1 to high-resolution timing number register 6-2 to take the 3rd high-resolution timing number in memory module 2, due to the 3rd high score
It is 0 to distinguish timing number not, generates high-resolution and starts timing signal startup high-resolution summing elements 5-1, every 1 high-resolution clock
Period, the high-resolution summing elements enumeration data+1, the Read-write Catrol module 1 read first high-resolution timing number
According to t3_1 to high-resolution timing configured register 6-1, the relatively more described high-resolution of the high-resolution timing comparison module 8 is cumulative
The high-resolution accumulated counts data of unit 5-1 outputs export timing data with high-resolution timing configured register 6-1, if the two
It is unequal, then continue to compare, if the two is equal, HIGH RESOLUTION TIME equal signal is exported, for triggering the timing signal
The high-resolution timing pip trig_t3_1 that 9 the output phase of module answers time point occurs.Timing signal occurs what module 9 exported
High-resolution timing pip number is 1, and it is 1 to be equal to high-resolution timing number, and the 5-1 stoppings counting of high-resolution summing elements is simultaneously clear
Zero.
Claims (4)
1. a kind of timing array with wide scope and high resoluting characteristic, which is characterized in that including Read-write Catrol module (1), deposit
It is fixed to store up module (2), wide scope counting module (3), wide scope timing configured module (4), high-resolution counting module (5), high-resolution
When configuration module (6), wide scope timing comparison module (7), high-resolution timing comparison module (8) and timing signal module occurs
(9)；
The Read-write Catrol module (1) be equipped with receiver port, and the Read-write Catrol module (1) respectively with the storage mould
Block (2), wide scope counting module (3), wide scope timing configured module (4), high-resolution counting module (5) and high-resolution timing are matched
Set module (6) connection；The wide scope counting module (3), wide scope timing configured module (4) respectively with the wide scope
Timing comparison module (7) connects；The high-resolution counting module (5), high-resolution timing configured module (6) respectively with the height
It differentiates timing comparison module (8) to connect, the wide scope timing comparison module (7), high-resolution timing comparison module (8) and institute
It states timing signal and module (9) connection occurs；
The Read-write Catrol module (1) by receiver port receive outside timing configured data and timing data, and
It is written in the memory module (2), the memory module (2) is for storing timing configured data and timing data, institute
The Read-write Catrol module (1) stated reads the data in the memory module (2), and classify be transferred to wide scope counting module (3),
Wide scope timing configured module (4), high-resolution counting module (5) and high-resolution timing configured module (6), the wide scope meter
Digital-to-analogue block (3) is for exporting wide scope accumulated counts to wide scope timing comparison module (7), the wide scope timing configured mould
For exporting timing data to wide scope timing comparison module (7), the wide scope timing comparison module (7) is used for block (4)
Than wide scope accumulated counts and timing data that wider range counting module (3) and wide scope timing configured module (4) export, and
Time equal signal is transferred to timing signal, module (9) occurs, the high-resolution counting module (5) is for exporting high-resolution
To high-resolution timing comparison module (8), the high-resolution timing configured module (6) arrives accumulated counts for exporting timing data
High-resolution timing comparison module (8), the high-resolution timing comparison module (8) for compare high-resolution counting module (5) and
The high-resolution accumulated counts and timing data of high-resolution timing configured module (6) output, and time equal signal is transferred to and is determined
When signal generating module (9), the timing signal occur module (9) export timing pip.
2. the timing array according to claim 1 with wide scope and high resoluting characteristic, which is characterized in that described deposits
For storage module (2) for storing timing configured data and timing data, the timing configured data include wide scope timing cycle
Data, wide scope timing number and high-resolution timing cycle data；The timing data includes wide scope timing data, high score
Distinguish timing number and high-resolution timing data.
3. the timing array according to claim 2 with wide scope and high resoluting characteristic, which is characterized in that the width
Range counting module (3) includes wide scope summing elements (3-1) and wide scope timing cycle register (3-2)；The read-write
Control module (1) reads the wide scope timing cycle data in memory module (2) to wide scope timing cycle register (3-2)；
The enumeration data initial value of wide scope summing elements (3-1) is zero, and timing signal starts meter the wide scope received by outside
Number, every 1 wide scope clock cycle, the wide scope summing elements enumeration data+1；
The wide scope timing configured module (4) includes wide scope timing configured register (4-1) and wide scope timing number
Register (4-2), it is fixed to wide scope that the Read-write Catrol module (1) reads the wide scope timing data in memory module (2)
When configuration register (4-1), read wide scope timing number in memory module (2) to wide scope timing number register (4-
2)；
The high-resolution counting module (5) includes high-resolution summing elements (5-1) and high-resolution timing cycle register (5-
2), the high-resolution timing configured module (6) includes that high-resolution timing configured register (6-1) and high-resolution timing number are posted
Storage (6-2)；
Wide scope of the wide scope timing comparison module (7) for relatively more described wide scope summing elements (3-1) output
Accumulated counts data and the timing data of wide scope timing configured register (4-1) output continue to compare if the two is unequal
Compared with, if the two is equal, output wide scope time equal signal, the wide scope time equal signal triggering timing signal
The timing pip that module (9) the output phase answers time point occurs；
It is next that the wide scope time equal signal triggers Read-write Catrol module (1) the reading memory module (2) simultaneously
A wide scope timing data is repeated the above process to wide scope timing configured register (4-1), until the clocked flip of output is believed
Number mesh is equal to wide scope timing number, and wide scope summing elements (3-1) stop counting and resetting；
The wide scope time equal signal triggers the Read-write Catrol module (1) and reads in memory module (2) simultaneously
High-resolution timing number does not start high score to high-resolution timing number register (6-2) if high-resolution timing number is zero
It distinguishes summing elements (5-1), if high-resolution timing number is not zero, generates high-resolution and start timing signal to start high-resolution tired
Adding unit (5-1), the enumeration data initial value of high-resolution summing elements (5-1) is zero, every 1 high-resolution clock cycle, institute
The high-resolution summing elements enumeration data+1 stated, the Read-write Catrol module (1) read first high-resolution timing data and arrive
High-resolution timing configured register (6-1), the relatively more described high-resolution summing elements of the high-resolution timing comparison module (8)
The timing data of the high-resolution accumulated counts data of (5-1) output and high-resolution timing configured register (6-1) output, if two
Person is unequal, then continues to compare, if the two is equal, exports HIGH RESOLUTION TIME equal signal, for triggering the timing letter
Number module (9) the output phase occurs answers the timing pip at time point；It is fixed that the module for reading and writing (1) reads next high-resolution
When data to high-resolution timing configured register (6-1), repeat the above process, until the timing pip number of output is equal to
High-resolution timing number, the high-resolution summing elements (5-1) stop counting and resetting.
4. the timing array according to claim 3 with wide scope and high resoluting characteristic, which is characterized in that the width
The range clock cycle=master clock cycle × wide scope timing cycle data, wherein master clock cycle is described with wide model
Enclose the operating clock cycle with high-resolution timing array；The high-resolution clock cycle=master clock cycle × high-resolution is fixed
When cycle data, wherein master clock cycle be the operating clock cycle with wide scope and high-resolution timing array.
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Effective date of registration: 20231226 Address after: Room 907, Building 23, No. 68 Jiangnan Road, Chunjiang Street, Fuyang District, Hangzhou City, Zhejiang Province, 311421 Patentee after: Kaiser Technology (Hangzhou) Co.,Ltd. Address before: 201800 mail box 800-211, Shanghai, Jiading District, Shanghai Patentee before: SHANGHAI INSTITUTE OF OPTICS AND FINE MECHANICS CHINESE ACADEMY OF SCIENCES |