CN106647910B - 一种用于超低功耗基准源的启动电路 - Google Patents

一种用于超低功耗基准源的启动电路 Download PDF

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CN106647910B
CN106647910B CN201611203919.6A CN201611203919A CN106647910B CN 106647910 B CN106647910 B CN 106647910B CN 201611203919 A CN201611203919 A CN 201611203919A CN 106647910 B CN106647910 B CN 106647910B
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circuit
tube
nmos tube
pmos tube
grid
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CN106647910A (zh
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王志鹏
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Changsha In Blx Ic Design Corp
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Changsha In Blx Ic Design Corp
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    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10Regulating voltage or current
    • G05F1/46Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

本发明公开了一种用于超低功耗基准源的启动电路,相对于传统的基准源模块中的启动电路,本发明通过合理使用了一个负阈值NMOS管,巧妙解决了启动电路工作瞬间会产生一个较大的瞬态电流的弊端,使得该启动电路可以广泛的应用在一些对功耗要求极其严格的基准源模块中。

Description

一种用于超低功耗基准源的启动电路
技术领域
本发明用于集成电路设计领域,具体涉及一种用于超低功耗基准源的启动电路。
背景技术
近年来,随着各种便携式电子产品广泛发展和应用,如手机、数码相机、移动音/视频设备等,如何降低功耗、延长电池的使用时间已成为产品设计首要考虑的问题之一。尤其对于USB接口芯片,在其未进行通信时,芯片处于睡眠状态,在这种状态下,全芯片的功耗只有几uA且需要严格控制瞬态大电流。基准电压源作为USB接口芯片唤醒功能重要的模块之一,对功耗的要求是极其严格的,既要保证超低的功耗,也不能产生大的瞬态电流,因此,传统的启动电路结构很难满足要求,因为启动电路在开启的一瞬间是极易产生一个较大的电流来使基准电压源摆脱“锁死”的状态,其非常典型的一个启动电路如图1所示,当偏置电流产生电路被“锁死”,即NMOS管N3的栅极为低电平,PMOS管P3的栅极为高电平,PMOS管P1处于关断状态,同时,NMOS管N1也处于关断状态,那么,PMOS管P2的栅极为低,P2将被完全开启,NMOS管N3的栅极会接收到一个高电平,NMOS管N3和N4都将被完全开启,虽然偏置电流产生电路会摆脱被“锁死”的状态,这也必然会在各自的对地通路上产生一个较大的瞬态电流,增加功耗。虽然这个瞬态电流在一些电源模块中并不十分关心,但在一些有着超低功耗要求的芯片中却十分重要。
发明内容
本发明要解决的问题在于:针对常规的基准源中启动电路易产生较大的瞬态功耗的弊端,提出了一种用于超低功耗基准源的启动电路,本发明的主要特征在于:
所述的电路包括PMOS管P1,PMOS管P2,NMOS管N1和一个负阈值NMOS管N2,PMOS管P1的源极接电源VDD,PMOS管P1的漏极接NMOS管N1的漏极和PMOS管P2的栅极,PMOS管P1的栅极接外部电路的输出端,NMOS管N1的栅极与NMOS管N1的源极相接并接到地VSS,PMOS管P2的源极接电源VDD,PMOS管P2的漏极接负阈值NMOS管N2的漏极,负阈值NMOS管N2的栅极与源极相接并与连接到外部电路的输入端,典型情况下,该外部电路通常为偏置电流产生电路。
本发明的主要特点在于:
1、结构简单:本发明仅在传统启动电路中,巧妙的增加了一个负阈值的NMOS管即实现了避免较大瞬态电流的产生;
2、性能优良:通过合理设置负阈值NMOS管的尺寸,可使基准电压源在非常低的功耗下摆脱“锁死”的状态;
3、应用广泛:本电路可广泛的应用于各种基准电压源或基准电流源的模块中。
附图说明
图1 传统的启动电路结构框图;
图2 本发明提出的一种用于超低功耗基准源的启动电路结构图。
具体实施方式
以下结合附图对本发明做进一步详细描述。
本发明提出的一种用于超低功耗基准源的启动电路,其结构如图2所示,包括PMOS管P1,PMOS管P2,NMOS管N1和一个负阈值NMOS管N2,PMOS管P1的源极接电源VDD,PMOS管P1的漏极接NMOS管N1的漏极和PMOS管P2的栅极,PMOS管P1的栅极接外部电路的输出端,NMOS管N1的栅极与NMOS管N1的源极相接并接到地VSS,PMOS管P2的源极接电源VDD,PMOS管P2的漏极接负阈值NMOS管N2的漏极,负阈值NMOS管N2的栅极与源极相接并与连接到外部电路的输入端,典型情况下,该外部电路通常为偏置电流产生电路,一个非常典型的偏置电流产生电路如图2的右半部分所示。当偏置电流产生电路被“锁死”,即NMOS管N3的栅极,NMOS管N4的栅极和漏极均为低电平,PMOS管P4的栅极,PMOS管P3的栅极和漏极均为高电平,PMOS管P1处于关断状态,同时,NMOS管N1也处于关断状态,那么,PMOS管P2的栅极为低电平,P2将被完全开启,PMOS管P2的漏极会被拉高,此时,负阈值NMOS管N2也是开启的,如果是常规NMOS管,栅极与源极相接是关断的,但N2是一个负阈值管,虽然VGS=0,但VTH是一个负值,所以,VGS-VTH>0。值得注意的是启动电路开启后,PMOS管P2的漏极会被瞬间拉高,但P2漏极电压的瞬态变化由于负阈值NMOS管N2的阻隔并不会使偏置电流产生电路的NMOS管N3的栅极电压瞬间拉高,因为负阈值NMOS管N2的栅极和漏极电压并不受其漏极电压控制,NMOS管N3的栅极电压会随着启动电路PMOS管P2和负阈值NMOS管N2的导通慢慢提高直至其合适的直流偏置点,摆脱被“锁死”的状态,并不会产生一个很高的瞬态电压,因此,也避免了启动电路开启瞬间产生大的瞬态电流。如果没有负阈值NMOS管N2的阻隔作用,如图1所示,那么,启动电路开启的瞬间,PMOS管P2完全导通,NMOS管N3的栅极会接收到一个高电平,NMOS管N3和N4都将被完全开启,虽然偏置电流产生电路会摆脱被“锁死”的状态,这也必然会在各自的对地通路上产生一个较大的瞬态电流,增加功耗。
当偏置电流产生电路摆脱被“锁死”的状态后,偏置电流产生电路将工作在一个合适的直流偏置点,那么启动电路的PMOS管P1将开启,由于NMOS管N1是关断的,所以PMOS管P1的漏极将被拉高,进而PMOS管P2将被关断,启动电路退出工作。

Claims (1)

1.一种用于超低功耗基准源的启动电路,其特征在于:包括PMOS管P1,PMOS管P2,NMOS管N1和一个负阈值NMOS管N2,PMOS管P1的源极接电源VDD,PMOS管P1的漏极接NMOS管N1的漏极和PMOS管P2的栅极,PMOS管P1的栅极接外部电路的输出端,NMOS管N1的栅极与NMOS管N1的源极相接并接到地VSS,PMOS管P2的源极接电源VDD,PMOS管P2的漏极接负阈值NMOS管N2的漏极,负阈值NMOS管N2的栅极与源极相接并连接到外部电路的输入端,该外部电路为偏置电流产生电路。
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TW200903213A (en) * 2007-07-02 2009-01-16 Beyond Innovation Tech Co Ltd Bias supply, start-up circuit, and start-up method for bias circuit
KR20140019497A (ko) * 2012-08-06 2014-02-17 (주)샌버드 스타트업 회로
CN103729004A (zh) * 2014-01-07 2014-04-16 上海华虹宏力半导体制造有限公司 一种偏置电流产生电路
CN104049671A (zh) * 2014-07-03 2014-09-17 中国科学院微电子研究所 一种面向三维存储器的零温度系数参考电压产生电路
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Publication number Priority date Publication date Assignee Title
TW200903213A (en) * 2007-07-02 2009-01-16 Beyond Innovation Tech Co Ltd Bias supply, start-up circuit, and start-up method for bias circuit
KR20140019497A (ko) * 2012-08-06 2014-02-17 (주)샌버드 스타트업 회로
CN103729004A (zh) * 2014-01-07 2014-04-16 上海华虹宏力半导体制造有限公司 一种偏置电流产生电路
CN104049671A (zh) * 2014-07-03 2014-09-17 中国科学院微电子研究所 一种面向三维存储器的零温度系数参考电压产生电路
CN104714594A (zh) * 2015-03-27 2015-06-17 西安华芯半导体有限公司 一种带隙基准的启动电路

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