CN106625203A - Chemical mechanical grinding method - Google Patents
Chemical mechanical grinding method Download PDFInfo
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- CN106625203A CN106625203A CN201610996811.0A CN201610996811A CN106625203A CN 106625203 A CN106625203 A CN 106625203A CN 201610996811 A CN201610996811 A CN 201610996811A CN 106625203 A CN106625203 A CN 106625203A
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- Prior art keywords
- cmp
- wafer
- dielectric layer
- layer
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Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
- B24B37/042—Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02065—Cleaning during device manufacture during, before or after processing of insulating layers the processing being a planarization of insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
Abstract
The invention provides a chemical mechanical grinding method. The chemical mechanical grinding method comprises the steps that a to-be-ground wafer is provided, and the wafer comprises a semiconductor substrate, an interlevel dielectric layer formed on the semiconductor substrate, grooves formed in the interlevel dielectric layer and metal interconnecting layers formed on the interlevel dielectric layer and in the grooves; the metal interconnecting layers are subjected to first chemical mechanical grinding, and part of the metal interconnecting layers are removed; the metal interconnecting layers are subjected to second chemical mechanical grinding, and the metal connecting layer on the interlevel dielectric layer is completely removed; the interlevel dielectric layer is subjected to third chemical mechanical grinding; third chemical mechanical grinding comprises a washing step; a corrosion inhibitor is adopted for washing the wafer, metal exposed within the wait time is prevented from being oxidized, and therefore the risk of dendrite defects is reduced, and the performance of a semiconductor device is improved; and meanwhile the wait time of the wafer in the third chemical mechanical grinding process is reduced.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of method of cmp.
Background technology
With the development of semiconductor technology, the diminution of device size, to the flat of semiconductor devices metal interconnecting layer surface
Change degree requires more and more higher.Cmp (CMP) is a kind of planarization that can meet multilayer wiring requirement, chemistry
Mechanical lapping is the combination of chemistry and mechanical effect, in material surface to be ground, because there is chemical reaction spy is generated
Given layer, then mechanically removes this certain layer.
Existing chemical mechanical polishing device generally comprises three cmp sub-devices, such as sub-device 1, sub- dress
2 are put with sub-device 3, three sub-devices carry out mechanical lapping to different wafers, and each wafer is required for Jing simultaneously
Crossing three sub-devices carries out three cmps.For example, it is formed with the semiconductor lining of interlayer dielectric layer and copper interconnection layer
Bottom, the sub-device 1 carries out first time cmp, removes most copper interconnection layer, and this process grinding rate compares
Hurry up, be a kind of rough lapping mode, then carry out second cmp using sub-device 2, remove the interlayer dielectric layer
Copper on surface, then carries out third time cmp using 3 pairs of interlayer dielectric layers of sub-device.
The sub-device 1 is completed after a grinding wafer, and the wafer is moved to the sub-device 2 and is ground, while
Sub-device 1 carries out the grinding of next wafer, and afterwards sub-device 3 carries out the grinding of the wafer, and sub-device 2 carries out next wafer
Grinding, sub-device 1 carries out the grinding of next one wafer, and three sub-devices are ground to different wafers simultaneously, but
The milling time total more than sub-device 3 with total milling time of sub-device 2 of sub-device 1, therefore, in sub-device 3, grind in master
One section of stand-by period is needed before mill, and due to the grinding of sub-device 2, the copper metal exposed in wait is easily by oxygen
Change, the semiconductor for ultimately forming can be caused to form dendron defect (Dendrites Defect).
Therefore, the stand-by period of third time cmp how is reduced, the generation for reducing dendron defect is this area
The technical problem of technical staff's urgent need to resolve.
The content of the invention
It is an object of the invention to provide a kind of method of cmp, reduces brilliant in third time cmp
The round stand-by period, reduce the generation of dendron defect.
A kind of method of cmp is the technical scheme is that, is comprised the following steps：
Wafer to be ground is provided, the wafer includes that Semiconductor substrate, formation interlayer on the semiconductor substrate are situated between
Matter layer, the groove being formed in the interlayer dielectric layer and the gold being formed on the interlayer dielectric layer and in the groove
Category interconnection layer；
The first cmp is carried out to the metal interconnection layer, the part metal interconnection layer is removed；
The second cmp is carried out to the metal interconnection layer, the gold on the interlayer dielectric layer is removed completely
Category interconnection layer；
3rd cmp is carried out to the interlayer dielectric layer；
3rd cmp includes a rinsing step：The wafer is rinsed using corrosion inhibiter.
Further, the 3rd cmp includes pre-grinding, main grinding and wafer cleaning.
Further, the rinsing step was carried out before the main grinding.
Further, the rinsing step is carried out with the pre-grinding, main grinding on same grinding pad.
Further, the metal interconnecting layer is copper interconnection layer, and the corrosion inhibiter is copper inhibitor.
Further, the corrosion inhibiter is BTA.
Further, the time that the rinsing step is rinsed is 30s～70s.
Further, described first the total of mechanical lapping, the second cmp and the 3rd cmp is learned
Time is suitable.
Further, first cmp, the second cmp and the 3rd cmp are adopted
Carried out with the different sub-devices of same chemical mechanical polishing device.
Further, first cmp, the second cmp and the 3rd cmp be simultaneously
Carry out, different wafers are ground respectively.
Compared with prior art, the method for the cmp that the present invention is provided, third time is carried out to interlayer dielectric layer
Cmp, the grinding includes a rinsing step, and metal interconnecting layer is rinsed using corrosion inhibiter, prevents when waiting
The interior metal for exposing is oxidized, and so as to reduce the risk that dendron defect occurs, improves the performance of semiconductor devices；Together
When reduce stand-by period of the wafer in third time chemical mechanical planarization process.
Description of the drawings
The schematic flow sheet of the method for the cmp that Fig. 1 is provided by one embodiment of the invention.
Each step structural representation of the method for the cmp that Fig. 2～Fig. 5 is provided by one embodiment of the invention.
Specific embodiment
To make present disclosure more clear understandable, below in conjunction with Figure of description, present disclosure is done into one
Step explanation.Certainly the specific embodiment is the invention is not limited in, general replacement well known to the skilled artisan in the art is also contained
Lid is within the scope of the present invention.
Secondly, the present invention has carried out detailed statement using schematic diagram, when present example is described in detail, for the ease of saying
Bright, schematic diagram, should not be to this as restriction of the invention not according to general ratio partial enlargement.
The present invention core concept be：Third time cmp is carried out to interlayer dielectric layer, the grinding includes a punching
Step is washed, metal interconnecting layer is rinsed using corrosion inhibiter, prevent the metal exposed within the stand-by period to be oxidized, so as to
The risk that dendron defect occurs is reduced, the performance of semiconductor devices is improve；Wafer is reduced simultaneously in the chemical machine of third time
Stand-by period in tool process of lapping.
The schematic flow sheet of the method for the cmp that Fig. 1 is provided by one embodiment of the invention, as shown in figure 1,
The present invention proposes a kind of method of cmp, comprises the following steps：
Step S01：Wafer to be ground is provided, the wafer includes Semiconductor substrate, formed on the semiconductor substrate
Interlayer dielectric layer, the groove that is formed in the interlayer dielectric layer and be formed on the interlayer dielectric layer and described recessed
Metal interconnecting layer in groove；
Step S02：The first cmp is carried out to the metal interconnection layer, the part metal interconnection layer is removed；
Step S03：The second cmp is carried out to the metal interconnection layer, the institute on the interlayer dielectric layer is removed
State metal interconnecting layer；
Step S04：3rd cmp is carried out to the interlayer dielectric layer；3rd cmp includes
One rinsing step：The metal interconnection layer is rinsed using corrosion inhibiter..
Each step structural representation of the method for the cmp that Fig. 2～4 provide for one embodiment of the invention, please join
Examine shown in Fig. 1, and with reference to Fig. 2～Fig. 4, the method for describing cmp proposed by the present invention in detail：
In step S01, there is provided wafer to be ground 10, the wafer 10 includes Semiconductor substrate 11, is formed in described half
Interlayer dielectric layer 12 on conductor substrate 11, the groove 13 being formed in the interlayer dielectric layer 12 and it is formed in the layer
Between metal interconnecting layer 14 on dielectric layer 12 and in the groove 13, as shown in Figure 2.
In the present embodiment the Semiconductor substrate 11 may include any semi-conducting material, the semi-conducting material may include but
It is not limited to：Si, SiC, SiGe, SiGeC, Ge alloy, GeAs, InAs, InP, and other III-V or II-VI group compound half
Conductor.The Semiconductor substrate 11 includes various isolation structures, such as fleet plough groove isolation structure.The Semiconductor substrate 11 may be used also
Partly led with the layering including organic semiconductor or such as SiGe (SGOI) on Si/SiGe, silicon-on-insulator (SOI) or insulator
Body.Various semiconductor devices can also be formed in the Semiconductor substrate 11.
The interlayer dielectric layer 12, can be low k dielectric (interlayer dielectric layer of formation is low k dielectric), may be used also
Think ultra low k dielectric materials (interlayer dielectric layer of formation is ultra-low-k dielectric layer).Generally adopt chemical gaseous phase spin coating proceeding
(SOG), prepared by whirl coating technology or chemical vapour deposition technique.
The metal interconnecting layer 14 is preferably copper interconnection layer, can be formed using dual damascene process.First, to interlayer
Dielectric layer 12 is performed etching, and produces the groove 13 for mosaic technology, is then followed by deposited metal barrier layer and copper seed layer (figure
Not shown in), then copper interconnection layer 14 is formed in interlayer dielectric layer 12 and groove 13, can be ripe using those skilled in the art institute
The various suitable technology known, such as physical gas-phase deposition or electroplating technology.Each step due to forming wafer 10
Suddenly prior art is, therefore not to repeat here.
In step S02, the first cmp is carried out to the metal interconnection layer 14, remove the part metal mutual
Connection layer 14, as shown in Figure 3.In the present embodiment, most metal interconnecting layer 14 is removed, this process grinding rate ratio is very fast,
It is a kind of rough lapping mode.
In step S03, the second cmp is carried out to the metal interconnection layer 14, the interlayer is removed completely and is situated between
The metal interconnecting layer 14 on matter layer 12, as shown in Figure 4.
In order to avoid during the thinner thickness of remaining metal interconnection layer 14, continuing to adopt first on the interlayer dielectric layer 11
This rough lapping of cmp can cause scratch to crystal column surface, therefore need to carry out the second mechanical lapping.Described second changes
Mechanical lapping is fine lapping.Second cmp removes completely the remaining gold on the interlayer dielectric layer 11
Category interconnection layer 14, and expose the metal interconnection layer 14 in groove.The grinding rate of second cmp is less than institute
State the grinding rate of the first cmp.
In step S04, the 3rd cmp is carried out to the interlayer dielectric layer, as shown in Figure 5.Described 3rd changes
Learning mechanical lapping includes a rinsing step：The wafer 10 is rinsed using corrosion inhibiter.
3rd cmp mainly includes pre-grinding, main grinding and wafer cleaning, is carrying out main grinding
Before carry out rinsing step.Preferably, the corrosion inhibiter is BTA (BTA), for protecting the copper interconnection layer 14 for exposing,
Prevent wafer 10 from aoxidizing within the stand-by period, to prevent the generation of dendron defect.
First cmp, the second cmp and the 3rd cmp adopt same chemistry
The sub-device of mechanical lapping equipment is carried out, such as described cmp includes sub-device one, sub-device two and sub-device three,
The sub-device one, sub-device two and sub-device three carry out respectively the first cmp, the second cmp and
3rd cmp.First cmp, the second cmp and the 3rd cmp are simultaneously
Carry out, different wafers are ground respectively, i.e., described sub-device one, sub-device two are carried out from sub-device San Tong method to different wafers
Grinding.For example：A pair wafers to be ground of sub-device carry out after the first cmp, moving to sub-device two, while
Wafer two moves to sub-device one；Sub-device two carries out the second cmp to wafer one, while a pair of wafers of sub-device
Two carry out the first cmp；Then wafer one moves to sub-device three, and wafer two moves to sub-device two, while wafer
Three move to sub-device one, and sub-device three carries out the 3rd cmp to wafer one, and sub-device two carries out to wafer two
Two cmps, a pair of wafers of sub-device three carry out the first cmp, wafer one complete cmp it
Afterwards, having follow-up wafer constantly carries out cmp.
First cmp and the second chemical-mechanical grinding liquid also mainly include pre-grinding, main grinding and crystalline substance
The steps such as circle cleaning.Because the first cmp grinds with the total time of the second cmp more than the 3rd chemical machinery
The total time of mill, but the main grinding of three cmps is carried out simultaneously, therefore, in the 3rd cmp
Step is rinsed before main grinding, it is possible to reduce the stand-by period of wafer in the 3rd cmp, prevent what is exposed
Copper is oxidized, and then prevents the generation of dendron defect.And due to the flushing carried out using buffer, while reduce other lacking
Fall into the risk for producing.
In the 3rd cmp, the rinsing step is enterprising in same grinding pad with the pre-grinding, main grinding
OK, i.e., after pre-grinding is carried out, step is directly rinsed, then directly carries out main grinding, wafer is not moved.
The time that the rinsing step is rinsed is 30s～70s, such as 30s, 50s or 70s so that the first time
Learn the total time of mechanical lapping, the second cmp and the 3rd cmp quite, or three chemical machineries
Grinding total time is identical.It is understood that the time that the rinsing step is rinsed is not limited in 30s～70s, can
With according to the difference of the 3rd cmp and the total time of the first cmp and the second cmp come
It is determined that.
In sum, the method for the cmp that the present invention is provided, the side of the cmp that the present invention is provided
Method, to interlayer dielectric layer third time cmp is carried out, and the grinding includes a rinsing step, mutual to metal using corrosion inhibiter
Even layer is rinsed, and prevents the metal exposed within the stand-by period to be oxidized, so as to reduce the risk that dendron defect occurs,
Improve the performance of semiconductor devices；Reduce stand-by period of the wafer in third time chemical mechanical planarization process simultaneously.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this
Any change, modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Scope.
Claims (10)
1. a kind of method of cmp, it is characterised in that comprise the following steps：
Wafer to be ground is provided, the wafer include Semiconductor substrate, formed interlayer dielectric layer on the semiconductor substrate,
The groove being formed in the interlayer dielectric layer and the metal interconnection being formed on the interlayer dielectric layer and in the groove
Layer；
The first cmp is carried out to the metal interconnection layer, the part metal interconnection layer is removed；
The second cmp is carried out to the metal interconnection layer, the metal removed completely on the interlayer dielectric layer is mutual
Connect layer；
3rd cmp is carried out to the interlayer dielectric layer；
3rd cmp includes a rinsing step：The wafer is rinsed using corrosion inhibiter.
2. the method for cmp as claimed in claim 1, it is characterised in that the 3rd cmp includes
Pre-grinding, main grinding and wafer cleaning.
3. the method for cmp as claimed in claim 2, it is characterised in that carried out before the main grinding described
Rinsing step.
4. the method for cmp as claimed in claim 3, it is characterised in that the rinsing step and the beforehand research
Mill, main grinding are carried out on same grinding pad.
5. the method for cmp as claimed in claim 1, it is characterised in that the metal interconnecting layer is copper interconnection
Layer, the corrosion inhibiter is copper inhibitor.
6. the method for cmp as claimed in claim 5, it is characterised in that the corrosion inhibiter is BTA.
7. the method for cmp as claimed in claim 1, it is characterised in that the rinsing step be rinsed when
Between be 30s～70s.
8. the method for cmp as claimed in claim 1, it is characterised in that described first learn mechanical lapping, second
The total time of cmp and the 3rd cmp is suitable.
9. the method for cmp as claimed in claim 8, it is characterised in that first cmp,
Two cmps and the 3rd cmp are carried out using the different sub-devices of same chemical mechanical polishing device.
10. the method for cmp as claimed in claim 9, it is characterised in that first cmp,
Two cmps are carried out simultaneously with the 3rd cmp, and different wafers are ground respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610996811.0A CN106625203A (en) | 2016-11-11 | 2016-11-11 | Chemical mechanical grinding method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610996811.0A CN106625203A (en) | 2016-11-11 | 2016-11-11 | Chemical mechanical grinding method |
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| CN106625203A true CN106625203A (en) | 2017-05-10 |
Family
ID=58806201
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| CN201610996811.0A Pending CN106625203A (en) | 2016-11-11 | 2016-11-11 | Chemical mechanical grinding method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110328561A (en) * | 2018-03-30 | 2019-10-15 | 长鑫存储技术有限公司 | The preparation method of chemical and mechanical grinding method, system and metal plug |
| CN113649945A (en) * | 2021-10-20 | 2021-11-16 | 杭州众硅电子科技有限公司 | Wafer polishing device |
| CN114121647A (en) * | 2022-01-24 | 2022-03-01 | 澳芯集成电路技术(广东)有限公司 | Method for improving chemical mechanical polishing efficiency |
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| CN1458672A (en) * | 2002-05-13 | 2003-11-26 | 台湾积体电路制造股份有限公司 | Method for reducing defect of chemical and mechanical grinding to produce coppor and grinding slurry residual |
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| CN110328561A (en) * | 2018-03-30 | 2019-10-15 | 长鑫存储技术有限公司 | The preparation method of chemical and mechanical grinding method, system and metal plug |
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| CN114121647B (en) * | 2022-01-24 | 2022-04-22 | 澳芯集成电路技术(广东)有限公司 | Method for improving chemical mechanical polishing efficiency |
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Application publication date: 20170510 |