CN106033708B - A kind of wafer thining method - Google Patents
A kind of wafer thining method Download PDFInfo
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- CN106033708B CN106033708B CN201510107555.0A CN201510107555A CN106033708B CN 106033708 B CN106033708 B CN 106033708B CN 201510107555 A CN201510107555 A CN 201510107555A CN 106033708 B CN106033708 B CN 106033708B
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Abstract
The present invention provides a kind of wafer thining method, includes the following steps: to provide semiconductor crystal wafer, forms passivation layer in the semiconductor crystal wafer front, and etch the passivation layer to form groove；Form the filled layer for covering the crystal round fringes and the groove and passivation layer；Remove the filled layer except crystal round fringes and trench region；Adhesive tape is formed on the passivation layer；Brilliant back-grinding is carried out to the wafer；Remove the adhesive tape；Remove the filled layer.Wafer thining method provided by the invention forms filled layer at the gaps such as Cutting Road and at crystal round fringes, in this way when carrying out brilliant back-grinding, due to being filled at the gaps such as Cutting Road and at crystal round fringes by filled layer, the Si powder generated in process of lapping whether all cannot be introduced into chip from wafer side or bottom surface, therefore can be fully solved the problem of Si powder during brilliant back-grinding at present enters chip.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of wafer thining method.
Background technique
In semiconductor technology rear end, due to different process demand, it is sometimes necessary to carry out wafer thinned, that is, to progress
The extra basis material of backside of wafer is removed certain thickness by brilliant back-grinding (backside grinding) subtracts backside of wafer
It is such as common to have 19 persons of outstanding talent cun (mil), 12 persons of outstanding talent cun etc. to certain thickness.Such as usually before integrated antenna package, 2 layers or 2 layers
The above chip is stacked carry out system encapsulation, and in order to adapt to light and smallization of ic chip package development trend, people
Wish that the thickness of wafer can be accomplished very thin (i.e. manufacture ultra-thin wafers), therefore wafer is subtracted before wafer cutting
It is thin, for example wafer is thinned to 150um even 150um or less.
As shown in Figure 1A, the thinned substantially process of wafer current is that first in 100 front of wafer, (front of wafer 100 refers to
The surface of element, lamination, interconnection line and weld pad etc. is formed on a semiconductor substrate) form passivation film (passivation
Film) 101, then etch passivation film layer 101 exposes Cutting Road (scriber line) 102 etc., then carries out cleaning removal erosion
Reagent and other residual substances are carved, the acceptable test (WAT) of chip is carried out then to test the electric property etc. of chip, works as test
Then 103 band of glue is recycled to be placed on wafer on the board of grinder then in 101 adhesive tape 103 of passivation film after qualification
Carry out brilliant back-grinding.In addition, for the adhesion strength of reinfored glue band 103 and passivation film 101, it can be in adhesive tape 103 and passivation film
101 adhesion strength increases binder 104.
But during brilliant back-grinding, other than the risks such as common broken wafers, there are also the Si powder (Si- after grinding
Dust the problems in chip can) be brought into；And once Si powder enters place deep in chip, subsequent cleaning is difficult completely
It disposes, as shown in Figure 1B, Si powder is full of in the Cutting Road in the B of region, not only visual inspection cannot reach a standard, appearance is influenced, and
Serious conditions also will affect subsequent cutting process.
Si powder enters the problems in chip and occurs mainly on the product with thick metal layer at top at present, this is because
When metal layer at top thickness is bigger, such as 20K, 33K, 40K, corresponding passivation film 101 also can be very thick, passivation film 101
The backward step (step high) (such as Cutting Road 102) of etching is bigger, and Si powder is more difficult to wash after entering.So not only after
Continuous cleaning influences production capacity, and some clients refuse to receive this kind of chip.Enter chip to reduce Si powder, way before
It is to change adhesive tape 103, more has the glue of adhesion strength by changing and cover gap (such as Cutting Road 102) as far as possible, but cannot solve
Certainly Si powder enters the problems in chip from wafer side, and as shown in Figure 1A, when 101 thickness of passivation film is larger,
Gap (such as Cutting Road 102) depth-to-width ratio is very big, and adhesive tape 103 can only cover gap upper area, and gap bottom section is still
Si powder can be entered.In addition, exactly subsequent be cleaned multiple times wafer or chip, but person can not remove chip completely
In Si powder.
Therefore, it is necessary to propose a kind of new production method, it is above-mentioned to solve the problems, such as.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
In order to overcome the problems, such as that presently, there are one aspect of the present invention provides a kind of wafer thining method comprising Xia Shubu
It is rapid: semiconductor crystal wafer being provided, forms passivation layer in the semiconductor crystal wafer front, and etch the passivation layer to form groove；
Form the filled layer for covering the crystal round fringes and the groove and passivation layer；It removes except crystal round fringes and trench region
Filled layer；Adhesive tape is formed on the passivation layer；Brilliant back-grinding is carried out to the wafer；Remove the adhesive tape；It is filled out described in removal
Fill layer.
Wafer thining method provided by the invention forms filled layer at the gaps such as Cutting Road and at crystal round fringes, in this way
When carrying out brilliant back-grinding, due to being filled at the gaps such as Cutting Road and at crystal round fringes by filled layer, produced in process of lapping
Raw Si powder whether all cannot be introduced into chip from wafer side or bottom surface, therefore can be fully solved brilliant back-grinding mistake at present
Si powder enters the problem of chip in journey.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
Figure 1A shows the wafer diagrammatic cross-section of pending brilliant back exposure mask；
Figure 1B shows the schematic diagram that Si powder enters the wafer of chip；
Fig. 2A~Fig. 2 I, which shows wafer thining method according to an embodiment of the present invention, successively to be implemented each step and is obtained
Obtain the diagrammatic cross-section of device；
Fig. 3 shows the flow chart of wafer thining method according to an embodiment of the present invention.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " other members
When part or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " is directly connected to
To " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.Art can be used although should be understood that
Language first, second, third, etc. describes various component, assembly units, area, floor and/or part, these component, assembly units, area, floor and/or portion
Dividing should not be limited by these terms.These terms are used merely to distinguish a component, assembly unit, area, floor or part and another
Component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, component, area,
Floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ",
" above " etc., herein can for convenience description and being used describe an elements or features shown in figure with it is other
The relationship of elements or features.It should be understood that other than orientation shown in figure, spatial relation term intention further include using with
The different orientation of device in operation.For example, then, being described as " below other elements " if the device in attached drawing is overturn
Or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary term
" ... below " and " ... under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other takes
To) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
The present invention provides a kind of wafer thining method, is used for thinned wafer thickness, so that its lightening and miniaturization, the party
Method includes the following steps: offer semiconductor crystal wafer, forms passivation layer in the semiconductor crystal wafer front, and etch the passivation layer
To form groove；Form the filled layer for covering the crystal round fringes and the groove and passivation layer；Remove crystal round fringes and ditch
Filled layer except slot region；Adhesive tape is formed on the passivation layer；Brilliant back-grinding is carried out to the wafer；Remove the glue
Band；Remove the filled layer.
Wafer thining method proposed by the present invention forms filled layer at the gaps such as Cutting Road and at crystal round fringes, this
Sample is when carrying out brilliant back-grinding, due to filling at the gaps such as Cutting Road and at crystal round fringes by filled layer, in process of lapping
The Si powder of generation whether all cannot be introduced into chip from wafer side or bottom surface, therefore can be fully solved brilliant back-grinding at present
Si powder enters the problem of chip in the process.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description, to illustrate this hair
The technical solution of bright proposition.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention
There can also be other embodiments.
It is described in detail below with reference to wafer thining method of Fig. 2A~Fig. 2 I and Fig. 3 to an embodiment of the present invention.
Firstly, executing step S301, semiconductor crystal wafer is provided, forms passivation layer in the semiconductor crystal wafer front, and lose
The passivation layer is carved to form groove.
As shown in Figure 2 A, semiconductor crystal wafer 200 is provided, forms passivation layer 201 in 200 front of semiconductor crystal wafer, and etch
Passivation layer 201 is to form groove 202.Wherein 200 front of wafer refers to formation element, lamination, interconnection line on a semiconductor substrate
And the surface of weld pad etc., opposite with front is backside of wafer.The surface that will be namely ground.
Semiconductor crystal wafer 200 can be following at least one of the material being previously mentioned: silicon, germanium, silicon-on-insulator
(SOI), silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI), germanium on insulator SiClx are laminated on insulator
(SiGeOI) and germanium on insulator (GeOI) etc..Such as PMOS and NMOS transistor are formed in semiconductor crystal wafer 200
Element.In addition, could be formed with isolation structure in semiconductor crystal wafer 200, the isolation structure is shallow trench isolation (STI) structure
Or selective oxidation silicon (LOCOS) isolation structure.Equally, conductive member, conductive structure can also be formed in semiconductor crystal wafer 200
Part can be the grid, source electrode or drain electrode of transistor, be also possible to the metal interconnection structure, etc. being electrically connected with transistor.
As an example, in the present embodiment, semiconductor crystal wafer 200 is monocrystalline silicon, and be formed with thereon such as PMOS and
NMOS element and interconnecting metal layer etc..
For passivation layer 201 for protecting the positive element of wafer 200, silica, silicon nitride, nitrogen is can be used in passivation layer 201
One of common used materials such as silica, phosphosilicate glass, boron phosphosilicate glass are a variety of, but and pass through such as its this use heat
The method commonly used in the art such as oxidizing process, sedimentation is formed.
As an example, in the present embodiment, silica and silicon nitride are formed by plasma activated chemical vapour deposition
Composite layer is as passivation layer 201.
After forming passivation layer 201, passivation layer 201 is etched, to form groove 202.Wherein groove 202, wherein
Groove 202 corresponds to the places such as the Cutting Road of wafer 200.
The etching of passivation layer 201 forms Other substrate materials, and make using conventional photolithography method on passivation layer 201
It is exposed with the exposure mask of predetermined shape, then by the patterned photoresist layer of development formation, and with patterned
Photoresist layer is that exposure mask is performed etching to form the groove of preset shape.
Then, step S302 is executed, the filled layer for covering the crystal round fringes and the groove and passivation layer is formed.
As shown in Figure 2 B, the filled layer 203 of covering 200 edge 200A of wafer and groove 202 and passivation layer 201 is formed.
Wherein filled layer 203 is negative photoresist or negative Other substrate materials, after exposure, the part not being irradiated by light can be gone with developer solution divided by
Form preset pattern.Filled layer 203 can be formed by coating method (such as rotary coating) or sedimentation.
As an example, in the present embodiment, forming polyimides (polyimide) material using chemical vapour deposition technique
Filled layer 20.
Then, step S303 is executed, wafer edge exposure is carried out, so as to cover the filled layer of the crystal round fringes through light
According to.
As shown in Figure 2 C, wafer edge exposure is carried out to wafer 200, so that the filled layer of covering 200 edge 200A of wafer
203A is through being illuminated by the light.Specifically, an edge of wafer 200 can be directed at irradiation light, and wafer is made by rotating wafer 200
200 entire edge is through being illuminated by the light, since the filled layer 203A of covering 200 edge 200A of wafer is the negative photoresist material of polyimides
Material, in this way after wafer edge exposure, the filled layer 203A of covering 200 edge 200A of wafer will not dissolve in developer solution.
Then, step S304 is executed, layer exposure is passivated to the wafer；So as to cover the filled layer warp of the groove
It is illuminated by the light.
As shown in Figure 2 D, layer exposure is passivated to wafer 200；So that the filled layer 203B of covering groove 202 is through light
According to.Specifically, in the present embodiment, using in step S301 when Etch Passivation 201 used predetermined shape exposure mask into
The exposure of row passivation layer so that the filled layer 203B of covering groove 202 is through being illuminated by the light, and is located at the filled layer of 201 top of passivation layer
203C is without being illuminated by the light, and in this way after passivation layer exposes, the filled layer 203B of covering groove 202 does not dissolve in developer solution, and position
Filled layer 203C above passivation layer 201 is then dissolved in developer solution.
Then, step S305 is executed, developed, solidified and ash operation, to remove the crystal round fringes and trench area
Filled layer except domain, and solidify the filled layer in crystal round fringes and the groove.
As shown in Figure 2 E, developed to wafer 200, solidified and ash operation, to remove 200 edge 200A of wafer and ditch
Filled layer except 202 region of slot, and solidify the filled layer in crystal round fringes 200A and groove 202.
Specifically, developer solution corresponding with the negative photoresist of polyimides can be used to remove filling out for 202 top of passivation layer
A layer 203C is filled, and carries out solidification and ash operation after the filled layer 203C above removal passivation layer 202, so that crystal round fringes
Filled layer solidification in 200A and groove 202, and the filled layer in crystal round fringes 200A and groove 202 is removed higher than passivation layer
202 part.That is, the region of exposure development is cured (i.e. fringe region and intermediate trench region), without cured region
It is ashed.
Then, step S306 is executed, forms adhesive tape on the passivation layer.
As shown in Figure 2 F, adhesive tape 204 is formed on passivation layer 201.Adhesive tape 204 is used for fixed wafer 200 when brilliant back-grinding
With the front of protection wafer 200, adhesive tape commonly used in the art, such as UV adhesive tape can be used.
Then, step S307 is executed, brilliant back-grinding is carried out to the wafer.
As shown in Figure 2 G, brilliant back-grinding is carried out to wafer 200, to remove certain thickness backing material, reaches and crystalline substance is thinned
Round purpose.Specifically, brilliant back-grinding uses method commonly used in the art, and details are not described herein.
Then, step S308 is executed, the adhesive tape is removed.
As illustrated in figure 2h, the adhesive tape 204 on passivation layer 201 is removed.The minimizing technology of adhesive tape 204 uses side commonly used in the art
Method, for example decline the adhesion strength of adhesive tape 204 by ultraviolet irradiation or heating, then cellotape 204.
Then, step S309 is executed, the filled layer is removed.
As shown in figure 2i, the filled layer 203B in the filled layer 203A and groove 202 of crystal round fringes is removed.Can specifically it lead to
Corresponding cleaning solution cleaning wafer 200 is crossed to remove filled layer.In the present embodiment, using for removing the negative photoresist of polyimides
Filled layer 203B in filled layer 203A and groove 202 of the TOK cleaning solution cleaning wafer 200 of material to remove crystal round fringes.
So far the Overall Steps of the present embodiment wafer thining method are completed, it is to be understood that in actual process
Before the present embodiment wafer thining method, among or may also include in other operations, such as step S301 later, when having etched
Further include cleaning step after passivation layer 201, to remove the residual substances such as remaining photoresist, developer solution, and carries out
WAT test, carries out subsequent step if qualified, if unqualified, without subsequent step.In addition, in removal filled layer
203 can also carry out visual inspection step, to detect the wafer after described be thinned with the presence or absence of problem.
The wafer thining method that the present embodiment proposes uses negative photoresist as filler, with bearing after Etch Passivation
Photoresist fill crystal round fringes region and gap position (positions such as groove, Cutting Road) in this way in subsequent brilliant back-grinding due to
Crystal round fringes and gap position, which fill up the Si powder generated in thus process of lapping by negative photoresist, cannot be introduced into chip.?
In the present embodiment, use negative photoresist as filler, and use two of the exposure steps method when forming filled layer, so that wafer
Fringe region and gap position are all covered with filled layer, in this way since crystal round fringes region and gap position are all covered with filling
Layer, both can avoid causing when only crystal round fringes region overlay has filled layer subsequent brilliant back exposure mask intermediate region amount of grinding more it is big, grind
It grinds non-uniform problem, and can avoid being caused by the gaps such as Cutting Road position when only wafer gap position is covered with filled layer and account for
Fewer (7% or so) and the problem of be easy piece.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (8)
1. a kind of wafer thining method, which is characterized in that include the following steps:
Semiconductor crystal wafer is provided, forms passivation layer in the semiconductor crystal wafer front, and etch the passivation layer to form groove；
Form the filled layer for covering the crystal round fringes and the groove and passivation layer；
The filled layer except crystal round fringes and trench region is removed, the filling being located in the crystal round fringes and the groove is retained
Layer；
Adhesive tape is formed on the passivation layer；
Brilliant back-grinding is carried out to the wafer；
Remove the adhesive tape；
Remove the filled layer.
2. wafer thining method according to claim 1, which is characterized in that the filled layer is negative photoresist.
3. wafer thining method according to claim 2, which is characterized in that under the step of forming the filled layer further includes
State step:
Wafer edge exposure is carried out, so as to cover the filled layer of the crystal round fringes through being illuminated by the light；
Layer exposure is passivated to the wafer；So as to cover the filled layer of the groove through being illuminated by the light；
Developed, solidified and ash operation, to remove the filled layer except the crystal round fringes and trench region, and makes wafer
Filled layer solidification in edge and the groove.
4. wafer thining method according to claim 3, which is characterized in that the exposure mask and erosion that the passivation layer exposure uses
It is identical to carve the exposure mask that the passivation layer uses.
5. wafer thining method according to claim 2, which is characterized in that the filling layer material is polyimides.
6. wafer thining method according to claim 2, which is characterized in that using described in the cleaning of negative photoresist cleaning agent
Wafer is to remove the filled layer.
7. wafer thining method described in one of -6 according to claim 1, which is characterized in that cover the crystal round fringes being formed
And before the filled layer of the groove and passivation layer further include: wafer acceptance test is carried out to the wafer, if test
It is qualified then carry out subsequent step；Conversely, then without subsequent step.
8. wafer thining method described in one of -6 according to claim 1, which is characterized in that also wrapped after removing the filled layer
It includes: visual inspection step, to detect the wafer after described be thinned with the presence or absence of problem.
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Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108609577B (en) * | 2016-12-12 | 2020-02-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of MEMS device |
| CN108346555A (en) * | 2017-01-23 | 2018-07-31 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof |
| CN108172498A (en) * | 2017-11-23 | 2018-06-15 | 南昌易美光电科技有限公司 | cleaning method based on chip thinning |
| CN108257851A (en) * | 2018-01-11 | 2018-07-06 | 上海华虹宏力半导体制造有限公司 | Wafer grinding method |
| CN108615706A (en) * | 2018-07-04 | 2018-10-02 | 南通沃特光电科技有限公司 | A kind of wafer singualtion method |
| CN108899302A (en) * | 2018-07-04 | 2018-11-27 | 南通沃特光电科技有限公司 | A kind of back-illuminated type CMOS sensor singualtion method |
| CN109037036A (en) * | 2018-08-02 | 2018-12-18 | 德淮半导体有限公司 | Crystal round fringes pruning method |
| CN111799152A (en) * | 2020-07-20 | 2020-10-20 | 绍兴同芯成集成电路有限公司 | Wafer double-sided metal process |
| CN112614912A (en) * | 2020-12-01 | 2021-04-06 | 浙江森尼克半导体有限公司 | Preparation method of indium antimonide chip |
| CN112959211B (en) * | 2021-02-22 | 2021-12-31 | 长江存储科技有限责任公司 | Wafer processing apparatus and processing method |
| CN114273992B (en) * | 2022-01-06 | 2022-11-01 | 西南应用磁学研究所(中国电子科技集团公司第九研究所) | Surface polishing method for patterned metal layer |
| CN117096011A (en) * | 2023-08-22 | 2023-11-21 | 扬州国宇电子有限公司 | Method and structure for improving adhesion between polyimide passivation layer and metal layer |
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| JP4364368B2 (en) * | 1999-10-27 | 2009-11-18 | リンテック株式会社 | Manufacturing method of semiconductor chip |
| JP2005044901A (en) * | 2003-07-24 | 2005-02-17 | Fuji Electric Holdings Co Ltd | Semiconductor wafer dividing method |
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| CN101131544A (en) * | 2006-08-25 | 2008-02-27 | 上海华虹Nec电子有限公司 | Method for improving silicon scraps contamination when back grinding |
| CN103105729A (en) * | 2011-11-14 | 2013-05-15 | 上海华虹Nec电子有限公司 | Photolithography method capable of preventing ground silicon dust from polluting wafers |
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