CN106601800A - 一种沟槽绝缘栅双极型晶体管 - Google Patents

一种沟槽绝缘栅双极型晶体管 Download PDF

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CN106601800A
CN106601800A CN201611094731.2A CN201611094731A CN106601800A CN 106601800 A CN106601800 A CN 106601800A CN 201611094731 A CN201611094731 A CN 201611094731A CN 106601800 A CN106601800 A CN 106601800A
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CN106601800B (zh
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王颖
刘彦娟
于成浩
曹菲
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Xiamen Lucky Microelectronics Co ltd
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Hangzhou Dianzi University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Bipolar Transistors (AREA)

Abstract

本发明提出了一种沟槽绝缘栅双极型晶体管,包括N‑型电压阻挡层、P型沟道区、P+欧姆接触区、N+发射区、P‑集电区、P+集电极区、N+衬底层以及沟槽栅极、栅氧介质层；其中，所述N‑型电压阻挡层和P型沟道区之间还存在一层N型电流增强层，所述的N‑型电压阻挡层与P型集电区之间存在一层N型缓冲层。该新结构背部具有一个由N‑型电压阻挡层、P‑集电区和N+衬底层组成的NPN晶体管，该NPN晶体管在器件关断过程中为N‑型电压阻挡层内存储的过量电子提供一个快速抽取的通道，减小器件的关断时间，从而减小器件的关断损耗，进而改善器件的通态压降与关断损耗之间的折衷关系。

Description

一种沟槽绝缘栅双极型晶体管
技术领域
本发明涉及绝缘栅双极型晶体管器件,尤其是沟槽绝缘栅双极型晶体管。
背景技术
IGBTs是由MOSFET和BJT组成的复合管，它融合了MOSFET和BJT这两种器件的优点，是一种理想的开关器件。而SiC优异的材料特性，例如3倍宽的禁带宽度，10倍高的临界场强，3倍大的热导率以及2倍高的载流子饱和速度，使得SiC基的半导体器件被广泛的应用到高温、高压、大功率等应用中。此外，由于单极器件的特征导通电阻与其击穿电压的2.5次方成正比，SiC MOSFETs器件不适合应用在击穿电压>10kV的领域。由于电导调制效应的存在，SiC IGBTs的特征导通电阻不再随击穿电压的增加而变化明显。与相同耐压的SiC MOSFETs器件相比，具有较低的特征导通电阻，适合应用于耐压>10kV的领域，例如智能电网，高压直流输电系统等电力电子系统。
然而，由于正向导通时电导调制效应的存在，尽管能降低器件的通态压降，但是同时又在漂移区中存储了大量的电子空穴对。关断时，这些存储在漂移区内的过量载流子需要一定的时间才能完全抽取和复合，会使得器件出现较长的电流拖尾，导致器件的关断损耗增加。正向导通时的电导调制效应越强，器件的通态压降越小，相应地关断损耗也越大。如何改善SiC IGBTs器件的导通压降与关断损耗之间的折衷关系，一直是业界的研究方向之一。
图1是现有的沟槽绝缘栅双极性晶体管结构示意图。
发明内容
本发明针对现有SiC IGBTs技术中的不足，提出了一种新的器件结构，该结构在其背部的集电极区集成一个NPN晶体管，在关断时为漂移区内的过量的电子提供一个抽取通道，从而加快电子的抽取速度进而减小器件的关断损耗。该结构的另一个特征就是高电阻率的P+集电区是位于N+衬底层上面，其厚度较薄，减小普通器件的厚的P+集电区对器件正向导通时的通态压降的影响。背部NPN晶体管的存在使得器件的关断损耗较低，改善器件的导通压降与关断损耗之间的折衷关系。
实现本发明目的技术方案：
一种沟槽绝缘栅双极型晶体管，N-型电压阻挡层上依次设有N型电流增强层、P型沟道区、由栅氧介质层和多晶硅栅电极构成的沟槽结构；所述的多晶硅栅电极通过栅氧介质层与所述的N+发射区、P型沟道区、N-型电压阻挡层相隔离；P+欧姆接触区和N+发射区设置在P型沟道区上；沟槽结构下面设有P+电场屏蔽区；N型缓冲层设置在N-型电压阻挡层下方，P-集电区、P+集电区设置在N型缓冲层下方，N+衬底层设置在P-集电区的下方，发射极电极位于P+欧姆接触区和N+发射区上面，并与P+欧姆接触区和N+发射区连接；所述集电极电极位于器件的底部，与N+衬底层和P+集电区相连接。
所述的N-型电压阻挡层的掺杂浓度为1014数量级，厚度大于100μm；
所述的P-集电区的掺杂浓度在1017～1018数量级之间，厚度在几微米至十几微米之间；
所述的N型缓冲的掺杂浓度要比N-型电压阻挡层的掺杂浓度高，在1016～1017数量级，厚度为几微米至几十微米之间；
所述的N型电流增强层的掺杂浓度要比N-型电压阻挡层的高，在1015～1016数量级，厚度为零点几微米至几微米之间；
所述的P型沟道区的掺杂浓度在1017～1018数量级，厚度为零点几微米至几微米之间。
本发明希望利用由器件背部的N+衬底层、P-集电区以及N-型电压阻挡层组成的NPN晶体管，在器件关断的过程中，加快对N-电压阻挡层存储的过量电子进行抽取速度，减小器件的关断时间，从而减小关断损耗，进而改善改善器件的导通压降与关断损耗之间的折衷关系。
附图说明
图1是现有的沟槽绝缘栅双极性晶体管结构示意图；
图2是本发明提出的沟槽绝缘栅双极型晶体管结构示意图；
图3是提出的沟槽绝缘栅双极型晶体管的制造过程示意图；
图4是提出的沟槽绝缘栅双极型晶体管的制造过程示意图；
图5是提出的沟槽绝缘栅双极型晶体管的制造过程示意图；
图6是提出的沟槽绝缘栅双极型晶体管的制造过程示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，以下结合附图对本发明进行具体阐述。
如图2所示，一种沟槽绝缘栅双极型晶体管，N-型电压阻挡层4上依次设有N型电流增强层7、P型沟道区8、由栅氧介质层12和多晶硅栅电极13构成的沟槽结构；所述的多晶硅栅电极13通过栅氧介质层12与所述的N+发射区9、P型沟道区8、N-型电压阻挡层4相隔离；P+欧姆接触区10和N+发射区9设置在P型沟道区8上；沟槽结构下面设有P+电场屏蔽区11；N型缓冲层3设置在N-型电压阻挡层4下方，P-集电区2、P+集电区6设置在N型缓冲层3下方，N+衬底层1设置在P-集电区2的下方，发射极电极14位于P+欧姆接触区10和N+发射区9上面，并与P+欧姆接触区10和N+发射区9连接；所述集电极电极15位于器件的底部，与N+衬底层1和P+集电区6相连接。
所述的N-型电压阻挡层4的掺杂浓度为1014数量级，厚度大于100μm。
所述的P-集电区2的掺杂浓度在1017～1018数量级之间，厚度在几微米至十几微米之间。
所述的N型缓冲3的掺杂浓度要比N-型电压阻挡层4的掺杂浓度高，在1016～1017数量级，厚度为几微米至几十微米之间。
所述的N型电流增强层7的掺杂浓度要比N-型电压阻挡层4的高，在1015～1016数量级，厚度为零点几微米至几微米之间。
所述的P型沟道区的掺杂浓度在1017～1018数量级，厚度为零点几微米至几微米之间。
本发明还提供了一种新的4H-SiC沟槽绝缘栅双极型晶体管的制造方法包括：
步骤1：在重掺杂的N+衬底层1上依次外延生长P-集电区2、N型缓冲层3和N-型电压阻挡层4，如图3所示。
步骤2：将晶片翻转，减薄N+衬底层1的厚度至所需要的值，然后选择性刻蚀P+集电区6的离子注入窗口5，如图4所示。
步骤3：通过窗口5利用注入离子的方式形成重掺杂的P+集电区6，如图5所示。
步骤4：再次翻转晶片，在N-型电压阻挡层4的正面，利用已经成熟的SiC UMOSFET制造工艺形成SiC IGBTs结构的正面结构，如图6所示。
步骤5：通过淀积金属形成发射极金属14和集电极金属15，形成如图2所示的新的4H-SiC沟槽绝缘栅双极型晶体管。
显然，本领域的技术人员可以对本发明进行各种改动和变形而不脱离本发明的精神和范围。应注意到的是，以上所述仅为本发明的具体实施例，并不限制本发明，凡在本发明的精神和原则之内，所做的调制和优化，皆应属本发明权利要求的涵盖范围。

Claims (6)

1.一种沟槽绝缘栅双极型晶体管，特征在于：N-型电压阻挡层上依次设有N型电流增强层、P型沟道区、由栅氧介质层和多晶硅栅电极构成的沟槽结构；所述的多晶硅栅电极通过栅氧介质层与所述的N+发射区、P型沟道区、N-型电压阻挡层相隔离；P+欧姆接触区和N+发射区设置在P型沟道区上；沟槽结构下面设有P+电场屏蔽区；N型缓冲层设置在N-型电压阻挡层下方，P-集电区、P+集电区设置在N型缓冲层下方，N+衬底层设置在P-集电区的下方，发射极电极位于P+欧姆接触区和N+发射区上面，并与P+欧姆接触区和N+发射区连接；所述集电极电极位于器件的底部，与N+衬底层和P+集电区相连接。
2.根据权利要求1所述一种沟槽绝缘栅双极型晶体管，特征在于：所述的N-型电压阻挡层的掺杂浓度为1014数量级，厚度大于100μm。
3.根据权利要求1所述一种沟槽绝缘栅双极型晶体管，特征在于：所述的P-集电区的掺杂浓度在1017～1018数量级之间，厚度在几微米至十几微米之间。
4.根据权利要求1所述一种沟槽绝缘栅双极型晶体管，特征在于：所述的N型缓冲的掺杂浓度要比N-型电压阻挡层的掺杂浓度高，在1016～1017数量级，厚度为几微米至几十微米之间。
5.根据权利要求1所述一种沟槽绝缘栅双极型晶体管，特征在于：所述的N型电流增强层的掺杂浓度要比N-型电压阻挡层的高，在1015～1016数量级，厚度为零点几微米至几微米之间。
6.根据权利要求1所述一种沟槽绝缘栅双极型晶体管，特征在于：所述的P型沟道区的掺杂浓度在1017～1018数量级，厚度为零点几微米至几微米之间。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108461537A (zh) * 2018-02-05 2018-08-28 电子科技大学 一种沟槽栅电荷存储型igbt及其制作方法
CN111129131A (zh) * 2018-10-30 2020-05-08 株洲中车时代电气股份有限公司 平面栅igbt器件

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103137679A (zh) * 2011-11-21 2013-06-05 上海华虹Nec电子有限公司 绝缘栅双极型晶体管器件结构及其制作方法
CN105789269A (zh) * 2016-03-04 2016-07-20 上海源翌吉电子科技有限公司 沟槽绝缘栅双极型晶体管及其制备方法
CN106098762A (zh) * 2016-07-26 2016-11-09 电子科技大学 一种rc‑igbt器件及其制备方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103137679A (zh) * 2011-11-21 2013-06-05 上海华虹Nec电子有限公司 绝缘栅双极型晶体管器件结构及其制作方法
CN105789269A (zh) * 2016-03-04 2016-07-20 上海源翌吉电子科技有限公司 沟槽绝缘栅双极型晶体管及其制备方法
CN106098762A (zh) * 2016-07-26 2016-11-09 电子科技大学 一种rc‑igbt器件及其制备方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
D.W.GREEN.ET.AL: "Performance analysis of the segment npn anode LIGBT", 《IEEE TRANSACTIONS ON ELECTRON DEVICES》 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108461537A (zh) * 2018-02-05 2018-08-28 电子科技大学 一种沟槽栅电荷存储型igbt及其制作方法
CN111129131A (zh) * 2018-10-30 2020-05-08 株洲中车时代电气股份有限公司 平面栅igbt器件
CN111129131B (zh) * 2018-10-30 2023-09-05 株洲中车时代半导体有限公司 平面栅igbt器件

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