CN106601625A - Clean-free hybrid integrated circuit welding method - Google Patents

Clean-free hybrid integrated circuit welding method Download PDF

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Publication number
CN106601625A
CN106601625A CN201611188414.7A CN201611188414A CN106601625A CN 106601625 A CN106601625 A CN 106601625A CN 201611188414 A CN201611188414 A CN 201611188414A CN 106601625 A CN106601625 A CN 106601625A
Authority
CN
China
Prior art keywords
welding
chip
solder
pedestal
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201611188414.7A
Other languages
Chinese (zh)
Inventor
尹国平
苏贵东
王德成
蔡景洋
聂平健
陈潇
陈帅业
卢辉昊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Guizhou Zhenhua Fengguang Semiconductor Co Ltd
Original Assignee
Guizhou Zhenhua Fengguang Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Guizhou Zhenhua Fengguang Semiconductor Co Ltd filed Critical Guizhou Zhenhua Fengguang Semiconductor Co Ltd
Priority to CN201611188414.7A priority Critical patent/CN106601625A/en
Publication of CN106601625A publication Critical patent/CN106601625A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4871Bases, plates or heatsinks
    • H01L21/4875Connection or disconnection of other leads to or from bases or plates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/814Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81401Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/81411Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/814Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81439Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/814Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81444Gold [Au] as principal constituent

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

The invention discloses a clean-free hybrid integrated circuit welding method comprising the following steps: using an all-solid-state prefabricated alloy solder sheet containing no soldering flux to replace an original paste type solder; using two alloy solders with different fuse points to respectively carry out mutual welding of a chip, a substrate circuit and a pedestal step by step under a nitrogen filling and temperature controllable environment, thus causing no pollution on the pedestal, the substrate circuit and the chip; directly bonding and packaging the product after welding, thus realizing clean-free welding. The product can be directly bonded and packaged after welding, thus preventing cleaning after welding, omitting cleaning agent usage and emission, saving time, and improving efficiency; compared with the paste type solder, the welding intensity of the product using the method is higher, and the product cannot drop in a constant acceleration test, thus further exceeding national military use standard prescribed requirements; the clean-free hybrid integrated circuit welding method is suitable for welding a housing and the substrate circuit with a welding metal medium as a welding surface, and suitable for assembling and welding a hybrid integrated circuit containing a backside metallization semiconductor chip and a passive element.

Description

A kind of No clean hydrid integrated circuit welding method
Technical field
The present invention relates to integrated circuit, furthermore, it is understood that being related to the welding method of hydrid integrated circuit.
Background technology
In original hydrid integrated circuit assembling, typically with cream solders such as soldering paste, epoxy conductings by chip, base Piece circuit, pedestal are welded as a whole.Because the cream solders such as soldering paste, epoxy conducting contain a certain proportion of scaling powder, In heating welding process, a part of scaling powder atomization, can be attached to pedestal, chip circuit and chip surface, after affecting product Continued key closes processing.Therefore, the product for being welded using cream solder is had to after welding to be had with three vinyl chlorides, acetone, ethanol etc. Machine solvent is cleaned.Even so, the residual that micro scaling powder and abluent stain can not be avoided completely, and its later stage volatilizees Gas out(Hydrogen, carbon dioxide etc.)Device inside atmosphere will be affected to deteriorate circuit performance, or even failure.
Jing is retrieved, and the application part for being related to hydrid integrated circuit welding in Chinese patent database is few, only 3, i.e.,: No. ZL2009200452501《The large-area welding fixture of hydrid integrated circuit special shaped soft substrate》, No. ZL2013102622616 《A kind of encapsulating method of the laser filler welding of hydrid integrated circuit encapsulation》With No. ZL201521009803X《Lead welding knot Structure and hydrid integrated circuit》.These patented technologies can not solve the problems, such as hydrid integrated circuit welding in prior art.
The content of the invention
It is an object of the invention to provide a kind of No clean hydrid integrated circuit welding method, by changing welding manner solution The problem that must be cleaned after certainly original hydrid integrated circuit welding.
To achieve the above object of the invention, the No clean hydrid integrated circuit welding method of inventor's offer is:Using not containing The all solid state prealloy solder sheet of scaling powder replaces original cream solder, in the environment of full of nitrogen and temperature-controllable, Chip, chip circuit, pedestal are carried out using the solder substep of two kinds of different melting points to be welded to each other, welding process will not be right Pedestal, chip circuit and chip are polluted, and directly can carry out being bonded, encapsulate after Product jointing, realize that No clean is welded;Specifically Way is:
The welding of first step pedestal and chip circuit
1)Pedestal is placed on graphite fixture, then fusing point is placed on pedestal for 280 DEG C of prefabricated gold-tin eutectic solder pieces, finally Chip circuit is stacked on gold alloy solder tablet, and adjusts pedestal, gold alloy solder tablet, chip circuit by matching requirements with tweezers Position and direction;
2)The component for assembling is positioned on the heating base plate of ATV702 type vacuum sintering furnaces together with graphite fixture, is closed Bell;
3)Nitrogen is filled into stove;
4)Welding temperature curve is set, makes high temperature section maintain 330 DEG C of temperature, time 1min;
5)Open ATV702 type vacuum sintering furnaces to be welded;
The welding of second step chip circuit and chip
1)After first step welding is completed, substrate is placed into for 221 DEG C of prefabricated silver alloy solder pieces by matching requirements fusing point On circuit, then by chip-stacked on gold alloy solder tablet, and the position of chip circuit, gold alloy solder tablet, chip is adjusted with tweezers Put and direction;
2)The component for assembling is positioned on the heating base plate of ATV702 type vacuum sintering furnaces together with graphite fixture, is closed Bell;
3)Nitrogen is filled into stove;
4)Welding temperature curve is set, makes high temperature section maintain 270 DEG C of temperature, time 2min;
5)Open ATV702 type vacuum sintering furnaces to be welded.
The solder of above two different melting points is the gold-tin eutectic solder and Sn96.5%- of Au80%-Sn20% respectively The tin-silver solder of Ag3.5%.
The No clean hydrid integrated circuit welding method of the present invention, directly can carry out being bonded after Product jointing, encapsulate, it is to avoid Cleaning after welding;Using and discharging for abluent can be avoided, while also time-consuming raising efficiency.Welded using this technique The product for connecing, weld strength are higher compared with cream solder, and product is amenable to 10000g Constant Acceleration Tests and does not fall off, far above state The 3000g that family military standard GJB 2438B specifies is required;Suitable for solder side be the shell of solderable metal medium, chip circuit With the assembly welding with back face metalization semiconductor chip, the hydrid integrated circuit of passive element.
Inventor points out:The various parts assembled using this method, solder side must be solderable metal medium.This method In addition to should be in the welding of hydrid integrated circuit, multi-chip module be applied also for(MCM), MEMS(MEMS), it is system-level Encapsulation(SiP)Components and parts in field are welded.
Description of the drawings
Typical structures of the Fig. 1 for hydrid integrated circuit, schematic diagrams of the Fig. 2 for No clean welding method
In figure, 1 is pedestal, and 2 is Au80%-Sn20% alloy weld tabs, and 3 is chip circuit, and 4 is Sn96.5%-Ag3.5% gold alloy solders Piece, 5 is chip, and 6 is lead.
Specific embodiment
Embodiment:With the FH0189 type high-voltage power operational amplifiers that Guizhou Zhenhua Fengguang Semiconductor Co., Ltd. produces it is Example, is typical hybrid integrated circuit structure, and altogether including 7 parts, inventory is as shown in table 1 altogether for its structural material:
FH0189 structural material inventories
Title material Model Quantity
Pedestal The round pedestal of TO-3 type metals 1
Alloy weld tabs Au80%-Sn20% 1
Chip circuit BeO chip circuits(Back side platinum silver soldering layer) 1
Alloy weld tabs Sn96.5%-Ag3.5% 2
Chip 541 type IC chips 2
Product jointing is welded using this method at twice and is completed, and by the process sequence of first high temperature low temperature again, first uses Au80%-Sn20% Solder sheet is welded on chip circuit on pedestal, and 2 541 chips are welded to base with Sn96.5%-Ag3.5% solder sheets again then On piece circuit.The product that welding is completed directly can be bonded.
3 products, product Jing X-ray checks are welded using the inventive method, voidage is less than 5%, is undergoing 10000g centrifugations After test, the intact nothing of all structures of product comes off.The voidage of the regulations of GJB GJB 2438 is much better than less than 50%, Undergo the requirement of 3000g centrifugal tests examination.With welding cavity it is little, weld strength is high the characteristics of.

Claims (2)

1. a kind of No clean hydrid integrated circuit welding method, it is characterised in that:Using all solid state prefabricated conjunction without scaling powder Gold solder tablet replaces original cream solder, in the environment of full of nitrogen and temperature-controllable, using the conjunction of two kinds of different melting points Gold solder substep carries out chip, chip circuit, pedestal and is welded to each other, and welding process will not be to pedestal, chip circuit and chip Pollute, directly can carry out being bonded after Product jointing, encapsulate, realize that No clean is welded;Specific practice is:
The welding of first step pedestal and chip circuit
Pedestal is placed on graphite fixture, then fusing point is placed on pedestal for 280 DEG C of prefabricated gold-tin eutectic solder pieces, finally Chip circuit is stacked on gold alloy solder tablet, and adjusts pedestal, gold alloy solder tablet, chip circuit by matching requirements with tweezers Position and direction;
The component for assembling is positioned on the heating base plate of ATV702 type vacuum sintering furnaces together with graphite fixture, close stove Lid;
Nitrogen is filled into stove;
(4) welding temperature curve is set, makes high temperature section maintain 330 DEG C of temperature, time 1min;
Open ATV702 type vacuum sintering furnaces to be welded;
The welding of second step chip circuit and chip
After first step welding is completed, it is that 221 DEG C of prefabricated silver alloy solder pieces are placed into substrate electricity by matching requirements fusing point Lu Shang, then by chip-stacked on gold alloy solder tablet, and the position of chip circuit, gold alloy solder tablet, chip is adjusted with tweezers And direction;
The component for assembling is positioned on the heating base plate of ATV702 type vacuum sintering furnaces together with graphite fixture, close stove Lid;
Nitrogen is filled into stove;
Welding temperature curve is set, makes high temperature section maintain 270 DEG C of temperature, time 2min;
Open ATV702 type vacuum sintering furnaces to be welded.
2. hydrid integrated circuit welding method as claimed in claim 1, it is characterised in that the alloy of described two different melting points Solder is the tin-silver solder of the gold-tin eutectic solder and Sn96.5%-Ag3.5% of Au80%-Sn20% respectively.
CN201611188414.7A 2016-12-21 2016-12-21 Clean-free hybrid integrated circuit welding method Pending CN106601625A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201611188414.7A CN106601625A (en) 2016-12-21 2016-12-21 Clean-free hybrid integrated circuit welding method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201611188414.7A CN106601625A (en) 2016-12-21 2016-12-21 Clean-free hybrid integrated circuit welding method

Publications (1)

Publication Number Publication Date
CN106601625A true CN106601625A (en) 2017-04-26

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CN (1) CN106601625A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030222126A1 (en) * 2002-03-29 2003-12-04 Fuji Electric Co., Ltd. Method of manufacturing semiconductor device
JP2005007412A (en) * 2003-06-17 2005-01-13 Sumitomo Metal Mining Co Ltd Solder clad piece
CN1666839A (en) * 2005-02-23 2005-09-14 中国电子科技集团公司第三十八研究所 Chip and carrier self-contrapositioning soft soldering method under gas protection
CN103779307A (en) * 2014-01-25 2014-05-07 嘉兴斯达半导体股份有限公司 Clean-free soldering power module and preparation method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030222126A1 (en) * 2002-03-29 2003-12-04 Fuji Electric Co., Ltd. Method of manufacturing semiconductor device
JP2005007412A (en) * 2003-06-17 2005-01-13 Sumitomo Metal Mining Co Ltd Solder clad piece
CN1666839A (en) * 2005-02-23 2005-09-14 中国电子科技集团公司第三十八研究所 Chip and carrier self-contrapositioning soft soldering method under gas protection
CN103779307A (en) * 2014-01-25 2014-05-07 嘉兴斯达半导体股份有限公司 Clean-free soldering power module and preparation method

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Application publication date: 20170426

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