CN106549653A

CN106549653A - A kind of new peak value latch circuit designs

Info

Publication number: CN106549653A
Application number: CN201510586698.4A
Authority: CN
Inventors: 胡荣炎
Original assignee: Individual
Current assignee: Individual
Priority date: 2015-09-16
Filing date: 2015-09-16
Publication date: 2017-03-29

Abstract

The invention belongs to technical field of integrated circuits, disclose a kind of new peak value latch circuit designs for switching power source chip, this circuit uses BiCMOS technologies, it is made up of the part such as delay circuit, control circuit, lock circuit, a kind of delay circuit of achievable temperature-compensating is adopted in time delay module, delay requirement is capable of achieving using the electric capacity of very little, it is effectively combined the real-time detectable voltage signals amplitude of variation of control signal and effectively removes the due to voltage spikes that on-off circuit initial time is produced, and crest voltage quick lock in is preserved.

Description

A kind of new peak value latch circuit designs

Technical field

The present invention relates to technical field of integrated circuits, more particularly, it relates to be used for switching power source chip in integrated circuit New offset latch cicuit technology.

Technical background

In Switching Power Supply, current harmonics component blows back into circuit, can cause the harmonic pollution of circuit, is to improve power work efficiency, Power factor correction technology is of increasing concern, in Active Power Factor Correction Technology, peak value comparison method method and average current control Preparation method is compared, simple with circuit structure, the advantages of loop compensation is easy, in peak current control circuitry, is needed to circuit Electric current is sampled, and is converted into voltage signal, and crest voltage is saved, and supplies subsequent conditioning circuit module, in work During, switching tube turn-on instant, the conducting electric current on armature winding start from zero linear increase, until it reaches peak value, in work( A small resistor is concatenated between the source and ground of rate switching tube, this current waveform is sampled, realize electric current turning to voltage Change.But power switch pipe in actual applications generally has very big breadth length ratio, so having the grid capacitance of several nanofarads Exist, when power tube grid end control signal by it is low uprise turn on switching tube when, this change can pass through grid source between electric capacity The source of power switch pipe is transferred to, a due to voltage spikes can be produced in initial time, and this due to voltage spikes can be given internal logic Circuit causes disorder, make circuit system cannot normal work, for prevent it is this interference make chip occur misoperation, generally require and keep away Open the time that this due to voltage spikes is produced.

Present invention aim at providing a kind of new offset latch cicuit for switching power source chip, BiCMOS is used in the design Technology, circuit are capable of achieving delay requirement by less electric capacity, so as to carry using the Long-time-delay circuit for being capable of achieving temperature-compensating The integrated level of high circuit, reduces cost, and the peak voltage that on-off circuit initial time is produced effectively is removed, and can fast lock It is fixed to preserve required voltage.

The content of the invention

The present invention proposes a kind of new offset latch cicuit for switching power source chip, and this circuit uses BiCMOS technologies, It is made up of the part such as delay circuit, control circuit, lock circuit, the main contents of the design are：

(1) circuit contains BiCOMS delay circuits, control circuit, lock circuit.

(2) the BiCOMS delay circuits described in include：The metal-oxide-semiconductor current mirroring circuit of M1, M2 composition, M3 are constituted MOS control pipes, M4, M5, M6, current biasing circuit and Bipolar transistors Q1 and fill that M9 is constituted Electric capacity C0, provides a time delayed signal for follow-up logic gates.

(3) the control circuit structure described in includes NMOS tube M7, phase inverter and phase inverter INV1 that M8 is constituted, INV2 and nor gate NOR1, NOR2.

(4) lock circuit described in includes M10, M11, M12, and two transmission gates and unity-gain voltage that M13 is constituted are slow Rush device composition.

The present invention can produce a due to voltage spikes in initial time for Switching Power Supply, and this due to voltage spikes can give internal logic electricity Disorder is caused on road, make circuit system cannot normal work, for prevent it is this interference make chip occur misoperation, generally require and avoid The time that this due to voltage spikes is produced, therefore devise a kind of new offset latch cicuit for switching power source chip.

Description of the drawings

Fig. 1 is voltage peak latch cicuit integrated circuit；

Fig. 2 is unit Gain Voltage Buffer structural representation.

Specific embodiment

Below in conjunction with the accompanying drawings the specific embodiment of the present invention is elaborated.

Voltage peak latch cicuit integrated circuit as shown in figure 1, on the left of dotted line be delay circuit, control end signal V_CFor logic Signal, works as V_CFor high level when, power switch pipe is off state, and the conducting of M3 pipes, electric capacity C0 both end voltages are forced Drag down, work as V_CDuring by high step-down, M3 pipes cut-off, power switch pipe open, now bias current pass through current mirror mirror image and Electric capacity C0 is charged after transistor Q1 effects, the charging current of electric capacity is equal to the base current of Bipolar transistor Q1：Ratios of the wherein M for the breadth length ratio of M1 and M2, I_eFor transistor Q1 emitter stages electricity Stream, current amplification factors of the β for transistor Q1.Charge the moment, a point voltage V_aStart linear rise, work as V_aFor power supply electricity During pressure, the cut-off of M4 pipes, M5 and M6 pipes are turned on, now V_bFor low level, V_dFor high level, the conducting of M7 pipes, M6 Tube short circuit, V_eFor low level, V_fFor high level, transmission gate is in Delayed conducting state.V_aDuring decline, when M4 is managed When electric current is more than M5 tube currents, V_b、V_dLevel overturns, and now a points turnover voltage is： Wherein g_m4And g_m5The respectively mutual conductance of M4 and M5 pipes, VDD is supply voltage.Work as V_aWhen being zero, the conducting of M4 pipes, M5 and M6 pipes end, now V_bFor high level, V_dFor low level, the cut-off of M7 pipes.V_aIn uphill process, work as M5 When tube current is bigger than M4 tube current, V_b、V_dLevel overturns, and now a points turnover voltage is：A points rise turnover voltage V_a2More than decline turnover voltage V_a1, therefore the control circuit With hysteresis function.Peak voltage exist time typically at the switching tube initial turn-on moment, this time about within 200ns, In view of the setting of forward position blocking time, the spike should be circumvented, while not affecting voltage signal sampling, it is considered to certain surplus, It is set as 300ns in the present invention, from delay circuit, when control signal V_CFor low level when, M3 pipes cut-off, time delay electricity Road is charged to electric capacity by current mirror and transistor Q1.

Latch cicuit is made up of transmission gate and unitary gain voltage buffer, and in latch cicuit, unitary gain voltage buffer circuit is such as Shown in Fig. 2, here using the automatic biasing folded cascode configuration of PMOS differential pair pipe, output voltage can be made good Follow input detection voltage, output stage adopts source follower, improve current output capability for subsequent conditioning circuit use, be can in real time with With detection input voltage, and the locking of quick high accuracy its crest voltage, the low frequency open-loop gain, input offset voltage to amplifier And its setup time has certain requirement.As the amplifier is used as unitary gain voltage buffer in circuit, input imbalance meeting exists The equivalent output of outfan, due to input voltage be detection voltage, detected value may as little as 200mV, input offset voltage Control within 2mV, in the case that maximum input voltage is 3V, its deviation is 0.66 ‰, the essence of unit gain amplifier Degree can be obtained by following formula：Wherein A₀For the low frequency open-loop gain of amplifier.Can be calculated and want to meet Ask, the low frequency open-loop gain of amplifier should be not less than 63.5dB.

In order to reach the quick purpose for latching crest voltage, here the setup time of amplifier there are certain requirements, in order that output electricity Pressure energy enough follows input voltage change closely, and according to circuit breaker in middle pipe minimum 2 μ s of ON time, reserving certain surplus here will fortune The setup time put is set in below 1 μ s.

Claims

1. a kind of new peak value latch circuit designs, it is characterised in that comprise the steps of：

1) peak value latch cicuit is made up of delay circuit, control circuit, lock circuit；

2) BiCOMS delay circuits include：The MOS controls of metal-oxide-semiconductor current mirroring circuit, M3 compositions that M1, M2 are constituted Pipe, M4, M5, M6, current biasing circuit and Bipolar transistors Q1 and charging capacitor C0 that M9 is constituted；

3) control circuit structure includes a metal-oxide-semiconductor M7, phase inverter that M8 is constituted and phase inverter INV1, INV2 and/or non- Door NOR1, NOR2；

4) lock circuit includes M10, M11, M12, two transmission gates and unitary gain voltage buffer that M13 is constituted.

2. a kind of new peak value latch circuit designs according to claim 1, it is characterised in that：Step (1) circuit Comprising peak value latch cicuit be made up of delay circuit, control circuit, lock circuit.

3. a kind of new peak value latch circuit designs according to claim 1, it is characterised in that：Step (2) circuit BiCOMS delay circuits are by control signal V_CControl, can circumvent the peak voltage of switch by controlling delay circuit.

4. a kind of new peak value latch circuit designs according to claim 1, it is characterised in that：Step (3) circuit The opening and closing of time delayed signal is controlled by logic function, rear class latch cicuit is controlled with this.

5. a kind of new peak value latch circuit designs according to claim 1, it is characterised in that：Step (4) circuit Latch cicuit is made up of transmission gate and unitary gain voltage buffer, and in latch cicuit, unitary gain voltage buffer circuit is adopted With the automatic biasing folded cascode configuration of PMOS differential pair pipe, output voltage can be made to follow input detection electricity well Pressure, output stage adopt source follower, improve current output capability and use for subsequent conditioning circuit.