CN106374887A

CN106374887A - Novel BiCMOS-based voltage peak latch circuit design

Info

Publication number: CN106374887A
Application number: CN201510425045.8A
Authority: CN
Inventors: 马利峰
Original assignee: Individual
Current assignee: Individual
Priority date: 2015-07-20
Filing date: 2015-07-20
Publication date: 2017-02-01

Abstract

The invention, which belongs to the technical field of an integrated circuit, discloses a novel BiCMOS-based voltage peak latch circuit design applied to a switching power supply chip. On the basis of the BiCMOS technology, the provided circuit is composed of a delay circuit, a control circuit, and a locking circuit. The delay circuit capable of realizing temperature compensation is employed in a delay module and a delay requirement can be met by using a small capacitor. A voltage signal amplitude change is detected in real time by combining a control signal effectively and a voltage peak generated at an initial time of a switching circuit can be eliminated effectively, and a peak voltage can be locked and stored rapidly.

Description

A kind of new bicmos voltage peak latch circuit designs

Technical field

The present invention relates to technical field of integrated circuits, more particularly, it relates in integrated circuit, it is used for switching power source chip New bicmos voltage peak latch cicuit technology.

Technical background

In Switching Power Supply, current harmonics component blows back into circuit, can cause the harmonic pollution of circuit, for improving power work efficiency, Power factor correction technology is of increasing concern, in Active Power Factor Correction Technology, peak value comparison method method and average current control Preparation method is compared, and has the advantages of circuit structure is simple, and loop compensation is easy, in peak current control circuitry, needs to circuit Electric current is sampled, and is converted into voltage signal, and crest voltage is saved, and supplies subsequent conditioning circuit module, in work During, switching tube turn-on instant, the conducting electric current on armature winding starts from zero linear increase, until it reaches peak value, in work( Concatenate a small resistor between the source of rate switching tube and ground, this current waveform is sampled, realize electric current turning to voltage Change.But power switch pipe in actual applications generally has very big breadth length ratio, so having the grid capacitance of several nanofarads Exist, when power tube grid end control signal by low uprise so that switching tube is turned on when, this change can be by the electric capacity between grid source It is transferred to the source of power switch pipe, a due to voltage spikes can be produced in initial time, and this due to voltage spikes can give internal logic Circuit causes disorder, make Circuits System cannot normal work, for prevent this interference make chip occur misoperation, generally require and keep away Open the time of this due to voltage spikes generation.

Present invention aim at providing a kind of new bicmos voltage peak latch cicuit for switching power source chip, this sets Meter uses bicmos technology, and circuit, using the Long-time-delay circuit that can achieve temperature-compensating, be can achieve by less electric capacity Delay requirement, thus improving the integrated level of circuit, reduces cost, and effectively remove the spike that on-off circuit initial time produces Voltage, and required voltage can be preserved by quick lock in.

Content of the invention

The present invention proposes a kind of new bicmos voltage peak latch cicuit for switching power source chip, this circuit fortune Use bicmos technology, be made up of the part such as delay circuit, control circuit, lock circuit, the main contents of this design are: (1) circuit contains bicoms delay circuit, control circuit, lock circuit.

(2) the bicoms delay circuit described in includes: the mos tube current mirror circuit that m1, m2 are constituted, m3 are constituted Mos control pipe, current biasing circuit and bipolar transistor q1 and filling that m4, m5, m6, m9 are constituted Electric capacity c0, provides a time delayed signal for follow-up logic gates.

(3) the control circuit structure described in includes a nmos pipe m7, phase inverter and phase inverter inv1 that m8 is constituted, Inv2 and nor gate nor1, nor2.

(4) lock circuit described in includes m10, and two transmission gates that m11, m12, m13 are constituted and unity-gain voltage delay Rush device to constitute.

The present invention can produce a due to voltage spikes for Switching Power Supply in initial time, and this due to voltage spikes can be to internal logic electricity Disorder is caused on road, make Circuits System cannot normal work, for prevent this interference make chip occur misoperation, generally require and avoid The time that this due to voltage spikes produces, therefore devise a kind of new bicmos voltage peak lock for switching power source chip Deposit circuit.

Brief description

Fig. 1 is voltage peak latch cicuit integrated circuit；

Fig. 2 is unit Gain Voltage Buffer structural representation.

Specific embodiment

Below in conjunction with the accompanying drawings the specific embodiment of the present invention is elaborated.

Voltage peak latch cicuit integrated circuit, as shown in figure 1, being delay circuit on the left of dotted line, controls end signal v_cFor logic Signal, works as v_cDuring for high level, power switch pipe is off state, and m3 pipe turns on, and electric capacity c0 both end voltage is forced Drag down, work as v_cDuring by high step-down, m3 pipe end, power switch pipe open, now bias current pass through current mirror mirror image and After transistor q1 effect, electric capacity c0 is charged, the charging current of electric capacity is equal to the base current of bipolar transistor q1:Wherein m is the ratio of the breadth length ratio of m1 and m2, i_eFor transistor q1 emitter stage electricity Stream, β is the current amplification factor of transistor q1.Charge the moment, a point voltage v_aStart linear rise, work as v_aFor power supply electricity During pressure, m4 pipe ends, m5 and m6 pipe turns on, now v_bFor low level, v_dFor high level, the conducting of m7 pipe, m6 Tube short circuit, v_eFor low level, v_fFor high level, transmission gate is in Delayed conducting state.v_aDuring decline, when m4 pipe When electric current is more than m5 tube current, v_b、v_dLevel overturns, and now a point turnover voltage is: Wherein g_m4And g_m5It is respectively the mutual conductance of m4 and m5 pipe, vdd is supply voltage.Work as v_aWhen being zero, m4 pipe turns on, M5 and m6 pipe ends, now v_bFor high level, v_dFor low level, the cut-off of m7 pipe.v_aIn uphill process, work as m5 When tube current is bigger than m4 tube current, v_b、v_dLevel overturns, and now a point turnover voltage is:A point rises turnover voltage v_a2More than decline turnover voltage v_a1, therefore this control circuit Have hysteresis function a peak voltage presence time typically in the switching tube initial turn-on moment, this time about within 200ns, In view of the setting of forward position blocking time, this spike should be circumvented, not affect voltage signal sampling it is considered to certain surplus simultaneously, It is set as 300ns, from delay circuit, when control signal v in the present invention_cDuring for low level, m3 pipe ends, time delay electricity Road is charged to electric capacity by current mirror and transistor q1.

Latch cicuit is made up of transmission gate and unitary gain voltage buffer, and in latch cicuit, unitary gain voltage buffer circuit is such as Shown in Fig. 2, adopt the automatic biasing folded cascode configuration of pmos differential pair tube here, output voltage can be made good Follow input detection voltage, output stage adopts source follower, improve current output capability and supply subsequent conditioning circuit use, for can in real time with With detection input voltage, and its crest voltage of the locking of quick high accuracy, to the low frequency open-loop gain of amplifier, input offset voltage And its setup time has certain requirement.Because this amplifier is used as unitary gain voltage buffer in circuit, input imbalance meeting exists The equivalent output of outfan, because input voltage is detection voltage, detected value may as little as 200mv, input offset voltage Control within 2mv, in the case that maximum input voltage is 3v, its deviation is 0.66 ‰, the essence of unit gain amplifier Degree can be obtained by following formula:Wherein a₀Low frequency open-loop gain for amplifier.Can be calculated and want for meeting Ask, the low frequency open-loop gain of amplifier should be not less than 63.5db.

In order to reach the quick purpose latching crest voltage, here the setup time of amplifier be there are certain requirements, in order that output electricity Pressure energy enough follows input voltage change closely, according to circuit breaker in middle pipe minimum ON time 2 μ s, reserves certain surplus and will transport here The setup time put is set in below 1 μ s.

Claims

1. a kind of new bicmos voltage peak latch circuit designs are it is characterised in that comprise the steps of

1) bicmos voltage peak latch cicuit is made up of delay circuit, control circuit, lock circuit；

2) bicoms delay circuit includes: the mos tube current mirror circuit that m1, m2 are constituted, the mos of m3 composition control Pipe, current biasing circuit and bipolar transistor q1 and charging capacitor c0 that m4, m5, m6, m9 are constituted；

3) control circuit structure includes a mos pipe m7, phase inverter and phase inverter inv1 that m8 is constituted, inv2 and/or non- Door nor1, nor2；

4) lock circuit includes m10, two transmission gates and unitary gain voltage buffer that m11, m12, m13 are constituted.

2. a kind of new bicmos voltage peak latch circuit designs according to claim 1 it is characterised in that: described step Suddenly the bicmos voltage peak latch cicuit that (1) circuit comprises is made up of delay circuit, control circuit, lock circuit.

3. a kind of new bicmos voltage peak latch circuit designs according to claim 1 it is characterised in that: described step Suddenly (2) circuit bicoms delay circuit is by control signal v_cControl, switch can be circumvented by controlling delay circuit Peak voltage.

4. a kind of new bicmos voltage peak latch circuit designs according to claim 1 it is characterised in that: described step Suddenly (3) circuit controls the opening and closing of time delayed signal by logic function, controls rear class latch cicuit with this.

5. a kind of new bicmos voltage peak latch circuit designs according to claim 1 it is characterised in that: described step Suddenly (4) circuit latch cicuit is made up of transmission gate and unitary gain voltage buffer, unity-gain voltage in latch cicuit Buffer circuits adopt pmos differential pair tube automatic biasing folded cascode configuration, can make output voltage well with With input detection voltage, output stage adopts source follower, improves current output capability and uses for subsequent conditioning circuit.