CN106549030B - A kind of imaging sensor and preparation method thereof - Google Patents
A kind of imaging sensor and preparation method thereof Download PDFInfo
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- CN106549030B CN106549030B CN201610885730.3A CN201610885730A CN106549030B CN 106549030 B CN106549030 B CN 106549030B CN 201610885730 A CN201610885730 A CN 201610885730A CN 106549030 B CN106549030 B CN 106549030B
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- 238000003384 imaging method Methods 0.000 title claims abstract description 31
- 238000002360 preparation method Methods 0.000 title claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 140
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 80
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 80
- 239000010703 silicon Substances 0.000 claims abstract description 80
- 238000000605 extraction Methods 0.000 claims abstract description 28
- 210000000746 body region Anatomy 0.000 claims abstract description 17
- 238000012545 processing Methods 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims description 35
- 239000002184 metal Substances 0.000 claims description 35
- 238000000034 method Methods 0.000 claims description 15
- 238000005516 engineering process Methods 0.000 description 22
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14634—Assemblies, i.e. Hybrid structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/1469—Assemblies, i.e. hybrid integration
Abstract
The present invention provides a kind of imaging sensors and preparation method thereof, comprising: prepares pixel array and its line in the silicon body region of the first SOI substrate；The control circuit and its extraction pole of each pixel array are prepared in the silicon body region of the second SOI substrate；Reading circuit and image processing algorithm circuit and its extraction pole are prepared in a silicon substrate；By the first SOI substrate with pixel array and its line with the 2nd SPI substrate have control circuit while be bonded, the control circuit one-to-one correspondence of the pixel array of the first SOI substrate and the second SOI substrate；The silicon layer for the one side that first SOI substrate is not bonded is peeled off, so that the first SOI substrate has flat upper surface；The bottom surface of second SOI substrate is mutually bonded with the one side with reading circuit and image processing algorithm circuit in the silicon substrate；The extraction pole of second SOI substrate is connected with the extraction pole in the silicon substrate, to reduce device dark current, improves device quality.
Description
Technical field
The present invention relates to technical field of integrated circuits, and in particular to a kind of imaging sensor and preparation method thereof.
Background technique
Imaging sensor is the important component for forming digital camera.Before traditional cmos image sensor uses
Photosensitizing type (FSI, Front Side Illumination) technology, i.e., it is preceding to shine technology.It is preceding to be mainly characterized by according to technology in silicon wafer
Front makes light sensitive diode, metal interconnection and light pipe hole (Light Pipe) in order, as shown in figure.Its advantage is that:
Simple process, it is completely compatible with CMOS technology；Cost is relatively low；Light pipe packing material refractive index is adjustable；Be conducive to improve
The transmissivity of incident light reduces crosstalk etc..Preceding according to technology is a kind of technology compatible with CMOS standard technology, is widely used in each
The production of kind (especially big pixel) cmos image sensor chip.However, since light is firstly the need of the metal by upper layer
Interconnection can just be irradiated to the light sensitive diode of lower section, because usually lower according to the fill factor of technology and sensitivity before this.
With becoming smaller for Pixel Dimensions, improves fill factor and come more difficult, another technology is before traditional at present
Photosensitizing type becomes back photosensitizing type (BSI, Back Side Illumination), i.e. back-illuminated technology.The main spy of back-illuminated technology
Point is to make light sensitive diode, metal interconnection in order in front side of silicon wafer first, and then silicon chip back side, which is thinned, (usually needs
Be thinned to 20um or less), and by through silicon via technology most important for back photosensitizing type cmos sensor (TSV,
Through-Silicon-Via light sensitive diode) is subjected to interconnection extraction, as shown in Figure 2.Through silicon via technology is by core
Between piece and chip, vertical conducting is made between wafer and wafer, realizes the state-of-the-art technology interconnected between chip.Due to interconnection electricity
Road is placed in back, and front all leaves photodiode for, thereby realizes fill factor as big as possible.Through silicon via technology
Advantage is to be irradiated to the incident light of light sensitive diode not influenced by metal interconnection, and sensitivity is higher, and fill factor is higher.However,
Through silicon via technical difficulty is higher, and to the more demanding of equipment, cost is also relatively high.And due to subtracting for ultra thin silicon wafers
The limitation of thin technique, usual back-illuminated technology are applied in the imaging sensor of small pixel (at present applied to the medium and small of smart phone
Pixel camera head generallys use back-illuminated technology).
For imaging sensor, most important parameter first is that dark current, dark current be characterized in the case of half-light due to
Noise caused by Pixel itself.Usually, when being BSI using body silicon, body silicon is thinned in CMP process (CMP)
When can generate homogeneity question (at most control in um precision) and lattice damage, this is not only to influence quantum efficiency (QE) uniformity
Factor and BSI cmos image sensor (CIS) dark current generate main source.If using SOI substrate, SOI lining
Bottom remaining SiO after removing Si2Very smooth, dark current is good, and isolation performance might as well.
It is the thin body silicon in the soi wafer of a standard in the conventional method for preparing imaging sensor on soi substrates
Substrate zone makes the pixel array region of imaging sensor, including light sensitive diode and control transistor；It is served as a contrast in a standard body silicon
The reading circuit of imaging sensor is made on bottom.Above-mentioned production is finished to the SOI substrate of pixel array and the body silicon of reading circuit
Substrate carries out metal bonding, the stacking substrate after metal bonding, and top is the pixel array region of SOI substrate, and lower section is body
The reading circuit area of silicon substrate.Lower cube silicon substrate can be fabricated to intermediate recess shape by process, i.e., intermediate to use one
Layer polysilicon+three-layer metal (1POLY+3metal) makes, and around uses one layer of polysilicon+three-layer metal+metal interconnecting layer
(RDL layer generally uses aluminium medium, and thickness is thicker, and resistivity is smaller, big commonly used in pad for (1POLY+3metal+RDL) production
Area metal).Intermediate recess region is consistent with top SOI substrate size, can match be stacked up and down.Top SOI lining
The thick silicon layer at bottom is removed, and the buried oxide layer of SOI can be retained.SOI wafer remaining SiO after removing Si2It is very smooth, dark current
Good, isolation performance might as well.It is highly beneficial for picture quality.By the encapsulation technology of cmos image sensor, by contact block
(PAD) metal wire extraction (PAD is located below at the inter-level dielectric of body silicon substrate) is carried out, realized to the cmos image sensor core
The encapsulation of piece.
This method can effectively reduce dark current, and still, current cmos image sensor integrates many on substrate mostly
Complicated image processing algorithm, particularly with vehicle-mounted or cell phone type imaging sensor, due to the requirement of high integration, substrate
On digital processing circuit it is very more and complicated.These digital circuits can introduce a large amount of digital noises, the string that these noises generate
It disturbs meeting and adverse effect is generated to the pixel array area (Pixel Array) on upper layer, so that occurring in finally obtained image various
Fixed and random noise.
Summary of the invention
In order to overcome the above problems, the present invention is intended to provide a kind of cmos image sensor and preparation method, to overcome
Image processing unit noise crosstalk interference problem.
In order to achieve the above object, the present invention provides a kind of preparation methods of imaging sensor, comprising:
Pixel array and its line are prepared in the silicon body region of the first SOI substrate；
The control circuit and its extraction pole of each pixel array are prepared in the silicon body region of the second SOI substrate；
Reading circuit and image processing algorithm circuit and its extraction pole are prepared in a silicon substrate；
One side by the first SOI substrate with pixel array and its line has the one of control circuit with the 2nd SPI substrate
Face is bonded, and the control circuit of the pixel array of the first SOI substrate and the second SOI substrate corresponds；
The silicon layer for the one side that first SOI substrate is not bonded is peeled off, so that the first SOI substrate has flat upper table
Face；
By one with reading circuit and image processing algorithm circuit in the bottom surface of the second SOI substrate and the silicon substrate
Face is mutually bonded；
The extraction pole of second SOI substrate is connected with the extraction pole in the silicon substrate.
Preferably, the thickness of the silicon body region of first SOI substrate is less than the one side of first SOI substrate not being bonded
Silicon layer thickness.
Preferably, the thickness of the silicon body region of second SOI substrate is less than the one side of second SOI substrate not being bonded
Silicon layer thickness.
Preferably, the pixel array and its line are light sensitive diode array and its metal interconnecting layer.
Preferably, the control circuit includes control transistor and its line.
Preferably, the control transistor is drawn by the first I/O circuit, and the first I/O circuit is located at the picture of the first SOI substrate
Around below pixel array.
Preferably, first I/O circuit is drawn by the extraction pole of second SOI substrate.
It preferably, include the second I/O circuit in the reading circuit and image processing algorithm circuit, the second I/O circuit is located at
Around below second SOI substrate；And second I/O circuit is drawn by the extraction pole of the silicon substrate.
Preferably, it is bonded between first SOI substrate and the second SOI substrate by metallic bond, second SOI substrate
It is bonded with the silicon substrate by Si prediction.
In order to achieve the above object, the present invention also provides a kind of according to obtained by the preparation method of above-mentioned imaging sensor
Imaging sensor comprising: the silicon substrate, second SOI substrate and the first SOI set gradually from the bottom up
Substrate.
The present invention has following technical advantage:
A. technique is wanted compared to production reading circuit, control circuit, interconnection line, IO and the pad on standard body silicon wafer
Ask it is higher need to be using for advanced technology, the present invention makes image sensor pixel cells in the SOI substrate of standard
Only need the micro process of low cost it is achieved that therefore saving a large amount of techniques to the production of image sensor pixel cells
Cost.
B. in cmos image sensor of the invention, since what is retained after the top layer silicon of the first SOI substrate of removing buries oxygen
Layer surface is very smooth, so that the dark current of obtained device is good, isolation performance improves the matter of acquired image
Amount.
C. cmos image sensor of the invention has used reduction process due to avoiding, thus avoid CMP be thinned bring
Homogeneity question (at most control in um precision) and lattice damage, also avoid the image quality decrease caused by being thinned.
D. remain physically between the first SOI substrate of the invention and the second SOI substrate above it is natural be isolated,
And isolation effect is preferable；Although the reading circuit and image processing algorithm circuit in the silicon substrate of bottommost are made an uproar there may be larger
Sound, but since (the first SOI substrate is to making an uproar to the second SOI substrate region of noise (generate) with the first SOI substrate above it
The region of acoustic sensing) there are enough distances, which avoids crosstalk from each other, is reducing chip ruler
Very little notice, does not influence picture quality.
Detailed description of the invention
Fig. 1 is the flow diagram of the preparation method of the imaging sensor of a preferred embodiment of the invention
Fig. 2-8 is each preparation step schematic diagram of the preparation method of the imaging sensor of a preferred embodiment of the invention
Specific embodiment
To keep the contents of the present invention more clear and easy to understand, below in conjunction with Figure of description, the contents of the present invention are made into one
Walk explanation.Certainly the invention is not limited to the specific embodiment, general replacement known to those skilled in the art
It is included within the scope of protection of the present invention.
Below in conjunction with attached drawing 1-8 and specific embodiment, invention is further described in detail.It should be noted that attached drawing is equal
The present embodiment is aided in illustrating to facilitate, clearly reach using very simplified form, using non-accurate ratio, and only
Purpose.
Referring to Fig. 1, the preparation method of the imaging sensor of the present embodiment, comprising:
Step 01: preparing pixel array and its line in the silicon body region of the first SOI substrate；
Specifically, referring to Fig. 2, the first SOI substrate 01 have top layer silicon 011, buried oxide layer 012 and bottom body silicon 013,
The thickness of bottom silicon body region 013 can be less than the thickness of the top layer silicon 011 for the one side of the first SOI substrate 01 not being bonded.Pixel
Array and its line can be light sensitive diode array and its metal interconnecting layer；Specifically, firstly, being prepared in silicon body region 013
Light sensitive diode D out prepares polysilicon P1 and metal layer M11, polysilicon P1, metal layer M11 and sense around light sensitive diode D
Optical diode interconnection, extraction of the polysilicon P1 for the subsequent light sensitive diode D electric signal generated.Metal layer M11 is mainly used for
Metal bonding is realized with the second SOI substrate 02 in subsequent bonding technology.Here it is possible in the silicon body region of the first SOI substrate 01
The preparation of light sensitive diode D is completed in 013 using micro process.
It should be noted that pixel array prepared by the silicon body region of the first SOI substrate and its line are unlimited in the present invention
The one layer of metal layer M11 referred in this present embodiment in other embodiments of the invention can also be D weeks in light sensitive diode
It encloses and prepares polysilicon P1 and more metal layers M11, for example, two layers, three layers or four layers.
Step 02: preparing the control circuit and its extraction pole of each pixel array in the silicon body region of the second SOI substrate；
Specifically, referring to Fig. 3, the second SOI substrate 02 include top layer silicon 021, buried oxide layer 022 and bottom silicon body region 023,
The thickness of the bottom silicon body region 023 of second SOI substrate 02 can be less than the top layer silicon for the one side of the second SOI substrate 02 not being bonded
021 thickness；Control circuit includes control transistor and its line；It controls transistor to draw by the first I/O circuit i, the first IO
Around circuit i is located at below the pixel array of the first SOI substrate 01.First I/O circuit i passes through the extraction of the second SOI substrate 02
It draws pole.Here, the extraction extremely PAD1 of the second SOI substrate 02.That dotted line separates in Fig. 3 is each pixel (pixel) respectively,
Pixel 1 and pixel2 is illustrated in Fig. 3, but the pixel of bottom silicon body region 023 is not limited to the two.
In general, the size of these control transistors is all larger (~0.35um), therefore, can be in the SOI silicon of standard
On piece can be completed using micron-sized process equipment.
In Fig. 3, M1, M2 and M3 three-layer metal layer are formed with above polysilicon P2, it should be noted that the present invention in
The metal layer formed above polysilicon P2 be not limited to the present embodiment in tri- layers of M1, M2 and M3 shown in Fig. 3, can be at least one layer
Metal layer, for example, one layer, two layers or four layers.
Step 03: reading circuit and image processing algorithm circuit and its extraction pole are prepared in a silicon substrate；
Specifically, referring to Fig. 4, in order to save chip size, reading circuit and image processing algorithm circuit can be located at
The lower section of the pixel array region of first SOI substrate 01 and the control circuit area of the second SOI substrate 02, reading circuit and image procossing
Algorithm circuit includes polysilicon P3, metal layer M21, M22, M23；What needs to be explained here is that in other embodiments of the invention,
Metal layer be not limited to the present embodiment in three-layer metal layer M21, M22, M23 shown in Fig. 4, can also be more metal layers, such as
For two metal layers or four layers of metal layer.
Reading circuit and image processing algorithm circuit need to carry out signal extraction by IO.Reading circuit and image procossing are calculated
It include the second I/O circuit ii in method circuit, around the second I/O circuit ii is located at below the second SOI substrate 02；And the 2nd IO electricity
Road ii is drawn by the extraction pole of silicon substrate 03.Here, the extraction of silicon substrate 03 extremely PAD2.
Referring to Fig. 4, at the corresponding reading circuit of each pixel unit of the expression that dotted line frame separates in Fig. 4 and image
Adjustment method circuit.
It should be noted that there may be larger noises for reading circuit and image processing algorithm circuit, but due to the mark
Remain physically between quasi- body silicon wafer and above-mentioned SOI wafer piece it is natural be isolated, and isolation effect is good, therefore, can will
Reading circuit and image processing algorithm circuit design are reducing chip size simultaneously, not shadow in the lower section of the pixel array region SOI
Ring picture quality.And in traditional technology in order to reduce lower section the biggish reading circuit of noise to upper images sensor pixel array
The influence in area need to avoid being placed on noise larger circuit below image sensor pixel array area, and be placed on pixel array region
Peripheral region.
Step 04: the one side by the first SOI substrate with pixel array and its line has control electricity with the second SOI substrate
Road is bonded on one side, and the control circuit of the pixel array of the first SOI substrate and the second SOI substrate corresponds；
Specifically, referring to Fig. 5, being bonded between the first SOI substrate 01 and the second SOI substrate 02 by metallic bond, first
Bonding between the metal M11 of SOI substrate 01 and the metal M3 of the second SOI substrate 02, photosensitive two pole of each of pixel array
Pipe D passes through metal bonding and links together with lower section control transistor.Such as 4 pipe pixels, need to make reset
(RESET) device (RS), transformer (Transformer) device (TX), row selection (ROW select) device (ROW), source with
With four control transistors of device (Source Follower) device (SF), including polysilicon P2, metal layer M1, M2, M3.In order to
Make to control transistor and light sensitive diode D in upper layer is interconnected, the metal bonding (Cu- of subsequent technique is realized by top-level metallic M3
Cu Bonding)。
Step 05: the silicon layer for the one side that the first SOI substrate is not bonded being peeled off, so that the first SOI substrate is with flat
Upper surface；
Specifically, referring to Fig. 6, the top layer silicon 013 for the side that the first SOI substrate 01 is not bonded peels off, Ke Yibao
After staying the buried oxide layer 012 of the first SOI substrate 01, the first SOI substrate 01 to be stripped, the performance of the buried oxide layer 012 of reservation is very flat
Whole, therefore, the dark current of obtained device is good, and isolation performance improves the matter of image acquired in imaging sensor
Amount.
Step 06: will there is reading circuit and image processing algorithm circuit in the bottom surface and silicon substrate of the second SOI substrate
One side be mutually bonded；
Specifically, referring to Fig. 7, the upper surface of the bottom surface of the second SOI substrate 02 and silicon substrate 03 by Si-Si bond conjunction,
Form the imaging sensor stacked.
Step 07: the extraction pole of the second SOI substrate is connected with the extraction pole in the silicon substrate.
Specifically, referring to Fig. 8, by wiring (Wire Bonding) technology of cmos image sensor, by PAD1 into
Row metal line is drawn, and PAD1 is connected with PAD2, realizes the interconnection of the second SOI substrate 02 and silicon substrate 03, finally
To image sensor structure as shown in figure 8, the imaging sensor includes: the silicon substrate 03, second set gradually from the bottom up
SOI substrate 02 and the first SOI substrate 01；Here, the second SOI substrate 02 is located at 01 lower section of the first SOI substrate, and the 2nd SOI is served as a contrast
The I/O circuit i at bottom 02 can be located at the region around 01 lower section of the first SOI substrate, and silicon substrate 03 is located under the second SOI substrate 02
Side, and the I/O circuit ii of silicon substrate 03 can be located at the region around 02 lower section of the second SOI substrate.Other about the structure retouch
Stating can be with reference to above-described embodiment, and which is not described herein again.
Although the present invention is disclosed as above with preferred embodiment, right embodiment is illustrated only for the purposes of explanation, and
It is non-to limit the present invention, those skilled in the art can make without departing from the spirit and scope of the present invention it is several more
Dynamic and retouching, the protection scope that the present invention is advocated should be subject to claims.
Claims (10)
1. a kind of preparation method of imaging sensor characterized by comprising
Pixel array and its line are prepared in the silicon body region of the first SOI substrate；
The control circuit and its extraction pole of each pixel array are prepared in the silicon body region of the second SOI substrate；
Reading circuit and image processing algorithm circuit and its extraction pole are prepared in a silicon substrate；
By the first SOI substrate with pixel array and its line with the second SOI substrate have control circuit while into
Line unit closes, and the control circuit of the pixel array of the first SOI substrate and the second SOI substrate corresponds；
The silicon layer for the one side that first SOI substrate is not bonded is peeled off, so that the first SOI substrate has flat upper surface；
By the bottom surface of the second SOI substrate and the one side phase with reading circuit and image processing algorithm circuit in the silicon substrate
Bonding；
The extraction pole of second SOI substrate is connected with the extraction pole in the silicon substrate.
2. the preparation method of imaging sensor according to claim 1, which is characterized in that the body of first SOI substrate
The thickness of silicon area is less than the thickness of the silicon layer for the one side of first SOI substrate not being bonded.
3. the preparation method of imaging sensor according to claim 1, which is characterized in that the body of second SOI substrate
The thickness of silicon area is less than the thickness of the silicon layer for the one side of second SOI substrate not being bonded.
4. the preparation method of imaging sensor according to claim 1, which is characterized in that the pixel array and its line
For light sensitive diode array and its metal interconnecting layer.
5. the preparation method of imaging sensor according to claim 1, which is characterized in that the control circuit includes control
Transistor and its line.
6. the preparation method of imaging sensor according to claim 5, which is characterized in that the control transistor passes through the
One I/O circuit is drawn, around the first I/O circuit is located at below the pixel array of the first SOI substrate.
7. the preparation method of imaging sensor according to claim 6, which is characterized in that first I/O circuit passes through institute
The extraction pole for stating the second SOI substrate is drawn.
8. the preparation method of imaging sensor according to claim 1, which is characterized in that at the reading circuit and image
It include the second I/O circuit in adjustment method circuit, around the second I/O circuit is located at below the second SOI substrate；And the 2nd IO
Circuit is drawn by the extraction pole of the silicon substrate.
9. the preparation method of imaging sensor according to claim 1, which is characterized in that first SOI substrate and
It is bonded between two SOI substrates by metallic bond, second SOI substrate and the silicon substrate are bonded by Si prediction.
10. a kind of obtained imaging sensor of preparation method of imaging sensor according to claim 1, feature exist
In, comprising: the silicon substrate, second SOI substrate and first SOI substrate set gradually from the bottom up.
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