JP2006294765A - Solid state imaging device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the planarity of a first flattening layer formed in the upper layer of a first wiring layer on a semiconductor substrate, and a second flattening layer formed in an upper layer of a second wiring layer formed on the first flattening layer. <P>SOLUTION: The first wiring layer 6a is formed on the perimeter region of the light-receiving section in the first flattening layer 5a provided on the semiconductor substrate 3, and a first dummy pattern 10a is formed on the light-receiving section of the first flattening layer. Next, a second wiring layer 6b is formed on the non-light-receiving section of the second flattening layer 5b provided on the first wiring layer and the first dummy pattern, and a second dummy pattern 10b is formed on the light-receiving section of the second flattening layer. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and a manufacturing method thereof. More specifically, the present invention relates to a solid-state imaging device and a method for manufacturing the same that attempt to improve the flatness of the planarization layer by relaxing the density of the pattern on the semiconductor substrate.

  Solid-state imaging devices using charge-coupled devices (CCDs), phototransistors, and photodiodes are widely used in area sensors used in digital still cameras and digital video cameras, line sensors used in facsimiles, barcode readers, etc. As a result, it is indispensable as a device that forms the core of input devices in the information society. Such solid-state imaging devices are highly integrated, and there is a strong demand for miniaturization and high resolution. .

Here, a multilayer wiring structure in which a plurality of wiring layers are formed on a semiconductor substrate is used for high integration, and complementary metal oxide semiconductor (CMOS) technology is used as this highly integrated device structure and manufacturing process. There was a solid-state imaging device.
Specifically, like the solid-state imaging device 101 shown in FIG. 5, a transistor 104 is formed on a semiconductor substrate 103 provided with a light receiving unit 102 that performs photoelectric conversion of received light. One planarizing layer 105a is formed. In addition, a first wiring made of aluminum, copper, or the like in a region other than the light receiving portion on the first planarization layer (a region indicated by reference numeral A in FIG. 5 and hereinafter referred to as “light receiving portion peripheral region”). A layer 106a is formed, and the first wiring layer is electrically connected to the semiconductor substrate by a bonding layer 107 filled in an opening formed in the first planarization layer. Further, a second planarizing layer 105b is formed on the first wiring layer, and a second wiring layer 106b made of aluminum, copper, or the like is formed in the peripheral region of the light receiving portion on the second planarizing layer. ing. Note that a third planarizing layer 105c is formed on the second wiring layer, and a color filter layer 108 is formed on the third planarizing layer.
Here, since there are two wiring layers and three flattening layers corresponding to the wiring layers, the color filter layer is formed on the uppermost third flattening layer, but the wiring layer is flattened. A color filter is usually formed on the uppermost layer.

  In a solid-state imaging device having such a multilayer wiring structure, when forming an upper layer after forming a lower wiring layer (first wiring layer), if there is a step in the lower layer, a step is generated even when the upper layer is formed. Since the focal distance from the projection pattern at the time of pattern exposure of the upper wiring layer (second wiring layer) to the layer forming the pattern (second wiring layer) is not constant at the step, the upper wiring layer (second wiring layer) The accuracy of pattern formation at the time of forming the (2 wiring layer) is lowered. In order to avoid this, it is an important technique to maintain the flatness of the insulating film (flattening layer) between the wiring layers.

In addition, with the progress of higher integration, the occupied area per unit pixel has been reduced, and at the same time the opening area of the light receiving part has also been reduced. It is becoming difficult to generate a sufficient amount of photo-induced charges to ensure the S / N ratio due to a shortage of light. Therefore, a technique has been proposed in which an on-chip lens is formed on a wiring layer formed on a semiconductor substrate via a planarization layer so as to satisfy both high integration and high sensitivity characteristics.
Specifically, like the solid-state imaging device 101 shown in FIG. 6, the transistor 104 is formed on the semiconductor substrate 103 provided with the light receiving unit 102, and the first planarization layer 105 a and the wiring are formed on the upper layer of the semiconductor substrate. The layer 106, the second planarization layer 105b, and the color filter layer 108 are formed, and the on-chip lens 109 is formed on the color filter layer.

  Here, even if an on-chip lens having an extremely excellent shape is formed, if the flatness of the surface of the underlying flattening layer (second flattening layer) of the on-chip lens is insufficient, Application unevenness occurs in the color filter layer to be formed, and the height and optical axis of the on-chip lens are not uniform. This makes it difficult for incident light to enter the light receiving unit through a predetermined optical path assumed at the time of design. For these reasons, it is important to maintain the flatness of the flattening layer that is the base of the on-chip lens.

  As a technique for improving the surface of the flattened layer, a flattened sacrificial layer is formed by applying a solvent-free acrylic monomer or the like on the flattened layer, and this flattened sacrificial layer is etched back to improve its surface properties. Techniques for transferring to a planarization layer, techniques for performing planarization by chemical polishing (CMP), and the like have been proposed (see, for example, Patent Document 1 and Patent Document 2).

JP-A-1-279204 JP-A-9-55488

By the way, the wiring layer of a solid-state imaging device is usually made of aluminum, copper, or the like, and such a wiring layer does not transmit light and cannot be formed on a light receiving portion of a semiconductor substrate. Will be formed. Then, since the wiring layer is formed only in the peripheral area of the light receiving portion, the wiring layer pattern on the semiconductor substrate is sparsely formed, and a flattening layer is formed on the wiring layer due to the sparseness of the wiring layer pattern. A step is produced when the film is formed.
That is, since the wiring layer pattern is sparse in the light receiving part where the wiring layer is not formed, the flattening layer is thinned, and in the region around the light receiving part where the wiring layer is formed, the wiring layer pattern is dense. For this reason, the flattening layer formed becomes thick.

  Although the above-described planarization sacrificial layer coating and CMP planarization methods are effective for the planarization of subtle steps that exist locally, it is not possible to planarize a large step with a large pitch over a wide area. Have difficulty.

  The present invention has been devised in view of the above points, and it is possible to improve the flatness of a planarizing layer formed on an upper layer of a wiring layer by relaxing the density of a pattern on a semiconductor substrate. An object of the present invention is to provide a solid-state imaging device and a method for manufacturing the same.

  In order to achieve the above object, in the solid-state imaging device according to the present invention, in the solid-state imaging device having a semiconductor substrate on which a light receiving portion is formed and a wiring layer that does not transmit light formed on the semiconductor substrate, The wiring of the wiring layer is provided on the peripheral area of the light receiving part, a dummy pattern made of a light transmissive material is formed on the light receiving part, and a planarization layer is formed on the wiring layer and the dummy pattern. .

  Here, due to the dummy pattern formed on the light receiving portion where the wiring layer is not formed, the density of the pattern of the light receiving portion and the peripheral region of the light receiving portion can be reduced. That is, the wiring layer is formed only in the peripheral area of the light receiving section, and the dummy pattern is formed only in the light receiving section, thereby reducing the density of the patterns in the light receiving section and the peripheral area of the light receiving section. Note that, by forming the dummy pattern with a light transmissive material, even if the dummy pattern is formed on the light receiving portion, it does not adversely affect the light collection of the light receiving portion.

  In order to achieve the above object, in the method for manufacturing a solid-state imaging device according to the present invention, a solid substrate having a light-receiving portion formed thereon and a wiring layer formed on the semiconductor substrate that does not transmit light. In the method for manufacturing an imaging device, a step of forming wiring of the wiring layer on a light receiving portion peripheral region, a step of forming a dummy pattern made of a light-transmitting material on the light receiving portion, the wiring layer and the dummy pattern Forming a planarizing layer thereon.

  Here, by forming a dummy pattern on the light receiving portion where the wiring layer is not formed, the density of the patterns in the light receiving portion and the peripheral region of the light receiving portion can be reduced.

  In the solid-state imaging device and the manufacturing method thereof according to the present invention described above, it is possible to reduce the density of the pattern of the light receiving portion of the semiconductor substrate and the region around the light receiving portion, and to improve the flatness of the flattening layer formed on the wiring layer Can be achieved.

Hereinafter, embodiments of the present invention will be described with reference to the drawings to facilitate understanding of the present invention.
FIG. 1 is a schematic cross-sectional view for explaining an example of a solid-state imaging device to which the present invention is applied. The solid-state imaging device 1 shown here is provided with a light receiving unit 2 that performs photoelectric conversion of received light. A transistor 4 is formed on the semiconductor substrate 3, and a first planarization layer 5a is formed on the upper layer of the semiconductor substrate. In addition, a first wiring layer 6a made of aluminum, copper, or the like is formed in the peripheral region of the light receiving unit on the first planarizing layer, and the first wiring layer is an opening formed in the first planarizing layer. The semiconductor layer is electrically connected to the semiconductor substrate by the bonding layer 7 filled therein. Note that the first dummy wiring 8a made of aluminum, copper, or the like may be formed as a dummy wiring in order to reduce the density of the first wiring layer in the light receiving portion peripheral region.

  The upper layer of the first planarization layer has a film thickness of about 10 to 30 nm, has light transmission, and a light-transmitting insulating material constituting the first dummy pattern described later and processing during dry etching Material (for example, a nitride film, an oxide film, etc.) with good accuracy (when the material for forming the dummy pattern 10a layer and the material of the first insulating film 9a are etched, the dummy pattern etching efficiency is better than the first insulating film). A first insulating film 9a made of a SIOC film, a low dielectric constant film, or the like is formed. This is not necessarily required when the etching accuracy can be controlled because the etching stopper film for forming the first dummy pattern depends on the accuracy of the etching process. Further, the light receiving portion on the first insulating film has a film thickness of about 200 to 300 nm and includes a light transmitting insulating material having optical transparency and insulating properties (for example, HDP (High Density Plasma) oxide film). A first dummy pattern 10a made of the silicon oxide film (refractive index n≈1.4) or silicon nitride film (refractive index n≈2.0) or the like is formed. The upper layer of the first dummy pattern is light transmissive and has substantially the same refractive index as that of the light transmissive insulating material constituting the first dummy pattern (for example, a nitride film (refractive index n ≈2.0), a second planarization layer 5b made of an oxide film (refractive index n≈1.4), SIOC film (refractive index n≈1.6 to 1.8), other low dielectric constant film having a similar refractive index, etc.) is formed. ing.

  In addition, the second wiring layer 6b made of aluminum, copper, or the like is formed in the peripheral area of the light receiving portion on the second planarizing layer, and the density of the second wiring layer in the peripheral area of the light receiving portion is reduced. A second dummy wiring 8b made of aluminum, copper or the like is formed. Further, the upper layer of the second planarization layer has a film thickness of about 10 to 30 nm, has a light transmission property, and selects a light transmission insulating material constituting a second dummy pattern to be described later and dry etching. A second insulating film 9b made of a material having a ratio of about 10 is formed.

  In addition, a second dummy pattern 10b made of a light-transmitting insulating material having a thickness of about 200 to 300 nm and having a light transmitting property and an insulating property is formed on the light receiving portion on the second insulating film. A third planarizing layer 5c made of a material having light transmittance and substantially the same refractive index as the light transmissive insulating material constituting the second dummy pattern is formed on the upper layer of the dummy pattern, A color filter layer 11 is formed on the third planarizing layer.

Here, if the refractive index of the light transmissive insulating material constituting the dummy pattern and the material constituting the planarization layer covering the dummy pattern are significantly different, the incident light is incident on the interface between the planarization layer and the dummy pattern. It may be reflected. Therefore, it is preferable to select a light-transmissive insulating material constituting the dummy pattern having a refractive index substantially the same as that of the material constituting the planarization layer. Specifically, the light transmissive insulating material constituting the first dummy pattern and the material constituting the second planarization layer have substantially the same refractive index, and the light transmissive insulating material constituting the second dummy pattern It is preferable that the refractive index of the material constituting the third planarizing layer be substantially the same.
As an example, when the dummy pattern is composed of an HDP oxide film and an oxide film is used as the planarizing layer, the refractive index of both can be made the same with the design value.

  In this embodiment, as in the conventional solid-state imaging device, the color filter layer is formed on the third flattening layer, but by forming the dummy pattern with the material constituting the color filter layer, A color image signal can be obtained without separately forming a color filter layer.

Hereinafter, a method for manufacturing the above-described solid-state imaging device will be described. That is, an example of a method for manufacturing a solid-state imaging device to which the present invention is applied will be described.
In an example of a manufacturing method of a solid-state imaging device to which the present invention is applied, first, as shown in FIG. 2A, a transistor 4 is formed on a semiconductor substrate 3 on which a light receiving portion 2 is formed, and an upper layer of such a semiconductor substrate. Then, the first planarizing layer 5a is formed. Subsequently, the first planarization layer is opened, and the bonding layer 7 is formed by filling the opening with a conductive material. The process up to this point is the same as the conventional method for manufacturing a solid-state imaging device.

  Next, as shown in FIG. 2B, after the aluminum film 20 is formed by sputtering, the first wiring layer is used as shown in FIG. 2C by using a general-purpose photolithography technique and etching technique. 6a and first dummy wiring 8a are formed.

  Subsequently, as shown in FIG. 2D, after the first insulating film 9a is stacked by about 10 nm, the first light-transmitting insulating film 22 having optical transparency and insulating properties is stacked by about 200 nm. The first dummy pattern 10a is formed as shown in FIG. 2E by using the photolithography technique and the etching technique. Next, as shown in FIG. 2F, a second planarization layer 5b is formed, and the second planarization layer is planarized by CMP.

  Here, in order to improve the flatness of the second flattening layer, which will be described later, it is sufficient that the first dummy pattern can be formed to reduce the density of the pattern of the first wiring layer. There is no need to form the first insulating film. However, in the case where the first light-transmissive insulating film is subjected to an etching process (dry etching process or the like) in forming the first dummy pattern as in the present embodiment by forming the first insulating film, The first insulating film can serve as an etching stopper, and the first dummy pattern can be formed with high accuracy. Therefore, it is preferable to form the first insulating film that functions as an etching stopper.

  Thereafter, the second wiring layer 6b and the second dummy wiring 8b are formed in the same manner as the first wiring layer and the first dummy wiring, and the second insulating film 9b is formed in the same manner as the first insulating film. At the same time, the second dummy pattern 10b is formed in the same manner as the first dummy pattern, and the third planarizing layer 5c is formed in the same manner as the second planarizing layer. Subsequently, after the planarization process is performed on the third planarization layer by the CMP process, a color filter layer is formed on the third planarization layer to obtain a solid-state imaging device as shown in FIG. be able to.

In an example of the solid-state imaging device to which the present invention is applied, the first dummy pattern is formed, and the unevenness of the pattern of the first wiring layer is alleviated, thereby suppressing the step generated when the second planarization layer is formed. Even if a step is generated, the flatness of the second planarization layer can be ensured by the CMP process because the amount of the step is small. Similarly, by forming the second dummy pattern and reducing the density of the pattern of the second wiring layer, the step generated when the third planarization layer is formed can be suppressed. For example, a step is generated. Even so, the flatness of the third planarizing layer can be ensured by the CMP process because the step amount is small.
Therefore, even if the multilayer wiring structure is adopted, a step due to the density of the wiring layer pattern hardly occurs, and a solid-state imaging device having a high-performance multilayer wiring structure can be realized.

  FIG. 3 is a schematic cross-sectional view for explaining another example of the solid-state imaging device to which the present invention is applied. The solid-state imaging device 1 shown here is an example of the solid-state imaging device to which the present invention is applied. Similarly, the transistor 4 is formed on the semiconductor substrate 3 provided with the light receiving portion 2, and the first planarization layer 5 a is formed on the upper layer of the semiconductor substrate. In addition, a wiring layer 6 made of aluminum, copper, or the like is formed in the peripheral region of the light receiving portion on the first planarizing layer, and a dummy wiring 8 is formed.

  Further, the upper layer of the first planarization layer has a thickness of about 10 nm, has light transparency, and has a selectivity of about 10 at the time of dry etching with a light-transmissive insulating material constituting a dummy pattern described later. An insulating film 9 made of a material (for example, a nitride film, an oxide film, a SIOC film, a low dielectric constant film, etc.) is formed. Further, the light receiving portion on the insulating film has a film thickness of about 200 nm and is made of a color filter material having optical transparency and insulating properties (for example, a silicon oxide film such as an HDP oxide film or a silicon nitride film). A dummy pattern 10 is formed. The upper layer of the dummy pattern is light transmissive and has substantially the same refractive index as the light transmissive insulating material constituting the dummy pattern (for example, nitride film, oxide film, SIOC film, low dielectric constant) A second planarizing layer 5b made of a film or the like is formed, and an on-chip lens 12 is formed on the second planarizing layer.

Hereinafter, a method for manufacturing the above-described solid-state imaging device will be described. That is, another example of a method for manufacturing a solid-state imaging device to which the present invention is applied will be described.
In another example of the manufacturing method of the solid-state imaging device to which the present invention is applied, first, as shown in FIG. 4A, the transistor 4 is formed on the semiconductor substrate 3 on which the light receiving unit 2 is formed, and such a semiconductor substrate is formed. A first planarizing layer 5a is formed on the upper layer. Subsequently, the first planarization layer is opened, and the bonding layer 7 is formed by filling the opening with a conductive material. The process up to this point is the same as the conventional method for manufacturing a solid-state imaging device.

  Next, as shown in FIG. 4B, after the aluminum film 20 is formed by sputtering, the wiring layer 6 and the dummy are formed as shown in FIG. 4C by using a general-purpose photolithography technique and etching technique. A wiring 8 is formed.

  Subsequently, as shown in FIG. 4D, after the insulating film 9 is laminated by about 10 to 30 nm, the color filter film 23 having optical transparency and insulating properties is laminated by about 500 to 1000 nm, and a general-purpose photolithography technique is used. And the dummy pattern 10 is formed as shown in FIG.4 (e) using an etching technique. At present, the color filter is thick because it uses the above-mentioned film thickness, but it can also be thin under other conditions such as the color filter material. In addition, as a color filter, a pigment-type color filter, a dye-type color filter, etc. are known, and the refractive index is generally about 1.5 to 1.7.

  Next, a second planarization layer is formed, and after the planarization process of the second planarization layer is performed by a CMP process, the on-chip lens 11 is formed on the second planarization layer. A solid-state imaging device as shown in (f) can be obtained.

In another example of the solid-state imaging device to which the present invention is applied, a step formed when the second planarization layer is formed can be suppressed by forming a dummy pattern and reducing the density of the wiring layer pattern. Even if a step is generated, since the amount of the step is small, the flatness of the second planarization layer can be ensured by the CMP process.
Therefore, the problem that the height and the optical axis of the on-chip lens formed on the second planarizing layer are not uniform is eliminated, and the incident light on the surface of the second planarizing layer is assumed to be a predetermined optical path at the time of design. The problem that it becomes difficult for the light to enter the light receiving portion through is eliminated, and the optical characteristics of the product are improved.

  Further, by forming the dummy pattern with the color filter material, it is not necessary to form a color filter on the second planarization layer, and the solid state imaging device can be further miniaturized.

It is typical sectional drawing for demonstrating an example of the solid-state imaging device to which this invention is applied. It is typical sectional drawing for demonstrating an example of the manufacturing method of the solid-state imaging device to which this invention is applied. It is typical sectional drawing for demonstrating another example of the solid-state imaging device to which this invention is applied. It is typical sectional drawing for demonstrating another example of the manufacturing method of the solid-state imaging device to which this invention is applied. It is typical sectional drawing (1) for demonstrating the conventional solid-state imaging device. It is typical sectional drawing (2) for demonstrating the conventional solid-state imaging device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Solid-state imaging device 2 Light-receiving part 3 Semiconductor substrate 4 Transistor 5a 1st planarization layer 5b 2nd planarization layer 5c 3rd planarization layer 6a 1st wiring layer 6b 2nd wiring layer 7 Junction layer 8a 1st 1 dummy wiring 8b second dummy wiring 9a first insulating film 9b second insulating film 10a first dummy pattern 10b second dummy pattern 11 color filter layer 12 on-chip lens 20 aluminum film 22 first light Permeable insulating film 23 Color filter film

Claims (5)

A semiconductor substrate having a light receiving portion formed thereon;
In a solid-state imaging device having a wiring layer that does not transmit light formed on the semiconductor substrate,
The wiring of the wiring layer is provided on the light receiving portion peripheral region,
A dummy pattern made of a light transmissive material is formed on the light receiving portion,
A solid-state imaging device, wherein a planarization layer is formed on the wiring layer and the dummy pattern. The solid-state imaging device according to claim 1, wherein the dummy pattern is made of a color filter material. The solid-state imaging device according to claim 1, wherein the dummy pattern has substantially the same refractive index as the planarization layer. In a method of manufacturing a solid-state imaging device having a semiconductor substrate on which a light receiving portion is formed and a wiring layer that does not transmit light formed on the semiconductor substrate,
Forming a wiring of the wiring layer on the light receiving portion peripheral region;
Forming a dummy pattern made of a light transmissive material on the light receiving portion;
Forming a planarization layer on the wiring layer and the dummy pattern. A method for manufacturing a solid-state imaging device. 5. The solid-state imaging device according to claim 4, wherein the dummy pattern is formed by forming a light transmissive film on the light receiving portion via an insulating film and etching the light transmissive film. Production method.

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