CN106533179A - Voltage converter - Google Patents

Abstract

The invention mainly relates to an electronic device for voltage conversion. A second controller is used for sensing an output voltage or an output current of a secondary side of a transformer in real time for power switching so as to generate a transient response control signal, a coupling component is used for transmitting the control signal generated by the second controller to a first controller at a primary side, and the first controller is used for generating a first pulse signal for power switching so as to control switch-on or switch-off of a winding of the primary side.

Description

Electric pressure converter

Technical field

Present invention is primarily about the electronic installation of voltage conversion, more precisely, being the change of real-time sensing rate of doing work switching The output voltage or output current of the primary side of depressor, and the control signal of transient response is produced, and will be controlled using coupling element Signal transmission processed controls the shut-off or conducting of primary side winding to the primary side of the transformator for power switching.

Background technology

In existing electric pressure converter, none is not the voltage or electric current for gathering load-side, and will be gathered using feedback network To the feedback signal of load-side feed back to the drive component of electric pressure converter, such as typical pulse pulse width modulation mode or arteries and veins Frequency modulated mode etc. is rushed, drive component determines what is switched between conducting and shut-off in electric pressure converter using feedback signal The dutycycle of master switch, so as to sized electric pressure converter is in the number of the output voltage of load-side.There is industry this area to lead to Often skill all knows, the drive component of electric pressure converter is used for driving master switch, but drive component can't directly from bearing The load voltage that side captures real-time change is carried, instead relies on feedback network to perceive load voltage, this feedback system will necessarily Produce and postpone effect, adverse consequencess are that drive component cannot be synchronous with the holding of the variable condition of load voltage because of the time delay To switch master switch in real time, thus can cause export to load current output voltage value with load needed for actual voltage value it Between there is deviation, it is this delayed to bring potential unstability to output voltage.

The content of the invention

In one alternate embodiment, disclose a kind of electric pressure converter, the first side winding of one of transformator and one Master switch is connected between an input voltage and an earth terminal, and the secondary side winding of the transformator is connected to load and provides Between one output node and a ground reference of output voltage；And first controller, for producing the first arteries and veins Rush signal to drive master switch to switch between conducting and shut-off；One is characterized output voltage size by one second controller And/or the detecting voltage and first reference voltage of sign load current size compare, and determine which is produced by comparative result The logic state of a raw control signal；One coupling element, is connected between first, second controller, and which will control The logic state of signal is delivered to the first controller, makes the first controller judge the first pulse according to the logic state of control signal The logic state of signal.

Above-mentioned electric pressure converter, second controller first comparator inverting input input detecting voltage and in homophase Input is input into the first reference voltage；When detecting voltage is less than the first reference voltage, the high level comparative result of first comparator The rest-set flip-flop of set second controller, makes the control signal of rest-set flip-flop output be turned to high level from low level；The The ON time generator of two controllers is turned to the moment of the rising edge of high level and starts timing from control signal from low level, The moment terminated to default ON time completes timing, and when timing is completed, the signal of ON time generator output is turned over by low level Go to high level and the rest-set flip-flop that resets, make control signal low level is turned to from high level.

Above-mentioned electric pressure converter, in second controller are in series with first, between bias circuit and ground reference Two switches, wherein first, second switched fabric is in a common node, first switch is driven by control signal, and second opens Close and driven by the inversion signal of control signal；The normal phase input end of the second comparator in the first controller and the common node it Between be connected with first electric capacity for belonging to coupling element, the inverting input of the second comparator is input into the second reference voltage, the A resistance is connected between two comparator normal phase input ends and earth terminal, second capacitance connection for belonging to coupling element exists Between earth terminal and ground reference.

Above-mentioned electric pressure converter, control signal for high level when first switch conducting and second switch shut-off, bias circuit carries For voltage be applied at common node, the voltage of the second comparator normal phase input end is drawn high by coupling element and is joined to more than second Voltage is examined, the second comparator exports the first pulse signal of high level；Control signal for low level when first switch shut-off and the Current potential at the common node is clamped down on ground reference by two switch connections, drags down the second comparator positive by coupling element The voltage of input is output as low level first pulse signal to the second reference voltage, the second comparator is less than.

Above-mentioned electric pressure converter, coupling element are pulse transformer, and control signal is by a coupling in second controller The one end of capacitive transmission to the primary side winding of pulse transformer, the other end of primary side winding are connected to ground reference；The One is connected between a signal generation node and one end of the primary side winding of pulse transformer in one controller to couple Electric capacity, the opposite other end of primary side winding are connected to earth terminal, produce and control signal so as to produce node in the signal The first pulse signal that logic state is consistent.

Above-mentioned electric pressure converter, produces in the signal and the resistance and one being arranged in parallel is connected between node and earth terminal Individual diode, the negative electrode of the diode is connected to that signal produces node and anode is then connected to earth terminal.

Above-mentioned electric pressure converter, the anode of commutation diode are connected to one end of the secondary side winding of transformator, two pole of rectification The negative electrode of pipe is connected to output node, and the opposite other end of the secondary side winding of transformator is then directly connected to ground reference.

Above-mentioned electric pressure converter, one end of the secondary side winding of transformator are directly connected to output node, transformator it is secondary It is connected with a synchro switch between the opposite other end and ground reference of side winding, synchro switch is by being produced by second controller The raw driving of second pulse signal of inversion signal each other with the first pulse signal, turns off this when master switch is turned on same Step switchs and the synchro switch is connected when master switch is turned off.Or, synchro switch is still made by being produced by second controller The driving of one the second pulse signal, now controls turn off master switch in the first pulse signal (for instance in low level) In the stage, the synchro switch is also turned off by the second pulse signal (such as being also at low level) control, that is, master is opened Close and synchro switch all disconnects and enters Dead Time.

Above-mentioned electric pressure converter, in ON time generator a sampling holder is connected in master switch but synchro switch is closed The magnitude of voltage of one end being connected with synchro switch of the secondary side winding of disconnected stage, sampling and holding transformator, ON time The magnitude of voltage of sampling is converted into electric current and in ON time generator by one voltage current adapter of generator Charging capacitor is charged；One the 3rd in ON time generator switch and charging capacitor be connected in parallel on a charge node and Between earth terminal, the normal phase input end of the 3rd comparator by the control source at charge node in ON time generator and The 3rd reference voltage is input in the inverting input of the 3rd comparator；And controlled by the rising edge triggering second of control signal One monostable flipflop of device processed produces the clock signal of high level, and the clock signal is except the rising edge in control signal Moment to be low level in remaining time outside high level, so as to by clock signal in the rising edge of control signal The 3rd switch is connected to charging capacitor spark；Charging capacitor proceeds by the timing of charge period after spark, directly Voltage to charge node causes the comparative result of the 3rd comparator to be turned to high level by low level more than the 3rd reference voltage Timing just terminates, and the high level comparative result of the 3rd comparator triggering rest-set flip-flop resets, and time period of the timing is used as connecing The default ON time of logical master switch.

Above-mentioned electric pressure converter, input voltage tend to increasing when causing the magnitude of voltage sampled to increase therewith, and default ON time becomes In reduction；Or input voltage tends to reducing when causing the magnitude of voltage sampled to reduce therewith, default ON time tends to increase.

Above-mentioned electric pressure converter, the 3rd switch and charging capacitor in ON time generator are connected in the section that charges in parallel Between point and earth terminal, the positive of the control source at charge node to the 3rd comparator in ON time generator is input into End is simultaneously input into the 3rd reference voltage in inverting input；ON time generator includes a fixed current source and multiple additional electricals Stream source is respectively connected with one between the current output terminal and charge node of each additional current sources for being charged for charging capacitor Individual electrical switch；By monostable flipflop in the rising edge triggering second controller of control signal produce high level when Clock signal, the clock signal are low electricity with external remaining time for high level except the moment of the rising edge in control signal It is flat, so as to the rising edge by clock signal in control signal connects the 3rd switch to charging capacitor spark；Charging capacitor exists The timing of charge period is proceeded by after spark, until the voltage of charge node causes the 3rd ratio more than the 3rd reference voltage High level timing is turned to by low level just terminates compared with the comparative result of device, the high level comparative result triggering of the 3rd comparator Rest-set flip-flop resets, and the time period of the timing is used as the default ON time for connecting master switch.

Above-mentioned electric pressure converter, during detecting voltage pulsation, is set in the initial time detecting voltage of preset period of time less than the One reference voltage, and detecting voltage is made after the first pulse signal drives one or more switch periods of master switch default It is modulated at the end of period more than the first reference voltage；The respective frequency values of one or more clock signals in preset period of time By occur priority time sequencing, by ON time generator a frequency comparator respectively with upper frequency marginal value, lower frequency Rate marginal value is compared, and makes one of ON time generator to count when any one frequency values is more than upper frequency marginal value The binary system initial count value that device is arranged deducts 1, or makes enumerator when any one frequency values is less than lower frequency marginal value The initial count value of setting adds 1, and the completeer rear enumerator of all frequency values is calculated a total count value；Total count value More than enumerator arrange upper critical count value when define total count value be equal to upper critical count value, or total count value less than count Total count value is defined during the lower critical count value that device is arranged and is equal to lower critical count value, each in binary total count value High level or low level code element are characterized accordingly for turning on and off an electrical switch.

Above-mentioned electric pressure converter, in two preset period of time of arbitrary neighborhood, the total count value in previous preset time period More than initial count value, the quantity of the electrical switch being switched in latter preset time period is made than previous preset time period The quantity of the electrical switch being inside switched on is more, then when the default ON time in latter preset time period is less than previous default Default ON time in section；Or the total count value in previous preset time period is less than initial count value, latter is made to preset The quantity of electrical switch of the quantity of the electrical switch being switched in the time period than being switched in previous preset time period is few, Then the default ON time in latter preset time period is more than the default ON time in previous preset period of time；Or it is previous Total count value in preset time period is equal to initial count value, makes the number of electrical switch being switched in latter preset time period The quantity of electrical switch being switched in amount and previous preset time period is equal, then default in latter preset time period is led The logical time is equal to the default ON time in previous preset period of time.

Above-mentioned electric pressure converter, the transformator also including one with secondary side winding around to identical assists winding, aid in around A diode is connected between one end and one end of an auxiliary capacitor of group, assists winding and auxiliary capacitor are respective another End is connected to earth terminal, and when secondary side winding has electric current to pass through, its diode forward between auxiliary capacitor is turned on and flowed The electric current of Jing assists windings charges to the auxiliary capacitor, provides supply voltage for the first controller by auxiliary capacitor.

Above-mentioned electric pressure converter, in the first controller electrifying startup module with junction field effect transistor and One controlling switch, controlling switch are connected between the control end of junction field effect transistor and earth terminal, and controlling switch exists The voltage of auxiliary capacitor not up to one starts being to turn on during voltage level but is off when reaching and starting voltage level； Start the power up phase of incoming transport voltage in the electric pressure converter, alternating voltage is via being input to after a rectifier circuit rectifies The drain electrode of the junction field effect transistor, making from junction field effect transistor source electrode the electric current for flowing out by a diode be should Auxiliary capacitor charges, until the voltage of auxiliary capacitor reaches startup voltage level to complete electrifying startup program, electrifying startup journey Controlling switch is turned off after the completion of sequence and is charged from assists winding to the auxiliary capacitor in the stage of assists winding conducting.

Above-mentioned electric pressure converter, including potentiometer, detect the partial pressure that voltage is that potentiometer is captured to output voltage in output node Value simultaneously characterizes the size of output voltage.Including sensing resistance, sensing resistance is with load in series in output node and reference ground electricity Between position, it is the size for sensing the pressure drop at resistance two ends and characterizing the load current for flowing through load to detect voltage.

Above-mentioned electric pressure converter, including a potentiometer, by the potentiometer in output node to the electricity of the output with ripple Pressure captures a partial pressure value as feedback voltage；Also including a sensing resistance, sensing resistance is with load in series in output node And ground reference between, by the pressure drop at sensing resistance two ends as the sensing voltage for characterizing load current size；And Also include wave filter, amplifier and adder, wave filter is used for the flip-flop filtered in feedback voltage but retains alternating component Magnitude of voltage, amplifier be used for amplify sensing voltage, wave filter output category alternating component magnitude of voltage and amplifier export Sensing voltage amplification magnitude of voltage by adder addition after as the detecting voltage.

In one alternate embodiment, a kind of pulse transformer is disclosed, including one carries the one group of side arm portion for extending in parallel U-shaped the first magnetic core framework, and including the second magnetic core framework of a bar shaped, for installing the one of pulse transformer Printed circuit plate thickness and adjacent first, second through hole is provided through on individual printed circuit board (PCB), from printed circuit board (PCB) One group of lateral arm portion of the first magnetic core framework is not inserted first through hole and the second through hole by the first side, and one group of side arm portion is each Front end face be directly pressed on a surface of the second magnetic core framework in the second side of printed circuit board (PCB).

Above-mentioned pulse transformer, first side surface or the second side surface of printed circuit board (PCB) be provided with planarization first, Second spiral coil, a series of ceoncentrically wound coils in the first spiral coil are around first through hole arrangement, the second helical form A series of ceoncentrically wound coils in coil are arranged around the second through hole.On printed circuit board (PCB) between first, second through hole Region be provided with one through printed circuit plate thickness strip gap, first, second through hole is using the gap as center Line of symmetry and be symmetrically distributed in the both sides in the gap.

Above-mentioned pulse transformer, first, second spiral coil are rendered as square or circular spiral coil.Also include applying Insulating cement on a printed circuit is covered for the adhesion of first, second magnetic core framework is held on a printed circuit.

Above-mentioned pulse transformer, is internally provided with the first of the first spiral coil of multilamellar and printed circuit board (PCB) in printed circuit board (PCB) The first spiral coil alignment of side surface or the second side surface overlaps, and is arranged at multiple first spirals of printed circuit intralaminar part Shape coil is arranged around first through hole；Second end and adjacent next first of first spiral coil arbitrarily on this All of first spiral coil is thereby connected, in multiple first helical forms of concatenation by the first end interconnection of spiral coil In coil, the first end of first first spiral coil is used as one of both equivalent Same Name of Ends or equivalent different name end, end Second end of one the first spiral coil is used as the other of both equivalent Same Name of Ends or equivalent different name end.For example, upper Under in adjacent two the first spiral coils, first spiral coil and adjacent next first helical form arbitrarily on this It is provided between coil and belongs to the insulating barrier of circuit board they are spaced apart.Further for example, being located at the first side surface of printed circuit board (PCB) The first end of first first spiral coil be used as equivalent Same Name of Ends (or the different name of multiple first spiral coil series connection structures End), and it is used as multiple the positioned at second end of first spiral coil at the end of the second side surface of printed circuit board (PCB) The equivalent different name end (or Same Name of Ends) of one spiral coil series connection structure.

Above-mentioned pulse transformer, is internally provided with the first of the second spiral coil of multilamellar and printed circuit board (PCB) in printed circuit board (PCB) The second spiral coil alignment of side surface or the second side surface overlaps, and is arranged at multiple second spirals of printed circuit intralaminar part Shape coil is arranged around the second through hole；Second end and adjacent next second of second spiral coil arbitrarily on this All of second spiral coil is thereby connected, in multiple second helical forms of concatenation by the first end interconnection of spiral coil In coil, the first end of first second spiral coil is used as one of both equivalent Same Name of Ends or equivalent different name end, end Second end of one the second spiral coil is used as the other of both equivalent Same Name of Ends or equivalent different name end.For example, it is located at The first end of first second spiral coil of the first side surface of printed circuit board (PCB) is used as multiple second spiral coil tandem junctions The equivalent Same Name of Ends (or different name end) of structure, and positioned at printed circuit board (PCB) the second side surface end the first spiral coil The second end be used as multiple second spiral coil series connection structures equivalent different name end (or Same Name of Ends).

Above-mentioned pulse transformer, is also equipped with the main transformer of power stage, the first side winding of main transformer on printed circuit board (PCB) Receives input voltage and secondary side winding for load output voltage, and the first side winding of main transformer and a master are provided Switch series connection；One chip with the first controller is installed on a printed circuit, is driven for producing the first pulse signal Dynamic master switch switches between conducting and shut-off；One chip with second controller is installed on a printed circuit, by one The detecting voltage and first reference voltage of individual sign output voltage size and/or sign load current size compares, by Comparative result determines the logic state of a control signal produced by which；The wherein pulse transformer is by the logic of control signal State is delivered to the first controller, makes the first controller that the logic of the first pulse signal is judged according to the logic state of control signal State, thereby determining master switch on or off.

In one alternate embodiment, a kind of pulse transformer is disclosed, including one carries the one group of side arm portion for extending in parallel U-shaped the first magnetic core framework, and including the second magnetic core framework of a bar shaped, for installing the one of pulse transformer Printed circuit plate thickness and adjacent first, second through hole is provided through on individual printed circuit board (PCB)；And carry in first First chip in heart hole and the second chip with the second centre bore, first, second chip are installed on a printed circuit, the One centre bore and first through hole alignment overlap and the second centre bore and the second through-hole alignment overlap；From the first side of printed circuit board (PCB) One of one group of side arm portion by the first magnetic core framework simultaneously insert the first centre bore, first through hole and another one is inserted simultaneously Second centre bore, the second through hole, and the respective front end face in one group of side arm portion directly compressed in the second side of printed circuit board (PCB) On a surface of the second magnetic core framework.

Above-mentioned pulse transformer, the first chip include：First substrate, is provided with first on a surface of the first substrate Helical form is connected up：Two pins of the first substrate proximity are arranged on, the two ends of the first helical form wiring are corresponded to respectively by lead It is connected on two pins；One the first plastic-sealed body, envelopes the first substrate, the first helical form cloth, lead, wherein drawing Foot is used to accept a part for lead and is enveloped by the first plastic-sealed body, but another part of pin is extended to outside the first plastic-sealed body For being welded with the pad on printed circuit board (PCB)；First centre bore runs through the first plastic-sealed body and the first substrate, and makes first A series of form concentric spirals shape wiring grommets in helical form wiring are arranged around the first centre bore.If being additionally provided with carrying first to serve as a contrast The first substrate at bottom, then two pins of first substrate and the first chip be arranged to mutually adjacent, and first substrate is also by One plastic-sealed body is coated, and the first centre bore also also extends through first substrate.

Above-mentioned pulse transformer, is provided with the wiring of the first helical form of multilamellar on the first substrate and they is mutual each other Alignment overlaps up and down, is provided with insulating medium layer, any one first spiral shell between two neighbouring the first helical form wirings A series of form concentric spirals shape wiring grommets in rotation shape wiring are arranged around the first centre bore；An any first helical form cloth on this The wiring of all of first helical form is thereby gone here and there by the second end of line and the first end interconnection of adjacent next first helical form wiring Connection, in multiple first helical form wirings of concatenation, the first end of first first helical form wiring is used as equivalent Same Name of Ends or equivalent One of both different name ends, the second end of the first helical form wiring at end are used as equivalent Same Name of Ends or equivalent different name end The other of both.For example, in neighbouring two the first helical forms wiring, any first helical form on this Insulating medium layer is provided between wiring and adjacent next first helical form wiring to be spaced apart them.Further for example, on substrate The first end of the first helical form wiring positioned at top be used as multiple first helical forms and connect up the equivalent of series connection structure Same Name of Ends (or different name end), and the second end of the first helical form wiring positioned at the bottom on substrate is used as multiple the One helical form connects up the equivalent different name end (or Same Name of Ends) of series connection structure.

Above-mentioned pulse transformer, the second chip include：Second substrate, is provided with second on a surface of the second substrate Helical form is connected up：Two pins of the second substrate proximity are arranged on, the two ends of the second helical form wiring are corresponded to respectively by lead It is connected on two pins；One the second plastic-sealed body, envelopes the second substrate, the second helical form cloth, lead, wherein drawing Foot is used to accept a part for lead and is enveloped by the second plastic-sealed body, but another part of pin is extended to outside the second plastic-sealed body For being welded with the pad on printed circuit board (PCB)；Second centre bore runs through the second plastic-sealed body and the second substrate, and makes second A series of form concentric spirals shape wiring grommets in helical form wiring are arranged around the second centre bore.If being additionally provided with carrying second to serve as a contrast The second substrate at bottom, then two pins of second substrate and the second chip be arranged to mutually adjacent, and second substrate is also by Two plastic-sealed bodies are coated, and second centre bore also also extends through second substrate.

Above-mentioned pulse transformer, is provided with the second helical form of multilamellar on the second substrate and connects up and upper and lower between them Alignment overlaps, and is provided with insulating medium layer, any one second helical form between two neighbouring the second helical form wirings A series of form concentric spirals shape wiring grommets in wiring are arranged around the second centre bore；A second helical form wiring arbitrarily on this Second end and the first end interconnection of adjacent next second helical form wiring, thereby by all of second helical form wiring series, In multiple second helical form wirings of concatenation, the first end of first second helical form wiring is used as equivalent Same Name of Ends or equivalent different One of both name ends, the second end of the second helical form wiring at end are used as equivalent Same Name of Ends or equivalent different name end two The other of person.For example, in neighbouring two the second helical forms wiring, an any second helical form cloth on this Insulating medium layer is provided between line and adjacent next second helical form wiring to be spaced apart them.Further for example, on substrate It is used as multiple first helical forms positioned at the first end of the second helical form wiring of top and connects up the equivalent same of series connection structure Name end (or different name end), and the second end of the second helical form wiring positioned at the bottom on substrate is used as multiple second Helical form connects up the equivalent different name end (or Same Name of Ends) of series connection structure.

Above-mentioned pulse transformer, also including coating insulating cement on a printed circuit for by first, second magnetic core framework Adhesion fixing is on a printed circuit.It is connected to each other by one or more connecting portions between first chip and the second chip and is made They become coplanar integral structure, so that the first chip and the second chip synchronization are installed on printed circuit board (PCB).

In one alternate embodiment, a kind of pulse transformer, including the first and second chips are disclosed, the first chip has First magnetic core framework of one U-shaped and with the first plastic-sealed body that the first magnetic core framework is given plastic packaging, the second chip has Second magnetic core framework of one U-shaped and with the second plastic-sealed body that the second magnetic core framework is given plastic packaging；First and second magnetic Core crab each with one group of side arm portion extending in parallel, the respective front end face in one group of side arm portion of the first magnetic core framework from One lateral margin face of the first plastic-sealed body is exposed out, and the respective front end face in one group of side arm portion of the second magnetic core framework is from the second modeling One lateral margin face of envelope body is exposed out, makes the lateral margin face in the side arm portion for exposing the first magnetic core framework of the first plastic-sealed body towards the The lateral margin face in the side arm portion for exposing the second magnetic core framework of two plastic-sealed bodies, and any one side arm in the first magnetic core framework is set The front end face alignment in a side arm portion in the front end face correspondence in portion and the second magnetic core framework.

Above-mentioned pulse transformer, is connected with stage casing part, the first chip between one group of side arm portion of the first magnetic core framework The first coil winding having is wrapped on the stage casing part of the first magnetic core framework, and the two ends correspondence of first coil winding connects respectively It is connected on two pins of the first chip, pin is used to accept a part for first coil winding and is coated on by the first plastic-sealed body Interior, another part of pin is extended to outside the first plastic-sealed body for carrying out butt welding with the pad on printed circuit board (PCB).

Above-mentioned pulse transformer, is connected with stage casing part, the second chip between one group of side arm portion of the second magnetic core framework The second coil winding having is wrapped on the stage casing part of the second magnetic core framework, and the two ends correspondence of second coil winding connects respectively It is connected on two pins of the second chip, pin is used to accept a part for second coil winding and is coated on by the second plastic-sealed body Interior, another part of pin is extended to outside the second plastic-sealed body for carrying out butt welding with the pad on printed circuit board (PCB).

Above-mentioned pulse transformer, when the first and second chips are mounted side by side on printed circuit board (PCB), arrange the first plastic-sealed body and Second plastic-sealed body is spaced apart, the front end face in the side arm portion in the front end face and the second magnetic core framework in the side arm portion of the first magnetic core framework It is aligned one to one in a spaced apart manner.

Above-mentioned pulse transformer, when the first and second chips are mounted side by side on printed circuit board (PCB), arrange the first plastic-sealed body and Second plastic-sealed body is brought into close contact, and makes lateral margin face and second modeling in the side arm portion for exposing the first magnetic core framework of the first plastic-sealed body Envelope body the side arm portion for exposing the second magnetic core framework lateral margin face it is seamless applying, the front end face in the side arm portion of the first magnetic core framework and The front end face in the side arm portion in the second magnetic core framework is aligned in the way of mutual low pressure is lived one to one.

Above-mentioned pulse transformer, the first plastic-sealed body and the second plastic-sealed body are spaced apart and filling insulation in gap between them Material, the front end face in the side arm portion in the front end face and the second magnetic core framework in the side arm portion of the first magnetic core framework is with by insulant Mode spaced apart is aligned one to one.

Description of the drawings

After reading described further below and reference the following drawings, the feature and advantage of the present invention will be evident that：

Fig. 1 be the present invention relates to electric pressure converter basic framework.

Fig. 2 is the feedback network that electric pressure converter carries out feedback using TL431.

Fig. 3～4 are the schematic diagrams that coupling element is respectively adopted electric capacity and pulse transformer.

Fig. 5 is the starting module that the first driver of primary side is carried.

Fig. 6 A are the modes of the second controller capacity coupler of primary side to the first driver transmission of control signals.

Fig. 6 B are to produce first, second pulse signal as output voltage or size of current change based on Fig. 6 A.

Fig. 6 C are that the adjustable pattern of the ON time of master switch is realized in second controller based on Fig. 6 A.

Fig. 6 D are the oscillograms that ON time is adjusted based on Fig. 6 C.

Fig. 7 A are the modes of the second controller pulse transformer of primary side to the first driver transmission of control signals.

Fig. 7 B are to produce first, second pulse signal as output voltage or size of current change based on Fig. 7 A.

Fig. 7 C are to compare with reference voltage after the output result of the wave filter and amplifier being introduced into based on Fig. 7 A is superimposed again.

Fig. 8 is the synchro switch for replacing primary side with the commutation diode of primary side.

Fig. 9 is the mode of the ON time that master switch is adjusted when load lightens.

Figure 10 is to clamp down on master switch ON time that latter control signal determined by previous control signal based on Fig. 9.

Figure 11 A～11B is structure of the pulse transformer in its first embodiment.

Figure 12 A～12E is structure of the pulse transformer in its second embodiment.

Figure 13 A～13C is structure of the pulse transformer in its 3rd embodiment.

Specific embodiment

Below in conjunction with each embodiment, clearly complete elaboration, but described embodiment are carried out to technical scheme Only it is the not all embodiment with the embodiment being described herein used by explanation of the invention, based on the embodiment such as this, the skill of this area The scheme obtained on the premise of creative work is not made by art personnel belongs to protection scope of the present invention.

Referring to Fig. 1, come as a example by exchanging the flyback FLYBACK electric pressure converter (Voltage Converter) for turning direct current The spirit of the present invention is illustrated, electric pressure converter includes the power stage transformator T for voltage conversion, transformator T Mainly there is primary side or claim first side winding L_PWith with primary side or claim secondary side winding L_S, primary side winding L_P's First end such as Same Name of Ends is in input node N₁₀Place receives input voltage V_INAnd primary side winding L_PRelative the second end such as different name End is then connected with a master switch Q1 between earth terminal GND.Basic working mechanism is embodied in, and master switch Q1 is received Switch between turn-on and turn-off to the driving of the first controller 104 of primary side controller or title, when master switch Q1 is connected When, the electric current of primary side flows through primary side winding L_PWith master switch Q1 and flow to earth terminal GND, but this stage is secondary Side winding L_SFlow through without electric current, and primary side winding L_PStart to store energy；Once master switch Q1 is turned off, just The electric current of level side stops, and the polarity of all of winding is all reverse, and transformator T start to transfer energy to primary side around Group L_SSo that primary side winding L_SRunning voltage and electric current are provided to load 18 in the stage of master switch Q1 shut-offs, and In output node N₂₀Place is to output capacitance C_OUTCharge and store electric charge, in primary side winding L_SFlowing through without electric current cannot Output capacitance C when directly providing operating current to load 18_OUTCan continue to provide running voltage to load 18.At some In embodiment, transformator T also has assists winding L_AUX, assists winding L_AUXCoil winding-direction and primary side winding L_S Around to identical, that is to say, that once master switch Q1 is turned off, generation flows through assists winding L_AUXElectric current it is substantial Can be to an electric capacity C_AUXIt is charged and as the working voltage source of the first driver 104.

Referring to Fig. 1,101 rectification alternating current of commutator, bridge rectifier 101 is utilized to include the diode D11 for illustrating in advance To four diodes such as D14.The sinusoidal friendship of conventional civil power is input into typically in a pair of input lines namely bus 12,14 Stream voltage V_AC, bridge rectifier 101 make full use of the sine-shaped positive half cycle of original alternating current, negative half period this two part, Alternating current complete sinusoidal wave form is converted into same polarity to export.As sinusoidal voltage V_ACThrough bridge rectifier After 101 all wave rectification, it is rectified and is converted into the pulsating volage with alternating component, in order to further reduce pulsating volage Ripple, alternating current are obtained to filter the ripple of rectified voltage also further with a CLC mode filter after being rectified Input voltage V_IN.In FIG it is observed that the inductance L of CLC mode filters₁One end be connected to commutator 101 Diode D₁₁、D₁₃Respective negative electrode, inductance L₁Opposite other end in node N₁₀It is coupled to primary side winding L in place_P First end, an and electric capacity C of CLC wave filter₁₁It is connected to inductance L₁One end and earth terminal GND between, CLC Another electric capacity C of wave filter₁₂It is connected to inductance L₁The other end and earth terminal GND between.Bridge rectifier 101 Diode D₁₂、D₁₄Respective anode is connected to earth terminal GND, and its median generatrix 12 is connected to diode D₁₁Sun Pole and D₁₂Negative electrode and bus 14 be connected to diode D₁₃Anode and D₁₄Negative electrode.

Referring to Fig. 1, electric pressure converter also includes and primary side winding L_PA RCD clamp circuit in parallel or shut-off buffering Circuit 103.Shut-off buffer circuit 103 includes electric capacity parallel with one another and resistance, and the rwo respective one end is connected to Node N₁₀And the other end of each of which is connected to the negative electrode of a diode in shut-off buffer circuit 103, two pole The anode of pipe is then connected to primary side winding L_PThe second end.The effect of shut-off buffer circuit 103 is to limit master switch Q1 The superposition of the energy of high frequency transformer leakage inductance causes when off peak voltage and secondary coil reflected voltage, superimposed voltage are produced Raw opportunity is that, during master switch Q1 turns to shut-off by saturation, the energy in leakage inductance can be by turning off buffering electricity The diode on road 103 charges to its electric capacity, and the voltage on the electric capacity may be flushed to the folded of counter electromotive force and leakage inductance voltage Value added, the effect of electric capacity is then to fall the energy absorption of the part.In primary side winding L_PWith master switch Q1 by ending shape When state is again introduced into conducting phase, the resistance that the energy Jing on the electric capacity of buffer circuit 103 turns off buffer circuit 103 is turned off To discharge, until the voltage on electric capacity reaches the counter electromotive force before next master switch Q1 shut-offs.

Referring to Fig. 1, primary side winding L_SFirst end such as different name end be connected to output node N₂₀And primary side winding L_S's The first end of a synchro switch Q2, and second end of synchro switch Q2 are connected to if opposite second end such as Same Name of Ends It is connected to ground reference VSS.Output capacitance C_OUTIt is connected to output node N₂₀And ground reference VSS between, In output node N₂₀Place can provide output voltage V for load 18_OAs the running voltage of load 18.Should be noted It is that one is connected another one and be have to be off in limit switch Q1, Q2, the such as master switch Q1 of primary side is connecting demands The synchro switch Q2 of primary side is turned off, and vice versa, and the master switch Q1 of primary side is in the demands primary side for turning off Synchro switch Q2 be switched on.Master switch Q1 and synchro switch Q2 are each respectively provided with first, second end and a control End, they are determined between first end and the second end by the high low logic level of the signal for being applied to control end as electrical switch It is conducting or disconnection.In the normal work stage of electric pressure converter, the generation of the first controller 104 of primary side First pulse signal S₁For driving master switch Q1 switching off and on switching, the second controller of primary side between state 105 the second pulse signal S for producing₂For driving synchro switch Q2 switching off and on switching between state.Exist in addition Synchro switch Q2 is by the second pulse signal S produced by second controller 105₂The driving stage, master switch Q1 and same Dead Time (dead time) is there is also between step switch Q2, so it can also happen that in the first pulse signal S₁Control Stage the second pulse signal S of master switch Q1 shut-offs processed₂By the control situation turned off by synchro switch Q2.

Referring to Fig. 1, except primary side winding L_SOutward, extra assists winding L for arranging_AUXFirst end such as different name end It is connected to a diode D_AUXAnode, diode D_AUXNegative electrode correspondence be connected to electric capacity C_AUXOne end, and And electric capacity C_AUXThe other end be connected to earth terminal GND, and assists winding L_AUXOpposite second end such as Same Name of Ends It is connected to earth terminal GND.When master switch Q1 is turned on, primary side winding L_SWith assists winding L_AUXTheir different name end It is the circulation of negative and no current, output capacitance C with respect to Same Name of Ends_OUTPower to load 18.Conversely, in master switch Q1 During shut-off, primary side winding L_SWith assists winding L_AUXThe pole reversal, the different name end of each of which is with respect to Same Name of Ends for just And there are current flowing, primary side winding L_PEnergy be sent to primary side winding L_SWith assists winding L_AUX, in other words, The not only primary side winding L when master switch Q1 is turned off_SLoad current is provided to load 18 and returns output capacitance C_OUTCharge, Assists winding L_AUXAlso return the auxiliary capacitor C for serving as power supply_AUXCharge.In FIG, electric capacity C_AUXWhat one end kept Voltage V_CCI.e. as the supply voltage of the first controller 104.Electric capacity C_YBe be connected to primary side ground GND and time Level side can filter what the distribution capacity between primary side and primary side winding was produced with reference to the safe electric capacity between ground potential VSS Noise voltage, or say the common mode disturbances for filtering that coupled capacitor is produced between primary side and primary side winding.

Referring to Fig. 1, the 105 real time acquisition node N of second controller of primary side₂₀Place output voltage V_OChanging condition or Sensing flows through the load current I of load 18 in real time_O(i.e. output current) changing condition, and control signal SQ is thereby produced, And the first controller 104 of primary side needs the state of the high low logic level using control signal SQ further to produce First pulse signal S1 all the way, and accordingly by the first pulse signal S₁Determine that master switch Q1 is to need conducting to need for Shut-off.Because second controller 105 produces control signal SQ relative to voltage V_OOr electric current I_OChange be almost transient state Response, the first controller 104 produces the first pulse signal S1 summary responses in the change of control signal SQ, then and first Pulse signal S1 equivalent to be also real-time tracking voltage V_OOr electric current I_OChange.How it is as second controller 105 How it is using coupling unit to produce between control signal SQ, and second controller 105, the first controller 104 Part 106 is will be described in detail interacting the contents such as transmission information later in follow-up.

Referring to Fig. 2, in TL431 feedback networks, resistance R₁And R₂To output voltage V_OPartial pressure is sampled, resistance R₃ Adjust as loop gain, electric capacity C₁And C₂It is compensating electric capacity and resistance R₅It is compensation resistance.Substantially operation principle is： Output voltage V_ODuring rising, in TL431, the control end of the programmable shunt regulator diode in three ends (is missed equivalent to a voltage The reverse input end of difference amplifier) due to have input resistance R₁And R₂Partial pressure value, so also with output voltage V_OOn Rise and increase, but the negative electrode (equivalent to the outfan of voltage error amplifier) of the programmable shunt regulator diode in three ends Voltage can decline, and the negative electrode and resistance R of shunt regulator diode are connected in causing to flow through photo-coupler 17₃Between send out The primary current I of optical element_DIncrease, what is flow through in the transistor of the reception light intensity for being inconjunction with opposite side in photo-coupler 17 is defeated Go out electric current also to increase therewith, so the voltage of the feedback port COMP of primary side controller 16 declines so as to promote control The dutycycle of the pulse signal of master switch Q1 reduces, and realizes output voltage V_OReduction.Vice versa, when output electricity Pressure V_ODuring reduction, but the trend of similar each the corresponding responsive state of regulation process is conversely, finally promote control master to open The dutycycle increase of the pulse signal of Q1 is closed, output voltage V is realized_OLifting.Resistance R₄Effect be to TL431 An electric current is injected additionally, it is to avoid TL431 cisco unity malfunctions because injection current is too small, if resistance value R₃It is appropriate to select Take resistance then resistance R₄Can omit.The feedback network of Fig. 2 must reserve enough gains and phase margin and whole to ensure The stability of individual system, such as open-loop gain at least reserve 45 ° of phase margin, and the scope for allowing generally for is 45 ° to 75 °. It is clear that the greatest problem that this compensating form is present is control mode complexity and postpones effect clearly, primary side Controller 16 cannot real-time detection primary side situation, and the present invention then advocates to abandon this feedback network.

Referring to Fig. 3, the coupling element 106 in Fig. 1 specifically employs coupled capacitor, referring to Fig. 4, the coupling unit in Fig. 1 Part 106 specifically employs pulse transformer.In addition, other piezoelectric elements or optical coupling element etc. are also applied for making For coupling element 106, as long as in primary side controller or the first controller 104 and secondary side controller can be claimed or claiming the Interaction data information between two controllers 105.

Referring to Fig. 5, a safe electric capacity C between input line 12,14, is connected with_X, can be used to suppress differential mode type to disturb and filter Except high frequency spurs signal, in the economization schematic diagram, input capacitance C_INIt is connected to input node and earth terminal GND Between, input to the alternating voltage V of one group of input line 12,14_ACBy 101 rectification of bridge rectifier described above Afterwards again by input capacitance C_INIt is filtered, obtains input voltage V_IN.Electric pressure converter is by input voltage V_INThrough power Output voltage V is provided to load on one group of output lead 22,24 after the voltage conversion of level_O.Also set up in the present invention in addition There is a rectification circuit to be connected in input line 12,14, a commutation diode D of rectification circuit₂₁Anode be connected to In input line 12, another commutation diode D of rectification circuit₂₂Anode be then connected in input line 14.In addition two Pole pipe D₂₁And D₂₂Respective negative electrode interconnects and is all connected to belong to a high voltage startup element of the first controller 104 The drain electrode end of JFET, it is also possible in the drain electrode end and diode D of JFET₂₁And D₂₂Connect one between respective negative electrode Current-limiting resistance R as shown in Figure 1₂₁, the source terminal of junction field effect transistor JFET is connected to a diode D₃₁'s Anode, diode D₃₁Negative electrode be connected to the auxiliary capacitor C as power supply mentioned above_AUXUnearthed one end, And a current-limiting resistance R is connected between the grid control end and source terminal of JFET₃₁, and grid and the ground connection of JFET Controlling switch SW is connected between the GND of end₃₁, controlling switch SW₃₁First end be connected to JFET grid and Second end is connected to earth terminal GND.When input line 12,14 plugs civil power and incoming transport electricity, it is applied to control and opens Close SW₃₁Grid on switching signal CTRL start drive control switch SW₃₁Into conducting state, so controlling switch SW₃₁Grid can be connected to ground potential GND and connect the JFET of negative critical voltage, therefore produce electric current from JFET's Drain electrode flows to source electrode by diode D₃₁To electric capacity C_AUXUnearthed one end charge.Resistance R₃₁The positive pressure at two ends Drop can rise, but JFET grids decline to the voltage between source electrode, and the big appointment of the voltage between final JFET source electrodes and grid is flat Weigh in a JFET pinch-off voltage (Pinch off) magnitude of voltage, equivalent to by JFET grid Gs to source S side To actual pressure drop be equal to this pinch off value negative.When JFET is to electric capacity C_AUXCharge until the voltage V of its storage_CC When rising reaches startup voltage level, a drive control module not illustrated is triggered into working condition, drive control Module is used to produce inceptive impulse signal, and master switch Q1 is driven between turn-on and turn-off by the inceptive impulse signal Switch and start working, so far then electric pressure converter completes to start Start-Up programs.After startup program terminates, rely on Assists winding L_AUXBy the diode D for being connected to its first end_AUXTo electric capacity C_AUXIt is charged.In addition, though Fig. 1 is not illustrated, it should be appreciated that can be with assists winding L_AUXFirst end and earth terminal GND between connect A potentiometer is connect, the partial pressure that potentiometer is sampled the first controller 104 is inputed to into, so as to the first controller 104 is utilized The potentiometer detects come the current over-zero (ZCD) for implementing primary side winding or the output voltage of primary side was carried out Pressure detection.And the first end of master switch Q1 is connected to primary side winding L as drained_PSecond end, master switch Q1 The second end as an inductive reactance R is also associated between source electrode and earth terminal GND_S, flow through primary side winding L_PElectricity Flow valuve is multiplied by inductive reactance R_SResistance value just can obtain representing the voltage V of the size of current for flowing through primary side_SIf, should Voltage V_SInput to the first controller 104, the first controller 104 is by this voltage V_SIt is limited to a default restriction Voltage V_LIMITIn the range of, it is possible to the electric current of primary side is monitored and overcurrent protection is realized.

Referring to Fig. 1, master switch Q1 is made first between turn-on and turn-off after switching startup program is completed, once when master opens Close Q1 to be turned off, primary side winding L_SFirst end be different name end polarity for just, then in primary side winding L_SFirst end The voltage of acquisition can open the second controller 105 of primary side as voltage ST is started.Second controller 105 is real-time The output voltage V of monitoring primary side_OThe electric current I of load 18 is flowed through with real-time monitoring_O, specific mode for example, using by It is connected on output node N₂₀Resistance R and ground reference VSS of primary side between_D1And R_D2The potentiometer of composition comes The partial pressure value for obtaining, this partial pressure value substantially result from resistance R_D1And R_D2Node at both interconnection as one Individual feedback voltage V_FBFeed back to second controller 105.And in output node N₂₀With ground reference VSS of primary side Between be arranged in series load 18 and one sensing resistance R_C, then flow through the electric current I of load 18_OCan be with sensing resistance R_C On sensing pressure drop V_CSDivided by sensing resistance R_CResistance representing, in other words, sense pressure drop V_CSCan be used to characterize stream Jing loads 18 and sensing resistance R_CLoad current value size.

Referring to Fig. 6 A, the members of the first controller 104 and second controller 105 are illustrated, reaches mentioned above By sensing pressure drop V_CSAnd feedback voltage V_FBChange come real-time control master switch Q1 on or off purpose.The One controller 104 and second controller 105 carry out the interaction of data by coupling element 106, and coupling element 106 includes Two coupled capacitors C₂₁And C₂₂, the working mechanism of first, second controller 104,105 is discussed below.Leading Shen Bright, the first controller 104 and second controller 105 are only used for explaining as the topological structure of example in herein below The spirit of the present invention, the embodiment such as this have the variant of various equivalences, any not done based on the embodiment such as this The scheme obtained on the premise of going out creative work belongs to protection scope of the present invention.

In second controller 105, with first switch SW₄₁With a second switch SW₄₂, each of which is equal Including first end and the second end and control end, as electrical switch, the high low logic state of the signal applied by control end is determined It is being off between first end and the second end or conducting.The rwo is connected on bias circuit 105d and with reference to ground potential Between VSS, such as first switch SW₄₁First end be connected to bias circuit 105d and the second end is connected to second switch SW₄₂First end, second switch SW₄₂The second end be then connected to reference to ground potential VSS, first switch SW₄₁With Second switch SW₄₂It is controlled by control signal SQ that the Q output of a rest-set flip-flop 105a is produced, for example, controls Signal SQ is coupled to first switch SW₄₁Control end, the anti-phase letter that control signal SQ is produced by phase inverter 105e Number it is coupled to second switch SW₄₂Control end, certain control signal SQ also can also be coupled after a buffer again To first switch SW₄₁Control end.That is, first switch SW₄₁Second switch SW during connection₄₂Should turn off Or first switch SW₄₁Second switch SW during shut-off₄₂Should connect.

For second controller 105, by the resistance R of potentiometer_D1And R_D2Partial pressure captures output voltage V_OOne Individual partial pressure value is feedback voltage V_FB, by feedback voltage V_FBA first comparator being input in second controller 105 The inverting input of A1, and the in-phase input end in first comparator A1 is input into a first reference voltage V_REF.Or As replacement feedback voltage V_FBMode, by with the 18 sensing resistance R that connect of load_CCapture sign and flow through load 18 The sensing voltage V of size_CS, will sensing voltage V_CSFirst comparator A1 being input in second controller 105 it is anti-phase Input.In addition the outfan of first comparator A1 is then connected to set end S of rest-set flip-flop 105a, the second control The signal S of an ON time generator 105c outputs in device 105_ONIt is input to the reset terminal of rest-set flip-flop 105a R, and a monostable flipflop (One-Shot) or one shots 105b are then connected to the Q of rest-set flip-flop 105a Between outfan and ON time generator 105c.First switch SW is located in second controller 105₄₁Open with second Close SW₄₂To on a branch road with reference to ground potential VSS, node N₂It is first switch SW₄₁The second end and second Switch SW₄₂First end interconnection at a common node, node N₄It is connected to reference to ground potential VSS, and node N₄It is second switch SW₄₂The second end at a node.

For the first controller 104, including a second comparator A2, also with the second comparator A2 just The node N that phase input is connected₁, and with a node N for being connected to earth terminal GND₃, it is additionally provided with connection In node N₁With node N₃Between a resistance R₄₁.One second is input in the inverting input of the second comparator A2 Reference voltage V_TH.The wherein node N of the first controller 104₁With the node N of second controller 105₂Between be connected with Belong to an electric capacity C of coupling element 106₂₁, in the node N of the first controller 104₃With the section of second controller 105 Point N₄Between be connected with an electric capacity C for belonging to coupling element 106₂₂.Although the multiple twin of coupling element 106 and Ethernet Line structure is entirely different, but they have similar data transfer effect, for example node N₁Can be substantially regarded as The receiving interface RX1+ of one controller 104, node N₃The receiving interface RX2- of the first controller 104 can be regarded as, It is corresponding to be, node N₂The transmission interface TX1+ of second controller 105, node N can be substantially regarded as₄ The transmission interface TX2- of second controller 105 can be regarded as.

Produce from the angle of system discussing cooperating between the first controller 104 and second controller 105 now The first pulse signal S of control master switch Q1₁Embodiment, this needs is by Fig. 6 A and Fig. 6 B explaining.When In two controllers 105, first comparator A1 end of oppisite phase individually enters feedback voltage V_FBOr individually enter sensing voltage V_CSWhen, Wherein work as feedback voltage V_FBOr sensing voltage V_CSStart the first reference voltage V than positive terminal_REFWhen low, Ye Jitu T is betided in 6B₁The event at moment, the output result of first comparator A1 is logic high, so rest-set flip-flop 105a is set, and makes control signal SQ of outfan Q outputs jump to logic high, so as to control signal SQ connects First switch SW in logical Fig. 6 A₄₁, but signal of control signal SQ by phase inverter 105e after anti-phase is logic low Level is so second switch SW can be turned off₄₂.Due to first switch SW₄₁Second switch SW during connection₄₂Shut-off, reference Ground potential VSS current potential can be less than earth terminal GND current potentials, so from the 105 to the first controller of second controller 104 it Between transmit signal, can be along by bias circuit 105d, first switch SW₄₁, node N₂, electric capacity C₂₁, node N₁、 Resistance R₄₁, node N₃, electric capacity C₂₂, node N₄, with reference to shape on such a loop LOOP1 of ground potential VSS Into current path, the positive voltage source that now bias circuit 105d is provided starts along first switch SW by conducting₄₁With Node N₂To the electric capacity C in coupling element 106₂₁Charge, then node N₂Filling at place namely transmission interface TX1+ Piezoelectric voltage V_TX1Changing condition as shown in Figure 6B, gradually rise.And node N₁At place namely receiving interface RX1+ Charging voltage V_RX1Changing condition also as shown in Figure 6B, due to electric capacity C₂₁The voltage at two ends can not be mutated, so T₁Moment voltage V_RX1Almost there is maximum, and with electric capacity C₂₁Pole plate between voltage progressively lifting so receiving interface Voltage V at RX1+_RX1Gradually reduce.This stage is because node N₁Charging voltage at place namely receiving interface RX1+ V_RX1More than the second reference voltage V_TH, cause the output result of the second comparator A2 namely the first pulse signal S of generation₁ For logic high, so as to by the first pulse signal S₁It is coupled to the control end of master switch Q1 to connect master switch Q1.Need It should be noted that because the first pulse signal S₁Have begun to control master switch Q1, so opening in electric pressure converter Dynamic (Start-Up) stage, the drive control circuit in the first controller 104 exported for controlling master switch Q1's Inceptive impulse signal just stops producing, and starts completely by the first pulse signal S₁Master switch Q1 is controlled, only voltage Transducer restarts upper electricity and is needed using inceptive impulse signal again to start master switch Q1.

Referring to Fig. 6 B, T₁First pulse signal S caused by moment₁This state lasts till T₂At the moment, T is arrived₂Moment, The ON time T of ON time generator 105c settings_ONTerminate so that ON time generator 105c can produce one The signal S of logic high_ONThe reset terminal S of rest-set flip-flop 105a is transported to as reset signal, so that RS is touched Control signal SQ for sending out the Q output output of device 105a is turned into logic low, so as to the shut-off of control signal SQ is schemed First switch SW in 6A₄₁, but signal of control signal SQ by phase inverter 105e after anti-phase is logic high So second switch SW can be connected₄₂.Due to first switch SW₄₁Second switch SW during shut-off₄₂Connect, from the second control 105 to the first controller of device processed 104, can be along by node N₂, second switch SW₄₂, node N₄, electric capacity C₂₂、 Node N₃, resistance R₄₁, node N₁, electric capacity C₂₁Return to node N₂Form the loop LOOP2, electric capacity C of closure₂₁ With electric capacity C₂₂A part of electric charge of charge storage can offset neutralization and by resistance R₄₁Consume.So from T₂Moment, Electric capacity C₂₁Release electric charge causes node N₂Charging voltage V at place namely transmission interface TX1+_TX1Progressively reduce, T₂Moment is because electric capacity C₂₁Voltage can not be mutated so causing node N₁Voltage at place namely receiving interface RX1+ V_RX1The negative value of of short duration appearance is pulled down to, with electric capacity C₂₁With electric capacity C₂₂Release electric charge causes at receiving interface RX1+ Voltage V_RX1It is close to T₃The zero potential of moment static state, and node N₂Voltage V at place namely transmission interface TX1+_TX1 Also close to T₃The zero potential of moment static state, this stage is due to node N₁Voltage V at place namely receiving interface RX1+_RX1 Less than the second reference voltage V for being for example close to zero potential_TH, cause the output result of the second comparator A2 namely the of generation One pulse signal S₁For logic low, so as to by the first pulse signal S₁To turn off master switch Q1.See from Fig. 6 B Examine, T₁Moment is to T₂ON time T between moment_ONBe master switch Q1 connect stage, T₂Moment is to T₃Moment it Between turn-off time T_OFFIt is the stage of master switch Q1 shut-offs, referring back to Fig. 1, has handed over the second pulse signal above S₂It is the first pulse signal S₁Or perhaps the inversion signal of control signal SQ, so the second pulse signal S₂In conducting Time T_ONT between when off_OFFLogic state and the first pulse signal S₁Conversely, can be by second controller part 105 producing second pulse signal S₂For controlling the synchro switch Q2 of primary side.

In the stage of master switch Q1 conductings, primary side current flows through primary side winding L_PEnergy storage is carried out, now due to synchronization Switch Q2 is turned off so primary side winding L_SPass through without electric current, output capacitance C_OUTPower to load 18.Leading In the stage of switch Q1 shut-offs, primary side current is reduced to zero primary side winding L_PRelease energy, primary side winding L_PEnergy Amount is sent to primary side winding L_SWith assists winding L_AUX, now synchro switch Q2 conductings are so primary side winding L_SAnd There is electric current to pass through in synchro switch Q2, primary side winding L_SLoad current is provided to load 18 and returns output capacitance C_OUT Charge, assists winding L_AUXAlso to the electric capacity C for serving as power supply_AUXCharge.Determining with regard to ON time generator 105c should ON time T_ONThe mode that time delay is measured, with reference to Fig. 6 A and Fig. 6 B, for example, can be exported by rest-set flip-flop 105a Control signal SQ is in T₁The rising edge Rising-edge at moment is held to trigger monostable flipflop 105b and produce one Other narrow clock pulses CLK1 of continuous nanosecond, it should be noted that narrow clock pulses CLK1 is only in control signal The rising edge of SQ is high level, and other times are low levels.Clock pulses CLK1 notifies ON time generator 105c Start timing, ON time generator 105c arrives default ON time T just in timing_ONThe moment of end, by turning on Time generator 105c sends a high level signal S_ONCome the rest-set flip-flop 105a that resets, therefore this control model The control model of constant on-time Constantly On Time is may be considered substantially, the invention essence based on the present invention God, in each switch periods, default constant on-time T_ONLasting duration can also adjust, for example we can be with Design satisfactory minimum constant on-time T_ON-MINOr maximum constant ON time T_ON-MAX。

Referring to Fig. 6 C, it is a kind of optional embodiment based on Fig. 6 A.In view of master switch Q1 switching frequency f with Input voltage V_INIncrease and reduce or with input voltage V_INReduce and increase, and frequency f is with ON time T_ONIncrease Reduce or with ON time T greatly_ONReduce and increase, if the too small magnetic cores that may result in transformator T of switching frequency f Magnetic core supersaturation, such as input voltage V caused and to return to the starting point of hysteresis curve in magnetic flux there is_INIncrease causes out Close that frequency f is too small may result in transformator T saturations, once now magnetic core cannot bear voltage and be easy for burning.In the enforcement In example, we will overcome this problem.Master switch Q1 connect but synchro switch Q2 turn off when, primary side around Group L_SPass through without electric current, but can be from primary side winding L_SThe second end such as Same Name of Ends and synchro switch Q2 first Voltage sample amount V of this node is captured at one node of end interconnection_SAM, and primary side winding L_SThe second end at this The voltage V of section_SAMPrimary side winding L is equal to about_SNumber of turn NS than upper primary side winding L_PNumber of turn NP again will Ratio NS/NP is multiplied by input voltage V_INResulting result of calculation, that is to say, that voltage V_SAMWith input voltage V_IN's Size has relatedness.Based on this relatedness, ON time generator 105c perceives voltage V_SAMSize, mat This produces suitable ON time T as foundation_ONTo suppress switching frequency f to be reduced to the magnetic caused by abnormality Core saturation.As shown in Fig. 6 C, 6D, pressure drop V is sensed_CSOr feedback voltage V_FBThan the first reference voltage V_REFIt is little just First comparator A1 can be caused to export set end S of the high level to rest-set flip-flop 105a, the Q of rest-set flip-flop 105a By low level upset for high level, control signal SQ is exported control signal SQ that outfan is produced to monostable flipflop 105b will promote monostable flipflop 105b when control signal SQ is overturn the rising edge for high level by low level Carve and produce clock signal clk 1.ON time generator 105c includes sampling holder (S/H) 105c-1 and Individual voltage current adapter 105c-2, also including one the 3rd switch SW₅₁And an electric capacity C_T, wherein sampling keeps The input of device 105c-1 is connected to primary side winding L_SThe second end such as Same Name of Ends, the output of sampling holder 105c-1 End is connected to the voltage input end of voltage current adapter 105c-2, supply voltage V_DDFor voltage current adapter 105c-2 Running voltage, current output terminal and the electric capacity C of voltage current adapter 105c-2 are provided_TOne end be connected to node N_T, Electric capacity C_TOpposite other end be connected to earth terminal GND.3rd switch SW₅₁First end be connected to node N_TAnd the Two ends are connected to earth terminal GND so that the 3rd switch SW₅₁With electric capacity C_TIt is that relation is in parallel, the 3rd switch SW₅₁ The clock signal clks 1 that produce of control end input monostable flipflop 105b.ON time generator 105c also includes The normal phase input end of the 3rd comparator A3 is connected to electric capacity C by one the 3rd comparator A3_TOne end namely charge node N_T, and the inverting input in the 3rd comparator A3 is input into a 3rd reference voltage V_P。

Referring to Fig. 6 C, ON time generator 105c adjusts ON time T_ONWorking mechanism be, using sampling protect Holder 105c-1 sampling primary side winding L_SThe second end such as Same Name of Ends voltage V_SAM, its sampling opportunity e.g. may be used To be the time of master switch Q1 conductings and synchro switch Q2 shut-offs, if input voltage V_INMore big then sampling holder The magnitude of voltage that 105c-1 keeps is bigger, causes the electric current of voltage current adapter 105c-2 outputs bigger.Vice versa, Input voltage V_INThe magnitude of voltage that more little then sampling holder 105c-1 keeps is less, causes voltage current adapter The electric current of 105c-2 outputs is less.Due to switching SW for driving the 3rd₅₁Clock signal clk 1 only RS touch The moment for sending out the rising edge of control signal SQ that device 105a is produced is high level, and other times are low level, so that control The switch SW of moment the 3rd of the rising edge of signal SQ processed₅₁Connected by transient state, then electric capacity C_TIt is stored in its one end namely section Point N_TThe electric charge at place switchs SW the 3rd₅₁This moment being switched on discharges, so the outfan of the 3rd comparator A3 Can produce and be output as low level signal S at this moment_ON.In figure 6d, the moment of the rising edge of control signal SQ, It is preset period of time T_SETThe moment of beginning.The rising edge This move of control signal SQ terminate after clock signal CLK1 is turned to low level again, as long as the 3rd switch SW₅₁It is disconnected after connection, electric capacity C_TReuse voltage x current The electric current of transducer 105c-2 outputs is charged.Once electric capacity C_TIn conducting period T_ONInside persistently charge, in conducting Period T_ONShut-off period T after end_OFFNode N is made inside_TThe voltage at place starts than the 3rd reference voltage V_PGreatly.Finally As a result, making the signal S that the outfan of the 3rd comparator A3 is produced_ONBy conducting period T_ONInterior low level is lifted to Shut-off period T_OFFInterior high level, and signal S_ONThe reset terminal R of rest-set flip-flop 105a is imported into again, so high The signal S of level_ONCan be resetted rest-set flip-flop 105a, allow control signal SQ that its Q output is produced by turning on the period T_ONInterior high level drops into shut-off period T_OFFInterior low level.Control signal SQ section T when off_OFFIt is interior lasting For low level, until shut-off period T_OFFLow level is extended for after end also, unless sensed pressure drop V next time_CSOr it is anti- Feedthrough voltage V_FBThan the first reference voltage V_REFLittle, first comparator A1 sends high level again and carrys out set rest-set flip-flop 105a exports high level.And the signal S that the outfan of the 3rd comparator A3 is produced_ONSection T when off_OFFInside it is continuously High level, until shut-off period T_OFFHigh level is extended for after end also, unless until next secondary control signal SQ has There is rising edge, so that clock signal clk 1 high level occurs to connect the 3rd switch SW₅₁, so that allow electric capacity C_T's Node N_TSpark, the 3rd comparator A3 just can produce low level signal S again_ON。

Referring to Fig. 6 C, input voltage V_INThe magnitude of voltage that more big then sampling holder 105c-1 keeps is also bigger, and causes The current value of voltage current adapter 105c-2 outputs is bigger, so as to reduce the charging interval, allows electric capacity C quickly_TOne end Node N_TThe voltage at place is more than the 3rd reference voltage V_P, short time interval T is inside contracted equivalent in whole switch periods_ONDuration, And period T_ONInterior control signal SQ be high level and be master switch Q1 turn-on time, so work as input voltage V_IN ON time T when bigger_ONBut it is shortened, corresponds to therewith, period T_OFFInterior control signal SQ is low level and is that master opens Close the turn-off time of Q1.In other words, although input voltage V_INIncrease and be intended to reduction switching frequency f, but turn-on time T_ONThe effect being shortened is the reduction degree for inhibiting switching frequency f.Vice versa, once input voltage V_INIt is less, The magnitude of voltage that then sampling holder 105c-1 keeps is less, the current value for causing voltage current adapter 105c-2 to export It is less, and delay the charging interval, electric capacity C is just allowed with slow speed finally_TThe node N of one end_TThe voltage at place surpasses Cross the 3rd reference voltage V_P, equivalent to being suitably to extend period T in whole switch periods_ONTime span, institute With input voltage V_INON time T that is less and causing master switch_ONBut it is extended.In other words, although input voltage V_IN Reduction be intended to increase switching frequency f, but turn-on time T_ONThe effect being extended is the increase journey for inhibiting switching frequency f Degree.Obviously, the Relative steady-state of the guarantee switching frequency f that this embodiment of the invention can be splendid.

Such as under discontinuous DCM patterns switching frequency f=(2 × I_O×L×V_O)÷{(V_IN)²×(T_ON)², wherein L It is the equivalent inductance value of transformator T, according to scheme provided above of the invention, it is clear that either input voltage V_INReduce also It is to increase, (the V in functional relationship_IN)²×(T_ON)²The change yardstick of this value of calculation is simultaneously little, can suppress Variable quantity/the amplitude of switching frequency f is damaged into saturation so as to avoid transformator T.

Referring to Fig. 7 A, than the embodiment of Fig. 6 A, topmost difference is the component type for changing coupling element 106 And others feature is then essentially identical.Coupling element 106 is pulse transformer PT, wherein the circuit of second controller 105 It is hereinbefore interpreted with the mode for producing control signal SQ, repeat no more.In this embodiment, the pulse transforming Device PT has as the transmission medium that data signal interaction is carried out between the first controller 104 and second controller 105 Primary side claims once to survey winding L_PT1With primary side or title secondary side winding L_PT2, primary side winding L_PT1It is connected to second Controller 105, primary side winding L_PT2It is connected to the first controller 104.Primary side winding L_PT1The first end for possessing is such as Same Name of Ends is used for receiving control signal SQ produced by rest-set flip-flop 105a and reference is coupled at the second end such as different name end Current potential VSS, primary side winding L_PT2The first end for possessing such as Same Name of Ends can be produced for driving the first of master switch Q1 Pulse signal S₁And second end for example different name end be used for be coupled to earth terminal GND.Although in primary side winding L_PT1 One end directly inputs control signal SQ, and by primary side winding L_PT2First end output result directly as the first pulse Signal S₁Be in theory it is feasible, but in order to ensure that signal does not pass mistake, the invention provides the embodiment of Fig. 7 A. Control signal SQ can be for transmission to the input to a buffer A4, and the outfan of buffer A4 is node N₅Place and Primary side winding L_PT1First end between connect an electric capacity C₅₂, primary side winding L_PT1The second end in node N₇Place It is with reference to ground potential VSS to be connected to a relatively low current potential or say.Primary side winding L_PT2First end and one be used for it is defeated Go out the first pulse signal S₁Signal produce node N_SBetween connect an electric capacity C₅₁, primary side winding L_PT2The second end In a node N₆Place is connected to earth terminal GND.And it is optional by a diode D₅₁Negative electrode be connected to node N_SAnd anode is in node N₆Place is connected to earth terminal GND, and optionally can be with node N_SWith node N₆Between One resistance R of connection₅₁.The working mechanism of pulse transformer PT is embodied in, electric capacity C₅₂Isolated DC electricity, when control letter Number SQ upset for high level when give electric capacity C₅₂Charge, also can lifting primary side winding L_PT1First end such as Same Name of Ends electricity Position.If Fig. 7 B are positioned at primary side winding L_PT1The voltage V of the transmission interface TX1+ at the first end node_TX1It is rough Waveform, primary side winding L_PT1It is considered as transmission interface TX2- at the node at the second end, pulse transformer PT will control letter Number SQ is delivered to primary side winding L_PT2, primary side winding L_PT2First end such as Same Name of Ends current potential also lifting, such as scheme 7B positioned at primary side winding L_PT2The voltage V of the receiving interface RX1+ at the first end node_RX1Rough waveform, it is secondary Level side winding L_PT2It is considered as receiving interface RX2- at the node at the second end.Due to electric capacity C during being somebody's turn to do₅₁Coupling Also can be by node N_SCurrent potential synchronization lifting get up, if adopt Schottky diode D₅₁Then diode D₅₁Clamp effect Node N should be also possible that_SCurrent potential increase rapidly, so as in node N_SFirst pulse signal S of place's output high level₁。 In contrast, once the electric capacity C when the upset of control signal SQ is low level₅₂Primary side winding L will be passed through_PT1 Electric discharge, electric capacity C₅₁Also by primary side winding L_PT2With resistance R₅₁Electric discharge so that signal produces node N_SCurrent potential it is fast Speed is fallen, so as to produce node N in signal_SPlace produces low level first pulse signal S₁, the first pulse signal S₁With The logic state upset of control signal SQ and synchronously change.Second pulse signal S₂It is the first pulse signal S₁It is anti-phase Signal, oscillogram such as Fig. 7 B.

Referring to Fig. 7 C, the embodiment is slightly distinguished with Fig. 7 A, in the embodiment of Fig. 7 A in second controller 105 The inverting input of first comparator A1 has been transfused to feedback voltage V_FBOr sensing voltage V_CSOne of them, but Fig. 7 C The output of embodiment median filter 105g be added by adder 105i with the output of amplifier 105h after be re-fed into To the inverting input of first comparator A1.Output node N in FIG₂₀Place or will be described in detail later The output node N of embodiment as shown in Figure 8₂₀The waveform of the actual ripple voltage Ripple at place is with alternating component and directly Stream composition, the voltage level of the average voltage level of ripple voltage equivalent to flip-flop, and total ripple voltage deduct direct current into The magnitude of voltage for dividing substantially is equal to the magnitude of voltage of alternating component.Feedback voltage V_FBBecause being output node N₂₀What place captured Partial pressure value, so which is substantially also a partial pressure of actual ripple voltage.Voltage V is sensed in addition_CSWhat is characterized is load electricity Stream I_OSize, present the load current I of DC and AC characteristics_OThe exchange that the DC current component for carrying is carried much larger than it Current component, so sensing voltage V_CSAnd alternating current-direct current signal, voltage of its average voltage level equal to its flip-flop Value.In fig. 7 c, actual ripple voltage is transported to a wave filter 105g, and the wave filter is used to filter actual ripple The flip-flop of voltage and only retain and output AC composition, it is believed that wave filter 105g is by feedback voltage V_FBIt is total Magnitude of voltage deducts the magnitude of voltage that the magnitude of voltage of flip-flop in the middle of it just obtains the alternating component in the middle of it.In fig. 7 c, bear Carry electric current I_OIn sensing resistance R_CThe pressure drop of upper generation senses voltage V_CSAn amplifier 105h is transported to, is sensed Voltage V_CSExport after being amplified by amplifier 105h.Wave filter 105g will filter feedback voltage V_FBFlip-flop and obtain The signal output of the alternating component for arriving will sense voltage V to adder 105i, amplifier 105h_CSProcess amplify with friendship The signal output of stream composition and flip-flop to adder 105i, the signal that wave filter 105g export by adder 105i with The signal of amplifier 105h outputs is re-fed into the inverting input of first comparator A1 after being added.The embodiment of Fig. 7 C Except the inverting input of first comparator A1 is not direct feedback voltage V_FBOr sensing voltage V_CSOutside, it is other It is identical with Fig. 7 A.And signal and the letter of amplifier 105h outputs that wave filter 105g is exported by adder 105i This scheme of inverting input of first comparator A1 is input to after number being added, replaces the anti-phase defeated of first comparator A1 Enter the feedback voltage V at end_FBOr sensing voltage V_CS, apply also for the embodiment of Fig. 6 A and Fig. 6 C.

Referring to Fig. 8, the embodiment is primary side winding L with the maximum difference of Fig. 1_SFirst end such as different name end pass through one Commutation diode D_RECIt is connected to output node N₂₀.And the synchro switch Q2 in Fig. 1 can also be abandoned, now Primary side winding L_SThe second end such as Same Name of Ends may be coupled directly to reference to ground potential VSS.Commutation diode D_REC's Anode is connected to primary side winding L_SFirst end and negative electrode is connected to output node N₂₀, starting voltage ST can be from rectification Diode D_RECNegative electrode at capture.Without the need for producing the second pulse signal S again if synchro switch Q2 is cancelled₂, remove Outside this, the running working mechanism of Fig. 8 is identical with Fig. 1, and it will not go into details here.

In electric pressure converter, if load 18 lightens or is unloaded, load current I_OWill significantly reduce, this is equally The switching frequency f of master switch Q1 can be caused to reduce, the underloading Light load situations of load 18 described herein or For unloaded Empty load are relative its heavily loaded Heavy load situations.And switching frequency f with electric pressure converter is No entrance audio zone is closely bound up, if switching frequency f is too low to produce unwanted oscillation, if such as electrical equipment user is heard The howling that transformator sends may be exactly that switching frequency f is reduced to 20Hz or so.

Referring to Fig. 9, the sound that the adaptive certainly solution switching frequency f of electric pressure converter reduces causing will be introduced in this embodiment Frequency sense of discomfort.The either embodiment of Fig. 6 A or Fig. 7 A or Fig. 7 C, by feedback voltage V_FBOr sensing voltage V_CS Or one of the signal of adder 105i output is considered as detection signal DE, therefore detection signal DE can be used for sign and carry The output voltage V of supply load 18_OAnd/or load current I_OReal-time size cases.This detection signal DE is input to The inverting input of one comparator A1, the first reference voltage level V_REFThe normal phase input end of first comparator A1 is input to, When detection signal DE is less than the first reference voltage level V_REFWhen, the high level of first comparator A1 output makes rest-set flip-flop The set end S set of 105a, rest-set flip-flop 105a start export high level control signal SQ, when closed between produce Raw device 105c produces the signal S of high level_ONRest-set flip-flop 105a when being transported to the reset terminal R of rest-set flip-flop 105a Start to export low level control signal SQ, this has hereinbefore been discussed in detail, and it will not go into details.In the embodiment of Fig. 9 In, a part of component of electric pressure converter is only illustrated, while also specially illustrating ON time generator 105c's A kind of optional but nonessential embodiment.In figure 9 and in figure 10, once working as detection signal DE is less than the first reference voltage Value V_REF, time trigger monostable flipflop 105b of rising edge of control signal SQ from low transition to high level Go out clock signal clk.In the embodiment in figure 10, the first reference voltage level V is less than with detection signal DE_REFTwo Illustrated as a example by individual adjacent time interval, for example, a first period TIME1 there occurs detection signal DE (for example certain One detection signal DE1) less than the first reference voltage level V_REFSituation, this moment electric pressure converter can by produce control Signal SQ1 processed connects master switch Q1 to modulate increase output voltage V_OAnd/or load current I_O, so as to adjust by voltage System causes the first period TIME1 end point detection signal DE to be revert to more than the first reference voltage level V just_REFState, There occurs that detection signal DE (such as some detection signal DE2) was low again again in a second period TIME2 later In the first reference voltage level V_REFSituation, electric pressure converter need again by produce control signal SQ2 control connect master Switch Q1 increases output voltage V to modulate_OAnd/or load current I_O, Jing voltage modulateds cause the second period TIME2 tie Spot detection signal DE is revert to just more than the first reference voltage level V_REF, so circulate.

Referring to Figure 10, detection signal DE1 is less than the first reference voltage level V in the first period TIME1_REF, first Period TIME1 initial time, the high level comparative result of first comparator A1 make rest-set flip-flop 105a set produce height Control signal SQ1 of level, at this moment, control signal SQ1 is turned to the rising edge of high level by low level before So that monostable flipflop 105b coverlets fire out the burst pulse namely clock signal CKL1 of high level, the process can be tied Close Fig. 6 A and Fig. 7 A or Fig. 7 C to understand.The clock signal CKL1 triggering and conducting produced by monostable flipflop 105b Time generator 105c proceeds by ON time T_ON1Timing, master switch Q1 connect ON time T_ON1It is interior The signal S that 3rd comparator A3 sends_ON1It is continuously low level.To ON time T_ON1After end, ON time is produced The 3rd comparator A3 in device 105c sends the signal S of high level_ON1As reset signal, rest-set flip-flop 105a is allowed Reset and make control signal SQ1 to be turned to low level state.In the first period TIME1, master switch Q1 can have many Individual switch periods and the quantity that illustrates incessantly, preset period of time T_SET- A is opened from the start time point of the first period TIME1 Beginning timing, through one or more switch periods until in preset period of time T_SETAt the end of-A, detecting voltage DE according to Expected imagination is greater than the first reference voltage V_REF, now control signal SQ1 is low level, and the moment again because The narrow clock signal of the follow-up next high level of clock signal clk 1 does not also occur, so electric capacity C_TAlso no transient state is put Electricity, then the signal S that the 3rd comparator A3 is exported_ON1Maintain high level.

Referring to Figure 10, after the first period TIME1 terminates, due to the voltage modulated effect of electric pressure converter so that detect Survey signal DE to revert to more than the first reference voltage level V_REFState, now the comparative result of first comparator A1 is for low Level.After certain interval of time, later in a second period TIME2 detection signal DE2 again below the first reference electricity Pressure value V_REF, in the second period TIME2 initial time, the high level comparative result of first comparator A1 triggers RS Device 105a set produces control signal SQ2 of high level, and at this moment, control signal SQ2 is turned over by low level before Go to the rising edge of high level so that the burst pulse namely clock that monostable flipflop 105b is clicked and sent high level is believed Number CKL2.Electric capacity C is triggered by clock signal CKL2 that monostable flipflop 105b is produced_TDischarge and be less than the 3rd reference Voltage V_P, now ON time generator 105c proceed by ON time T_ON2Timing, master switch Q1 connect ON time T_ON2The signal S that interior 3rd comparator A3 sends_ON2It is continuously low level.To ON time T_ON2Terminate Afterwards, electric capacity C_TCharge to more than the 3rd reference voltage V_P, the 3rd comparator A3 in ON time generator 105c Go out the signal S of high level_ON2As reset signal, rest-set flip-flop 105a is allowed to reset and be turned to control signal SQ2 Low level state.Equally in the second period TIME2, master switch Q1 can also have the multiple switch cycle and illustrate incessantly Quantity, preset period of time T_SET- B starts timing from the start time point of the second period TIME2, through one or many Individual switch periods are until in preset period of time T_SETAt the end of-B, detect voltage DE it is anticipated that imagination can be more than first Reference voltage V_REFTo meet loading demand, now control signal SQ2 is low level, and the moment is again because clock is believed The narrow clock signal of number CLK2 follow-up next high level does not also occur, so electric capacity C_TAlso no spark, then The signal S of the 3rd comparator A3 outputs_ON2Maintain high level.

Referring to Fig. 9, hereafter by with adjacent previous preset period of time T_SET- A and latter preset period of time T_SET- B is occurred Feedback voltage V_FBOr sensing voltage V_CSOr the output signal of adder 105i is less than the first reference voltage V_REFSituation As a example by, be illustrated in switching frequency f it is too low when, the present invention be how to avoid transformator T utter long and high-pitched sounds and directing switch frequency f take off From audio zone.Wherein feedback voltage V_FBOr sensing voltage V_CSOr the output signal of adder 105i one of is arbitrarily considered as Detection signal DE.In figure 9 and in figure 10, previous preset period of time T_SETIn-A, the control signal SQ1 moment produces Clock signal clk 1 has frequency value F, because the quantity of the high level burst pulse of time period clock signal CLK1 can Can more than once, so frequency value F is likely to there is the situation of one or more.In fig .9, there is provided one Clock generator 113 at least include agitator 113a and frequency divider 113b, agitator 113a produce oscillator signal and Export and give frequency divider 113b, and frequency divider 113b then changes the frequency of oscillator signal to provide upper frequency marginal value F_H With lower frequency marginal value F_LExport to frequency comparator 114 as reference frequency, thereby the frequency comparator 114 can The frequency value F that the clock signal clk 1 that control signal SQ1 rising edge is triggered is had and upper frequency marginal value F_HWith Lower frequency marginal value F_LIt is compared.Enumerator 115 carries totalizer and subtraction count device, and enumerator 115 Initial count value can assignment in advance, be more than upper frequency marginal value F in some frequency value F_HTime limit counter 115 Subtract 1 on the basis of the counting initial value being assigned, lower frequency marginal value F is less than in some frequency value F_LTime limit devises a stratagem Number devices 115 Jia 1 on the basis of the counting initial value being assigned, as being carried out plus computing is also carried out subtracting computing entirely by frequently The comparative result of rate comparator 114 determines that comparative result is transferred to enumerator 115, and enumerator 115 is held by the result The operational rule of row previous definition.In preset period of time T_SETIn-A, according to each high level narrow pulse clock signal CLK1 Corresponding frequency value F size and reference frequency comparison result so that or enumerator 115 sequentially plus 1 Subtract 1, and be based on the corresponding species number of frequency value F (for example 5 different frequency values) and hold enumerator 115 The counts of capable same number (for example counting 5 times), final enumerator 115 can produce a total count value.This Outer enumerator 115 has also been defined count condition, namely limits under upper a critical count value and one to enumerator 115 Critical count value, is equal to upper critical count value once total count value is defined if when total count value exceedes upper critical count value, or Person then defines total count value equal to lower critical count value when total count value is less than lower critical count value.Or when total count value is equal to When one of upper critical count value or lower critical count value, total count value is defined without the need for changing.

Understand for convenience, it is assumed that in exemplary but non-limiting embodiment, in preset period of time T_SETIt is several high in-A Level narrow pulse clock signal CLK1 correspondences are with five kinds of different frequencies, it is also possible to think the frequency of clock signal clk 1 The total number of value F is five.In this case, enumerator 115 counts initial value to be presented as two binary As a example by code element BIT [00], lower critical count value is defined as binary code element BIT [00] of two, and upper critical count value It is defined as binary code element BIT [11] of two.When the total number of the frequency value F of clock signal clk 1 is five, often Individual frequency values successively keep up with frequency critical value F according to the timing node for occurring_HWith lower frequency marginal value F_LIt is compared, by To perform, compare the result hypothesis for obtaining in front and back is frequency comparator 114 respectively：First frequency values faces less than lower frequency Dividing value F_L, second frequency values be higher than upper frequency marginal value F_H, the 3rd frequency values be less than lower frequency marginal value F_L, the 4th Individual frequency values are higher than upper frequency marginal value F_H, the 5th frequency values be less than lower frequency marginal value F_L, according to meter defined above Number rule, enumerator 115 are counted to the number of several high level narrow pulse clock signal CLK1, and enumerator 115 is in meter Before and after on the basis of number initial value BIT [00], the counting step of five execution is embodied in：First frequency values faces less than lower frequency Dividing value F_LWhen frequency comparator 114 comparative result flip-flop number 115 up counter effectively and Jia 1, second Frequency values are higher than upper frequency marginal value F_HWhen frequency comparator 114 comparative result flip-flop number 115 subtraction count device Effectively and subtract 1, the 3rd frequency values are less than lower frequency marginal value F_LWhen frequency comparator 114 comparative result flip-flop number The up counter of device 115 effectively and Jia 1, the 4th frequency values are higher than upper frequency marginal value F_HWhen frequency comparator 114 Comparative result flip-flop number 115 subtraction count device effectively and subtract 1, the 5th frequency values are less than lower frequency marginal value F_LWhen frequency comparator 114 the up counter of comparative result flip-flop number 115 effectively and Jia 1, so counting just It is BIT [01] that initial value BIT [00] meets two to enter a total count value obtained after adding up to five times to count before and after sequentially.In addition In one example, it is assumed that counting initial value BIT [00] mentioned above and lower critical count value BIT [00] and upper critical count value BIT [11] is constant, but the scope of five frequency values there occurs change, and enumerator 115 is counting the base of initial value BIT [00] Before and after on plinth, the counting step of five execution is embodied in：First frequency values is higher than upper frequency marginal value F_HWhen frequency comparator The subtraction count device of 114 comparative result flip-flop number 115 is effective and subtracts 1, second frequency values is higher than that upper frequency is critical Value F_HWhen frequency comparator 114 comparative result flip-flop number 115 subtraction count device effectively and subtract 1, the 3rd frequency Rate value is higher than upper frequency marginal value F_HWhen frequency comparator 114 the subtraction count device of comparative result flip-flop number 115 have Imitate and subtract 1, the 4th frequency values are higher than upper frequency marginal value F_HWhen frequency comparator 114 comparative result flip-flop number 115 subtraction count device is effective and subtracts 1, the 5th frequency values are higher than upper frequency marginal value F_HWhen frequency comparator 114 The subtraction count device of comparative result flip-flop number 115 is effective and subtracts 1, and total count value is less than lower critical meter in this case Numerical value BIT [00], so lower critical count value BIT [00] being assigned finally is treated as total count value.In another phase In anti-example, it is assumed that counting initial value BIT [00] and lower critical count value BIT [00] and upper critical count value BIT [11] are no Become, but the scope of five frequency values there occurs change, enumerator 115 is before and after counting on the basis of initial value BIT [00] The counting step of five execution is embodied in：First frequency values is less than lower frequency marginal value F_LWhen frequency comparator 114 ratio The relatively up counter of result flip-flop number 115 effectively and Jia 1, second frequency values are less than lower frequency marginal value F_LWhen The up counter of the comparative result flip-flop number 115 of frequency comparator 114 effectively and Jia 1, the 3rd frequency values it is low In lower frequency marginal value F_LWhen frequency comparator 114 comparative result flip-flop number 115 up counter effectively and plus 1st, the 4th frequency values are less than lower frequency marginal value F_LWhen frequency comparator 114 comparative result flip-flop number 115 Up counter effectively and Jia 1, the 5th frequency values are less than lower frequency marginal value F_LWhen frequency comparator 114 comparison knot The up counter of fruit flip-flop number 115 effectively and Jia 1, and the total count value after counting for five times in this case is more than upper Critical count value BIT [11], so upper critical count value BIT [11] being assigned finally is treated as total count value.

Referring to Fig. 9 and Figure 10, enumerator 115 described above occurs to the counting of the frequency value F of clock signal clk 1 In upper preset period of time T_SETIn-A, and total count value is finally transmitted and is encoded/be burnt to one by enumerator 115 and posted Store in storage 116.In upper preset period of time T_SETThe meaning of-A inside counting frequency value Fs be make it is adjacent next Individual preset period of time T_SETON time T in-A_ON2Absolute presupposition period T_SETON time T in-A_ON1It is adjusted, and The foundation for implementing adjustment is exactly the total count value corresponding to frequency value F.Adjustment ON time T_ON2Mode referring to Fig. 9, In the ON time generator 105c of Fig. 9, mainly include a fixed current source 110 and two optional extra currents Source 111,112, also including one the 3rd switch SW₅₁And an electric capacity C_T, supply voltage V_DDFor fixed current source 110 and two additional current sources 111,112 running voltages are provided.The wherein electric current I of the output of fixed current source 110₀Directly It is transported to C_TAn end node N_TPlace and electric capacity C can be continuously_TCharge, electric capacity C_TOpposite other end be connected to and connect Ground terminal GND.But additional current sources 111 and electric capacity C_TThe node N of one end_TBetween be connected to one the 4th switch SW₆₁, 4th switch SW₆₁First end receive additional current sources 111 output electric current I₁And the second end is connected to node N_T, only There is the 4th switch SW₆₁Control end cause the 4th switch SW high level is received₆₁During conducting, additional current sources The electric current I of 111 outputs₁Just can be from node N_TLocate as electric capacity C_TCharge.In the same manner, another additional current sources 112 and electricity Hold C_TThe node N of one end_TBetween be connected to another the 5th switch SW₆₂, the 5th switch SW₆₂First end receive it is attached Plus the electric current I of the output of current source 112₂And the second end is connected to node N_T, the only the 5th switch SW₆₂Control end connecing Receive high level and cause the 5th switch SW₆₂During conducting, the electric current I of the output of additional current sources 112₂Just can be from node N_T Locate as electric capacity C_TCharge.One the 3rd switch SW in voltage current adapter 105c-2₅₁First end be connected to node N_TAnd the second end is connected to earth terminal GND so that the 3rd switch SW₅₁With electric capacity C_TIt is that relation is in parallel, the 3rd opens Close SW₅₁Control end be input into monostable flipflop 105b in upper preset period of time T_SETBy control signal SQ1 in-A Rising edge come the high level clock signal CLK1 that formed, the 3rd switch SW₅₁Connected by transient state, then electric capacity C_TStorage In its one end namely node N_TThe electric charge at place switchs SW the 3rd₅₁This moment being switched on discharges, so the 3rd ratio Outfan compared with device A3 can produce low level signal S at this moment_ON1.Clock letter after the rising edge of control signal SQ1 The high level burst pulse of number CLK1 falls back to low level, and fixed current source 110 starts to electric capacity C_TNode N_TCharge, If the 4th switch SW₆₁Then additional current sources 111 and fixed current source 110 are switched on together to electric capacity C_TNode N_TCharge, if the 5th switch SW₆₂Be switched on then additional current sources 112 also with fixed current source 110 together to electric capacity C_TNode N_TCharge.The clock signal CKL1 triggering and conducting time generator produced by monostable flipflop 105b 105c proceeds by ON time T_ON1Timing, master switch Q1 connect ON time T_ON1Interior 3rd comparator The signal S that A3 sends_ON1It is continuously low level.Once electric capacity C_TIn conducting period T_ON1Inside persistently charge, in conducting Section T_ON1Electric capacity C after end_TNode N_TThe voltage at place starts than the 3rd reference voltage V_PCause greatly the 3rd comparator A3 Outfan produce signal S_ON1In conducting period T_ON1At the end of be turned to shut-off period T_OFF1Interior high level, and Signal S_ON1The reset terminal R of rest-set flip-flop 105a is imported into again, so the signal S of high level_ON1Can be resetted RS Trigger 105a, allows control signal SQ1 that Q output is produced by turning on period T_ON1Interior high level drops into shut-off Period T_OFF1Interior low level, so as to turn off master switch Q1.If master switch Q1 is detectd after first switch periods Survey voltage DE and still be below the first reference voltage V_REF, then master switch Q1 will start perform second switch periods, with this Analogize, until preset period of time T_SETAt the end of-A detect voltage DE it is anticipated that imagination be greater than the first reference voltage V_REF.According to this switching mode, master switch Q1 is in conducting period T_ON1Inside it is switched on and section T when off_OFF1Interior quilt The action of shut-off, in whole preset period of time T_SETCan circulate in-A repeatedly.

Second controller 105 is according to upper preset period of time T_SETThe total count value of-A inside countings device 115, produces next Individual preset period of time T_SETHigh level burst pulse CLK2 at the moment of control signal SQ2 and its rising edge in-B.This work It is embodied in as mechanism：If upper preset period of time T_SETIn-A, switching frequency f is too low causes transformator T to enter what is uttered long and high-pitched sounds Audio zone so that the final total count value of enumerator 115 is more than default initial count value because of cumulative algorithm, should Total count value is stored in depositor 116, and the binary element write by depositor 116 is by as control electronics Switch namely the 4th switch SW₆₁With the 5th switch SW₆₂The control signal whether connected, once switching frequency f is too low make Total count value is more than initial count value, and the total count value of such as write of depositor 116 is bit BIT [01], or write is considered as Upper critical count value BIT [11] of total count value, they are bigger than counting initial value code element BIT [00].

According to example described above, total count value BIT [01] is by as the 4th switch SW₆₁With the 5th switch SW₆₂'s Control signal, 0 control the 4th of high bit switch SW₆₁Shut-off, switchs SW compared with 1 control the 5th of low level₆₂Connect. Or total count value BIT [11] is by as the 4th switch SW₆₁With the 5th switch SW₆₂Control signal, high bit 1 control Make the 4th switch SW₆₁Connect, SW is switched compared with 1 control the 5th of low level₆₂Connect.It should be noted that leading in Fig. 9 Logical time generator 105c is only to illustrate modeled schematic diagram, and the content of some common-senses does not show, for example Those skilled in the art knows, and the control signal data of depositor need to pass through decoder for decoding in advance in certain embodiments After recycle one group of decoded signal effectively to turn on and off corresponding switch.

In next preset period of time T_SETThere is detecting voltage DE in-B and be less than the first reference voltage V_REFWhen, this is preset Period T_SETThe clock signal clk 2 of the high level burst pulse of the rising edge triggering of control signal SQ2 in-B once allows the Three switch SW₅₁Connected by transient state, electric capacity C_TIt is stored in node N_TThe electric charge at place is by the 3rd switch SW₅₁Discharge, So the outfan of the 3rd comparator A3 can produce low level signal S at this moment_ON2.The rising edge of control signal SQ2 The high level burst pulse of clock signal clk 2 falls back to low level afterwards, and fixed current source 110 starts to electric capacity C_TSection Point N_TCharge, if the 4th switch SW₆₁Be switched on then additional current sources 111 also with fixed current source 110 together to electricity Hold C_TNode N_TCharge, if the 5th switch SW₆₂Be switched on then additional current sources 112 also with fixed current source 110 Together to electric capacity C_TNode N_TCharge.Total count value BIT [01] control the 4th of depositor 116 switchs SW₆₁Shut-off And control the 5th and switch SW₆₂Connect, so the electric current I of the output of additional current sources 112₂Export with fixed current source 110 Electric current I₀It is delivered directly to electric capacity C_TAn end node N_TLocate as electric capacity C_TCharge, it is clear that electric current sum (I₀+I₂) phase For simple electric current I₀Charging rate faster, so next preset period of time T_SETRelative to a upper preset period of time in-B T_SET- A can soon by electric capacity C_TIt is full of, speed is faster.Identical reason, total count value BIT [11] of depositor 116 Control the 4th switch SW₆₁, the 5th switch SW₆₂Connect, so the electric current I of the output of additional current sources 111₁, additional electrical The electric current I of the output of stream source 112₂With the electric current I of the output of fixed current source 110₀It is delivered directly to electric capacity C_TAn end node N_TLocate as electric capacity C_TCharge, it is clear that electric current sum (I₀+I₁+I₂) relative to simple electric current I₀Charging rate faster, institute With next preset period of time T_SETRelative to upper preset period of time T in-B_SET- A can soon by electric capacity C_TIt is full of, Speed is faster.The clock signal CKL2 triggering and conducting time generator 105c produced by monostable flipflop 105b Carry out ON time T_ON2Timing, master switch Q1 connect ON time T_ON2What interior 3rd comparator A3 sent Signal S_ON2It is continuously low level.Once electric capacity C_TIn conducting period T_ON2Inside persistently charge, in conducting period T_ON2Knot Electric capacity C after beam_TNode N_TThe voltage at place starts than the 3rd reference voltage V_PThe big outfan for causing the 3rd comparator A3 The signal S of generation_ON2In conducting period T_ON2At the end of be turned to shut-off period T_OFF2Interior high level, and signal S_ON2 The reset terminal R of rest-set flip-flop 105a is imported into again, so the signal S of high level_ON2Can be resetted rest-set flip-flop 105a, Control signal SQ2 that its Q output is produced is allowed by turning on period T_ON2Interior high level drops into shut-off period T_OFF2 Interior low level, so as to turn off master switch Q1.If master switch Q1 detects voltage DE after first switch periods It still is below the first reference voltage V_REF, then master switch Q1 will start perform second switch periods, by that analogy, directly To preset period of time T_SETAt the end of-B detect voltage DE it is anticipated that imagination be greater than the first reference voltage V_REF.According to This switching mode, master switch Q1 is in conducting period T_ON2Inside it is switched on and section T when off_OFF2The action being inside turned off, In whole preset period of time T_SETCan circulate in-B repeatedly.

Has no doubt, in preset period of time T_SET- A does not introduce extra current source 111 and/or current source 112 in advance, but Preset period of time T_SETExtra current source 111 and/or current source 112 are introduced in-B so that preset period of time T_SETIn-B Conducting period T_ON2Because charging current is bigger, electric capacity C_TCharging interval speed relative to conducting period T_ON1Faster and Allow node N quickly_TThe 3rd reference voltage V of voltage ratio at place_PGreatly, its result is exactly to cause conducting period T below_ON2It is little In conducting period T_ON1.In view of master switch Q1 switching frequency f with conducting period T_ONIncrease and reduce or with leading Logical period T_ONReduce and increase, when load 18 is underloading or zero load, turn on period T_ON1The switching frequency f in stage because It is too small and allow transformator T enter utter long and high-pitched sounds audio zone when because conducting period T later_ON2Diminish, namely appropriate increase The value of switching frequency f, allows transformator T to depart from audio zone of uttering long and high-pitched sounds.

Substantially conducting period T_ON1With conducting period T_ON2Relative size relation it is non-with the counting initial value of enumerator 115 Chang Xiangguan.If in exemplary but non-limiting embodiment, in preset period of time T_SETThe meter of-A Stage Countings device 115 Number initial value is BIT [01] or BIT [10], then the 4th switch SW₆₁Or the 5th switch SW₆₂One of them can be switched on and Another one is closed, then the electric current I of the output of additional current sources 111₁Or the electric current I of the output of additional current sources 112₂Meeting With the electric current I in fixed current source 110₀Together in conducting period T_ON1Stage is electric capacity C_TCharge, total total charging electricity Flow valuve is (I₁+I₀) or (I₂+I₀), so that counting initial value therein is BIT [01] as an example, counting initial value BIT [01] On the basis of, the counting step by five execution before and after the priority time sequencing that different frequency occurs is：First frequency values ＞ Upper frequency marginal value F_HWhen frequency comparator 114 comparative result flip-flop number 115 subtraction count device effectively and subtract 1, Second frequency values ＜ lower frequency marginal value F_LWhen frequency comparator 114 comparative result flip-flop number 115 addition meter Number devices effectively and Jia 1, the 3rd frequency values ＞ upper frequency marginal value F_HWhen frequency comparator 114 comparative result triggering meter The subtraction count device of number devices 115 effectively and subtract 1, the 4th frequency values ＜ lower frequency marginal value F_LWhen frequency comparator 114 Comparative result flip-flop number 115 up counter effectively and Jia 1, the 5th frequency values ＞ upper frequency marginal value F_H When frequency comparator 114 the subtraction count device of comparative result flip-flop number 115 effectively and subtract 1, in this case Final total count value is BIT [00], that is, turns on period T_ON2Stage is electric capacity C_TCharge total total charging current Value is I₀, so electric capacity C_TIn conducting period T_ON2What stage charging needed is greater than electric capacity C total times_TIn the conducting period T_ON1The time that stage charges, equivalent to conducting period T_ON2It is adjusted to more than conducting period T_ON1, so as to cause switch Frequency f is from preset period of time T_SETThe higher value of-A is adjusted to preset period of time T_SETThe smaller value of-B.

In sum, previous preset period of time T in Fig. 10_SET- A, the control letter of the second controller 105 of primary side Number SQ1 is delivered to the first controller 104 of primary side by coupling element 106 so that what the first controller 104 was produced First pulse signal S₁Control master switch Q1 has ON time T in switch periods_ON1.Latter in Fig. 10 Preset period of time T_SET- B, control signal SQ2 of the second controller 105 of primary side are delivered to just by coupling element 106 First controller 104 of level side so that the first pulse signal S that the first controller 104 is produced₁Control master switch Q1 exists There is in switch periods ON time T_ON2.When preset period of time T_SET- A inside countings device 115 is to the upper of control signal SQ1 The number of frequency value F of the CLK1 of edge triggering is risen according to counting rule, be calculated final total count value is more than just During beginning count value so that latter preset period of time T_SETON time T in-B_ON2＜ ON time T_ON1.Vice versa, When be calculated final total count value is less than initial count value so that latter preset period of time T_SETConducting in-B Time T_ON2＞ ON time T_ON1.When be calculated final total count value is equal to initial count value so that latter Individual preset period of time T_SETON time T in-B_ON2=ON time T_ON1.Its cause is often to experience Pressure DE is less than the first reference voltage V_REFEvent when, total count value all can be updated once, and the code in total count value Unit directly decides switch SW₆₁、SW₆₂Connection whether.Namely voltage DE ought occur to detect next time less than the first ginseng Examine voltage V_REFEvent when, last detecting voltage DE is less than the first reference voltage V_REFThe total that calculates of stage Numerical value is determined_REFStage ON time.It is worth note Meaning is, although the present invention is explaining using two bit symbols and two extra additional current sources 111,112 as example The spirit of invention, but in the middle of actual topology, count initial value and count marginal value up and down and do not receive two in fact The restriction of number of symbols, while the quantity of additional current sources is not also limited by the such quantity of two branch roads.

In content described above, the data transmission medium namely the present invention between the first and second controllers 104,105 The framework of the pulse transformer PT adopted by the coupling element 106 being related to is extremely important, below corresponding Figure 11 A Into Figure 13 C, it will the structure of pulse transformer PT is discussed in detail.

Referring to Figure 11 A, it is contemplated that in the whole system of electric pressure converter, all of electronic devices and components all can surface installation or patch Piece is in PCB, and will advocate by the use of circuit board 200 in this embodiment to tie as pulse transformer PT physics A part for structure.It is emphasized that circuit board 200 is not the overall picture of PCB in Figure 11 A, needs are show only The regional area used.To drill or etch or all possible mode such as cut on circuit board 200, make in advance An adjacent first through hole 201 and second through hole 202 are had, their thickness through circuit board 200.As Option and nonessential item, can be being located at the region between first through hole 201 and the second through hole 202 in circuit board 200 The gap 203 of a strip is prepared, the gap 203 also extends through the thickness of circuit board 200.As option rather than must Must item, first through hole 201 and the second through hole 202 centered on gap 203 line of symmetry and be arranged in the seam with being respectively symmetrically The opposite sides of gap 203.The nonessential item as option, first through hole 201 and the second through hole 202 are square. The surface of circuit board 200 is formed with spiral coil 202a around first through hole 201, such as pulse transformer PT Primary side winding, spiral coil 202a has the conducting ring of the square shape of multiple concentric, and this series of concentric square is led Electric ring is set on circuit board 200 and is generally aligned in the same plane around first through hole 201, the conducting ring of each circle.Helical form The center of coil 202a and the center of first through hole 201 substantially overlap.Equally, in the same of circuit board 200 One surface is formed with another spiral coil 202b around the second through hole 202, such as the secondary of pulse transformer PT Side winding, spiral coil 202b have the conducting ring of the square shape of multiple concentric, this series of concentric square conducting ring ring Around the second through hole 202, the conducting ring of each circle is set on circuit board 200 and is generally aligned in the same plane.Spiral coil 202b Center and the center of the second through hole 202 substantially overlap.Spiral coil 202a has the end of a thread of a head end As Same Name of Ends and the end of a thread with another relative tail end as different name end.Same spiral coil 202b have one The end of a thread of individual head end is as Same Name of Ends and the end of a thread with another relative tail end as different name end.Spiral coil 202a Have various with the pattern of 202b or structure, for example circuit board 200 upper surface or lower surface around first through hole 201 form spiral helicine back-shaped shallow trench, including multiple concentric square grooves from the inside to the outside, when in these concentric square ditches Filling or damascene conductive material such as metallic copper etc. in groove, the conducting ring that just can form the square shape of multiple concentric is used as spiral Shape coil 202a.Equally, the upper surface or lower surface in circuit board 200 forms helical form around the second through hole 202 Shallow trench, when the filling in these concentric square grooves or during damascene conductive material, just can form the square shape of multiple concentric Conducting ring as spiral coil 202b.In other various alternative embodiments, spiral coil 202a or 202b Be exactly directly for example to adhere to, deposition, sputtering, the upper surface that mode is installed to circuit board 200 such as electroplate, including one is The multiple concentric square metal coil of row, for example they be and other metal lines or line footpath TRACE on circuit board 200 It is coated with by metal material simultaneously and is formed.Although being by taking square spiral coil 202a or 202b as an example, not in figure In the other embodiment of signal, each coil of spiral coil 202a or 202b is also configured to a series of concentric circulars Ring or various polygonal shapes etc..Although Figure 11 A only depict the spiral coil 202a or 202b of monolayer, In other alternative embodiments, for spiral coil 202a, can be arranging multilamellar not inside the circuit board 200 The spiral coil for illustrating comes with the spiral coil 202a of top layer or bottom right on the direction of circuit board 200 It is accurate to overlap, make mutually to arrange in the way of face is parallel between the spiral coil of different levels, now inside circuit board 200 These extra additions spiral coils (not illustrating) as spiral coil 202a around first through hole 201 Arrangement.It is same for spiral coil 202b for, the spiral shell that can not illustrated with the setting multilamellar inside the circuit board 200 Rotation shape coil be directed at coincidence with the spiral coil 202b of top layer or bottom on the direction of circuit board 200, makes Mutually arrange in the way of face is parallel between the spiral coil of different levels, now inside circuit board 200 these are extra Spiral coil (not illustrating) arrange around the second through hole 202 as spiral coil 202b.In multilamellar spiral shell Rotation shape coil framework in, between the spiral coil of different levels be spaced apart and they between be laminated with belonging to printed circuit board (PCB) 200 Insulating barrier and be electrically insulated, but two arbitrarily neighbouring spiral coils must meet the condition of an interconnection：Upper one Second end (or first end) of spiral coil must lead to the first end (or second end) of adjacent next spiral coil Cross the interconnection line that is built in circuit board 200 to be electrically connected with, these multi-layer spiral coils are together in series.Example Such as in multi-layer spiral coil, the first end (or second end) of the first spiral coil of top layer or bottom is used as multiple spiral shells The equivalent Same Name of Ends (or different name end) of rotation shape coil tandem structure, and the spiral coil at an end of bottom or top layer Equivalent different name end (or Same Name of Ends) of second end (or first end) as multiple spiral coil series connection structures.

Referring to Figure 11 A, pulse transformer PT at least includes the magnetic core framework 210 and bag of U-shaped (or saying it is the shape of a saddle) Include the magnetic core framework 211 of a strip, magnetic core framework 210 include along equidirectional the side arm portion 210a for extending in parallel and Side arm portion 210b, also includes the stage casing part 210c substantially vertical with side arm portion 210a, 210b, side arm portion 210a and 210b is connected to both the both sides of stage casing part 210c, substantial side arm portion 210a and 210b and stage casing part 210c is integral structure.Intert to first through hole 201 as a side arm portion 210a of U-shaped magnetic core framework 210 and Relative another side arm portion 210b of the U-shaped magnetic core framework 210 is then corresponded to and is interted to the second through hole 202, so that Obtain magnetic core framework 210 to be installed on circuit board 200, and in order to form the magnetic circuit loop of closure, in addition it is also necessary to by magnetic core Skeleton 211 is combined with magnetic core framework 210.In Figure 11 B, magnetic core framework 210 is from the front one of circuit board 200 Side is inserted, and the respective front end face (or disconnected section or facet) of two side arm portions 210a, 210b of magnetic core framework 210 Together with being brought into close contact with a surface of magnetic core framework 211 in the relative reverse side of circuit board 200, so as to build magnetic Road.It should be noted that in order to avoid bringing the deviation on understanding because of the difference of term or term, context is carried And side arm portion front end face END FACE be the surrounding side SIDE FACE of opposite side arm for.Magnetic core bone Gap 204, equally, magnetic are reserved between the side of one side arm portion 210a of frame 210 and the side wall of first through hole 201 Also gap 204 is reserved between the side of another side arm portion 210b of core crab 210 and the side wall of the second through hole 202. In Figure 11 B, in view of magnetic core framework 210 and magnetic core framework 211 are condensed together with separable form, if interior The electronic equipment for being equipped with pulse transformer PT is shaken or is fallen and is likely to cause magnetic core framework to collapse from preferably existing Some insulating cements are put on circuit board 200 by the rwo gluing or is retained on circuit board 200 and unlikely is rocked displacement.Note The primary efficacy of printed circuit board (PCB) 200 here is the transformator T for installing above and the envelope for being integrated with the first controller 104 Cartridge chip and each components and parts such as encapsulation chip of second controller 105 are integrated with, only in PCB 200 Some folding corner region or the comparatively rare region of some surface mount elements enter eleven punch 11 reserving a position, make Standby first through hole 201 and the second through hole 202, so as to install pulse transformer PT in this reserved location.Wherein master switch Q1 and synchro switch Q2 can both can be with separately installed in PCB 200, it is also possible to by master switch Q1 and first Controller 104 is installed in PCB 200 in being integrated in an encapsulation chip again, and/or by synchro switch Q2 It is integrated in an encapsulation chip with second controller 105 and is installed in PCB 200 again.

Referring to Figure 12 A, it is another kind of structure of pulse transformer PT, the still magnetic core framework 210 including U-shaped and long Cube or cube-shaped magnetic core framework 211, but the scheme of spiral coil 202a and 202b as an alternative, also have There are first chip 301 and second chip 302.The relatively close center of the first chip 301 of flat square shape First centre bore 314 through 301 thickness of the first chip is provided with position, and the first chip 301 also has At least two pins 312 and 313, the pin 312 and 313 are used for and the pad butt welding on circuit board 200, example Such as welded using scolding tin material by surface mount technology.The close center of the second chip 302 of flat square shape Place is provided with second centre bore 324 through 302 thickness of the second chip, and the second chip 302 also has at least Two pins 322 and 323, pin 322 and 323 are used for and the pad butt welding on circuit board 200.Now, electricity Adjacent first through hole 201 and second through hole 202 are formed with road plate 200 still.When the first chip 301 is installed to electricity When on road plate 200, it as the first square centre bore 314 should be with circuit board 200 square first through hole 201 Alignment, when the second chip 302 is installed on circuit board 200, its second centre bore 324 as square should be with electricity The second square through hole 202 of road plate 200 is aligned.As the first centre bore 314 and first through hole 201 are overlapped so U One side arm portion 210a of shape magnetic core framework 210 is easy to while be inserted through the rwo, the phase of U-shaped magnetic core framework 210 Another side arm portion 210b is then corresponded to and is inserted through the second overlapping centre bore 324 and the second through hole 202 simultaneously.In figure In 12B, magnetic core framework 211 is combined with magnetic core framework 210, magnetic core framework 210 is from the front of circuit board 200 Side is inserted, and the respective front end face of two side arm portions 210a, 210b of magnetic core framework 210 is in the phase of circuit board 200 The opposite side of reverse side is fit together with a surface accurate of magnetic core framework 211, so as to build magnetic circuit.Referring to Figure 12 B Shown, the side of a side arm portion 210a of magnetic core framework 210 is respective with first through hole 201, the first centre bore 314 It is reserved with gap 204 between the wall of side, the side of another side arm portion 210b of magnetic core framework 210 and the second through hole 202, Also gap 204 is reserved between second centre bore, 324 respective side wall.

Referring to Figure 12 C-1, the relation of the first chip 301 and the second chip 302 is changed on the basis of Figure 12 A, In the embodiment of Figure 12 A, the first chip 301 and the second chip 302 are each independent chips, and they need individually The paster toward on circuit board 200, but in the possible embodiments of Figure 12 C-1, the first chip 301 and the second chip 302 connect One is connected on as an entirety, the first chip 301 and 302 synchronous paster of the second chip circuit board 200 can be arranged on On.In the top view of Figure 12 C-2, the first chip 301 and the second chip 302 are arranged side by side, wherein the first chip 301 A corner 311a and a corner 321a of the second chip 302 between it is close to each other, and the rwo pass through one Connecting portion 331 links together.Another angle of another corner 311b of the first chip 301 and the second chip 302 Close to each other between portion 321b, the rwo is linked together by connecting portion 332.Connecting portion 331,332 is except arrangement The other positions in the first and second chips gap between the two are moveable to outside the corner of chip, as long as ensureing the of interconnection One chip 301 and the second chip 302 are substantially coplanar, synchronously can be installed on circuit board 200.

Referring to Figure 12 D, it is the perspective view of the first chip 301 and the second chip 302 shown based on Figure 12 A.First Chip 301 includes helical form wiring 315 and the second chip 302 includes helical form wiring 325, with regard to helical form wiring 315 Individually represent with 325 pattern in fig. 12e.Optionally, in fig. 12e, a substrate 317 is used to carry one Silicon substrate 316, substrate 316 can also be used alone, and substrate 317 and 316 respective center of substrate offer hole, Hole around its center on the upper surface of substrate 316 is disposed with helical form wiring 315, helical form wiring 315 Center and substrate 317,316 respective center of substrate substantially overlap because helical form wiring 315 is to lead Body is so insulated by the insulating barrier and substrate 316 of 316 upper surface of substrate.Another lining being arranged side by side with substrate 316 Bottom 326 is carry by a substrate 327, and substrate 326 can be used alone, 326 respective center of substrate 327 and substrate Position offers hole, and the hole around its center on the upper surface of substrate 326 is disposed with helical form wiring 325, The center and substrate 327,326 respective center of substrate of wherein helical form wiring 325 substantially overlaps, because Helical form wiring 325 is conductor so needing to insulate with substrate 326 by the insulating medium layer of 326 upper surface of substrate.This In substrate 317,327 have multiple choices mode ensure the present invention enforcement, can also adopt in addition to insulated substrate The alternative such as the lead frame (Lead-frame) of typical metal material.Although Figure 12 E only depict monolayer Helical form wiring 315 or 325, but in other alternative embodiments, can be with it for substrate 316 The helical form wiring that setting multilamellar is not illustrated weight is being directed on the direction of substrate 316 with helical form wiring 315 Close, the helical form of different levels is mutually arranged in the way of face is parallel between connecting up, now on substrate 316 these Helical form wiring (not illustrating) of extra addition is arranged around the first centre bore 314 as helical form wiring 315. The same helical form wiring that can not illustrated so that multilamellar is arranged on it for substrate 326 to connect up with helical form 325 overlap in the alignment on the direction of substrate 316, make the helical form of different levels mutually parallel with face between connecting up Mode arrange, helical forms wiring (not illustrating) and helical form cloth of these extra additions now on substrate 326 Line 315 is the same to be arranged around the second centre bore 324.In the framework of multi-layer spiral wiring, the spiral of different levels Be spaced apart between shape wiring and insulating medium layer (such as silicon dioxide etc.) is provided between them and electric between causing Insulation, but two arbitrarily neighbouring helical form wirings must meet the condition of an interconnection：Upper helical form wiring Second end (or first end) must be with the first end (or second end) of adjacent next helical form wiring by being built in insulation These multi-layer spirals wirings are together in series being electrically connected with by interconnection line in dielectric layer by this way.For example exist In multi-layer spiral wiring, positioned at top layer or bottom first helical form wiring first end (or second end) as multiple spiral shells Rotation shape connects up the equivalent Same Name of Ends (or different name end) of series connection structure, and positioned at the helical form cloth at bottom or an end of top layer Second end (or first end) of line connects up the equivalent different name end (or Same Name of Ends) of series connection structure as multiple helical forms.

Referring to Figure 12 D and Figure 12 A, the first chip 301 has a plastic-sealed body 311, and the second chip 302 has one Plastic-sealed body 321.In the first chip 301, the helical form wiring that substrate 316 and its upper surface are formed by plastic-sealed body 311 315 be coated in, in if substrate 317 is additionally provided with, which is also coated on by plastic-sealed body 311.Helical form wiring 315 One end (such as Same Name of Ends) by the lead 318 formed by wire bonding WIRE BONDING be connected to adjacent substrates 317, On the pin 312 of substrate 316, the opposite other end (such as different name end) of helical form wiring 315 is using wire bonding WIRE Other leads 318 that BONDING is formed are connected on the pin 313 of adjacent substrates 317, substrate 316, equally In lead 318 is also required to be coated on by plastic-sealed body 311.Pin 312 is used for the part for accepting lead 318 by plastic-sealed body 311 In being coated on, but pin 312 some extend to outside plastic-sealed body 311 for use in circuit board 200 on Pad butt welding, same pin 313 are used to accepting in the part of lead 318 is coated on by plastic-sealed body 311, but draw Foot 313 some extend to outside plastic-sealed body 311 for use in circuit board 200 on pad butt welding.Phase Similar, in the second chip 302, the helical form wiring 325 that substrate 326 and its upper surface are formed by plastic-sealed body 321 In being coated on, if substrate 327 is additionally provided with, it is also coated on interior by plastic-sealed body 321.Wherein helical form connects up 325 One end (such as Same Name of Ends) by the lead 328 formed by wire bonding WIRE BONDING be connected to adjacent substrates 327, On the pin 322 of substrate 326, the opposite other end (such as different name end) of helical form wiring 325 is using wire bonding WIRE Other leads 328 that BONDING is formed are connected on the pin 323 of adjacent substrates 327, substrate 326, equally In lead 328 is also coated on by plastic-sealed body 321, plastic-sealed body is, for example, to be prepared by the material of epoxy resin.Pin 322 It is used to accepting in the part of lead 318 is coated on by plastic-sealed body 311 with 323, but pin 322 and 323 each also has A part extend to outside plastic-sealed body 311 for use in circuit board 200 on pad butt welding.

Referring to Figure 12 D and Figure 12 A, in the first chip 301, a first square centre bore 314 is simultaneously through modeling Envelope body 311, substrate 316, the respective thickness of substrate 317 (if selected), and the first centre bore 314 is substantially Positioned at plastic-sealed body 311, substrate 316,317 respective center of substrate, helical form wiring 315 is used as pulse transforming The primary side winding of device PT, a series of concentric square conducting rings in the middle of it are around the first centre bore 314, and spiral The center of shape wiring 315 and the center of the first centre bore 314 essentially coincide.Corresponding, in the second chip In 302, a second square centre bore 324 is simultaneously through plastic-sealed body 321, substrate 326, substrate 327 (if quilt From) respective thickness, and the second centre bore 324 is located substantially on plastic-sealed body 321, substrate 326, substrate 327 Primary side winding of respective center, the wherein helical form wiring 325 as pulse transformer PT, in the middle of it is Row concentric square conducting ring is around the second centre bore 324, and helical form connects up 325 center and the second center The center in hole 324 essentially coincides.For the embodiment of Figure 12 C-1 and Figure 12 C-2, in plastic packaging operation MOLDING In step, the 321 synchronous integrated plastic packaging molding of plastic-sealed body of the plastic-sealed body 311 of the first chip 301 and the second chip 302, One corner 321a of one corner 311a and plastic-sealed body 321 of plastic-sealed body 311 is adjacent, close to each other in position, And both are bridged by the connecting portion 331 (and plastic-sealed body material) between them, plastic-sealed body 311 it is another One corner 321b of individual corner 311b and plastic-sealed body 321 is adjacent, close to each other in position, and by between them Connecting portion 332 (and plastic-sealed body material) both are bridged.In the embodiment of Figure 12 B, circuit board 200 On first through hole 201 and the region between the second through hole 202 can prepare the narrow gap 203 of strip and can not also prepare. In the embodiment of Figure 12 A to 12E, on position relationship, the stage casing part 210c and magnetic core bone of magnetic core framework 210 Frame 211 is parallel with the plane that the first flat chip 301, the second chip 302 are each located, also with circuit board 200 It is parallel, but magnetic core framework 210 connection the side arm portion 210a at section part 210c two ends and side arm portion 210b are equal wherein It is vertical with the plane that the first chip 301, the second chip 302 are each located, it is also perpendicular with circuit board 200.When first When chip 301 and the second chip 302 are installed on circuit board 200, substrate 316 and substrate 317,326 and of substrate Substrate 327 and for plastic packaging their flat plastic-sealed body 311,321 and circuit board 200 is parallel.

Referring to Figure 13 A, it is another kind of structure of pulse transformer PT, with first chip 401 and second core Piece 402, the first chip 401 include a U-shaped or saddle-shaped magnetic core framework 410, and the second chip 402 includes one U-shaped or saddle-shaped magnetic core framework 420.In the first chip 401, as shown in Figure 13 B, magnetic core framework 410 includes The side arm portion 410a and side arm portion 410c for extending in parallel also includes the center section part substantially vertical with side arm portion 410a, 410c 410b, stage casing part 410b is divided to be connected to side arm portion 410a, 410c between the two.One first coil winding 415 It is wrapped on the 410b of stage casing part, one end (such as Same Name of Ends) of first coil winding 415 is directly with welding or each with other Kind of connected mode is electrically connected with pin 412, the opposite other end (such as different name end) of first coil winding 415 it is direct with Welding is electrically connected with other various connected modes and pin 413, and pin 412,413 is adjacent to magnetic core framework 410.Modeling In magnetic core framework 410,415 plastic packaging of first coil winding are coated on by envelope body 411, pin 412 is used to accept First Line In that part of circle winding 415 is coated on by plastic-sealed body 411, but pin 412 some extend to plastic-sealed body Outside 411 for use in circuit board 200 on pad butt welding, same pin 413 be used for accept first coil around In that part of group 415 is coated on by plastic-sealed body 411, but pin 413 some extend to plastic-sealed body 411 Outside for use in circuit board 200 on pad butt welding.In the second chip 402, as shown in Figure 13 B, magnetic Core crab 420 includes that the side arm portion 420a for extending in parallel and side arm portion 420c also include and side arm portion 420a, 420c base This vertical stage casing part 420b, stage casing part 420b are connected to side arm portion 420a, 420c between the two.One Two coil winding 425 is wrapped on the 420b of stage casing part, and one end (such as Same Name of Ends) of second coil winding 425 is straight Connect to weld or be electrically connected with other various connected modes and pin 422, and second coil winding 425 is relatively another Hold (such as different name end) directly to weld or be electrically connected with other various connected modes and pin 423, pin 422,423 Neighbouring magnetic core framework 420.Plastic-sealed body 421 draws in being coated on magnetic core framework 420,425 plastic packaging of second coil winding Foot 422 is used to accepting in that part of second coil winding 425 is coated on by plastic-sealed body 421, but pin 422 is also Some extend to outside plastic-sealed body 411 for use in circuit board 200 on pad butt welding, same pin 423 For accepting in that part of second coil winding 425 is coated on by plastic-sealed body 421, but pin 423 also has one Point extend to outside plastic-sealed body 421 for use in circuit board 200 on pad butt welding.Figure 13 A's to 13C In embodiment, on position relationship, the stage casing part 410b of magnetic core framework 410, side arm portion 410a, 410c it is coplanar and It is parallel with the plane that flat the first chip 401 is located, the stage casing part 420b and side arm portion 420a of magnetic core framework 420, 420c is coplanar and parallel with the plane that flat the second chip 402 is located.And when the first chip 401 and the second chip 402 when be mounted side by side on circuit board 200, the magnetic core framework 410, magnetic core framework 420 and to being applied to modeling Seal their flat plastic-sealed body 411,421 and circuit board 200 is parallel.

Referring to Figure 13 A, for magnetic core framework 410 and magnetic core framework 420, it is desirable to the side arm portion 410a of magnetic core framework 410 Front end face 410a-1 from a side 411a of plastic-sealed body 411 it is exposed out, front end face 410a-1 in fact be category In a facet perpendicular with the length direction of side arm portion 410a or the disconnected section of side arm portion 410a, magnetic core is also required The front end face 410c-1 of the side arm portion 410c of skeleton 410 from a side 411a of plastic-sealed body 411 it is exposed out, Front end face 410c-1 is belonging to a cutting perpendicular with the length direction of side arm portion 410c of side arm portion 410c in fact Face or disconnected section.And require magnetic core framework 420 side arm portion 420a front end face 420a-1 from the one of plastic-sealed body 421 In individual side 421a it is exposed out, front end face 420a-1 be belonging in fact side arm portion 420a with side arm portion 420a's A perpendicular facet of length direction or disconnected section, also require the front end of the side arm portion 420c of magnetic core framework 420 Face 420c-1 from a side 421a of plastic-sealed body 421 it is exposed out, front end face 420c-1 is belonging to side in fact A facet perpendicular with the length direction of side arm portion 420c of arm 420c or disconnected section.Wherein it is further defined by using During pulse transformer PT, the side 411a of plastic-sealed body 411 must be directed towards the side 421a of plastic-sealed body 421, wherein limiting Side 411a and side 421a is aspectant be oppositely arranged be in order to allow magnetic core framework 410 side arm portion 410a front end Face 410a-1 can be aligned with the front end face 420a-1 of the side arm portion 420a of magnetic core framework 420, while magnetic can also allow The front end face 410c-1 of the side arm portion 410c of core crab 410 can be with the front end of the side arm portion 420c of magnetic core framework 420 Face 420c-1 is aligned, such that it is able to the side arm portion of the side arm portion 410a along magnetic core framework 410 to magnetic core framework 420 420a, and along the side arm portion 410c from the side arm portion 420c of magnetic core framework 420 to magnetic core framework 410, at two pieces The magnetic core magnetic circuit of closure is built between magnetic core framework 410 and 420.

Referring to Figure 13 B, it is a kind of using method of pulse transformer PT, by the first chip 401 and the second chip 402 When being installed on circuit board 200, make the first chip 401 and the second chip 402 close to each other, until the first chip The side 411a of 401 plastic-sealed body 411 touches a side 421a of the plastic-sealed body 421 of the second chip 402, and Side 411a and the seamless unoccupied places of side 421a fit together.The now front end of the side arm portion 410a of magnetic core framework 410 The seamless unoccupied places of front end face 420a-1 of the side arm portion 420a of face 410a-1 and magnetic core framework 420 fit together, magnetic core The front end face 420c-1 of the side arm portion 420c of the front end face 410c-1 and magnetic core framework 420 of the side arm portion 410c of skeleton 410 Seamless unoccupied place fits together.Equivalent to allowing the side arm portion 410a and magnetic core framework of magnetic core framework 410 on position relationship 420 side arm portion 420a docking, the side arm portion 420c of the side arm portion 410c and magnetic core framework 420 of magnetic core framework 410 Docking, so as to magnetic core framework 410 and magnetic core framework 420 can be spliced to form expected ring core structure.

Referring to Figure 13 C, the embodiment and Figure 13 B slightly have difference, Figure 13 B limit the side 411a of plastic-sealed body 411 with The side 421a of plastic-sealed body 421 is completely seamless to be brought into close contact, but in the middle of Figure 13 C, by the first chip 401 and the When two chips 402 are mounted side by side on circuit board 200, make the first chip 401 and the second chip 402 close to each other, But retain a gap 430 between the side 411a of plastic-sealed body 411 and the side 421a of plastic-sealed body 421, now still So require until the side 411a of the plastic-sealed body 411 of the first chip 401 touches the plastic-sealed body 421 of the second chip 402 Side 421a faces each other the alignment in face, and the front end face 410a-1 and magnetic of the side arm portion 410a of magnetic core framework 410 The front end face 420a-1 of the side arm portion 420a of core crab 420 faces each other the alignment in face, the side arm portion of magnetic core framework 410 The front end face 420c-1 of the side arm portion 420c of the front end face 410c-1 and magnetic core framework 420 of 410c faces each other the right of face It is accurate.Equivalent on position relationship, allow magnetic core framework 410 side arm portion 410a and magnetic core framework 420 side arm portion 420a Between be mutually butted in the way of it there is gap, similar, the side arm portion 410c of magnetic core framework 410 and magnetic core framework It is mutually butted in the way of it there is gap between 420 side arm portion 420c, so as to magnetic core framework 410 and magnetic core framework 420 can be spliced to form expected ring core structure, only the side arm portion 410a and magnetic core framework of magnetic core framework 410 420 side arm portion 420a separated and air gap, and the side arm portion of magnetic core framework 410 are formed in the position for disconnecting The side arm portion 420c of 410c and magnetic core framework 420 separated and air gap, front end face 410a-1 are formed in the position for disconnecting And the air gap between the air gap between front end face 420a-1 and front end face 410c-1 and front end face 420c-1 is used to prevent magnetic from satisfying With.When air gap is left in the magnetic core in pulse transformer PT, as the permeability of air only has such as iron core permeability Several one thousandths, magnetomotive force are nearly all dropped on air gap, thus leave air gap magnetic core its average permeability will significantly under Drop, not merely residual magnetic flux density can be reduced, and peakflux density may also reach up saturation flux density, so that magnetic No longer easily there is magnetic saturation in logical increment increase, magnetic core of transformer.In this embodiment, optionally also in plastic-sealed body 411 Side 411a and the side 421a of plastic-sealed body 421 between fill insulant 450 among the gap 430 that retains, absolutely Edge material 450 is not only capable of achieving electrical isolation, on the other hand can also effectively strengthen the first chip 401 and the second core Piece 402 is retained on the bond strength on circuit board 200.

More than, by explanation and accompanying drawing, the exemplary embodiments of the ad hoc structure of specific embodiment being given, foregoing invention is carried Existing preferred embodiment is gone out, but these contents has been not intended as limitation.For a person skilled in the art, in reading State it is bright after, various changes and modifications undoubtedly will be evident that.Therefore, appending claims should be regarded as and cover this Whole variations and modifications of bright true intention and scope.In Claims scope any and all scope of equal value with it is interior Hold, be all considered as still belonging to the intent and scope of the invention.

Claims (18)

1. a kind of electric pressure converter, it is characterised in that the first side winding of a transformator and a master switch are connected on Between individual input voltage and an earth terminal, the secondary side winding of the transformator is connected to one to load offer output voltage Between output node and a ground reference；And

One the first controller, drives master switch to switch between conducting and shut-off for producing the first pulse signal；

One is characterized output voltage size and/or characterizes the detecting voltage and one of load current size by one second controller Individual first reference voltage compares, and the logic state of a control signal produced by which is determined by comparative result；

One coupling element, is connected between first, second controller, and the logic state of control signal is delivered to first by which Controller, makes the first controller that the logic state of the first pulse signal is judged according to the logic state of control signal.

2. electric pressure converter according to claim 1, it is characterised in that in the first comparator of second controller Inverting input input is detected voltage and is input into the first reference voltage in in-phase input end；

When detecting voltage is less than the first reference voltage, the RS of the high level comparative result set second controller of first comparator Trigger, makes the control signal of rest-set flip-flop output be turned to high level from low level；

The ON time generator of second controller is turned to the moment of the rising edge of high level and opens from control signal from low level Beginning timing, the moment terminated to default ON time complete timing, when timing is completed the signal of ON time generator output by Low level is turned to high level and the rest-set flip-flop that resets, and makes control signal be turned to low level from high level.

3. electric pressure converter according to claim 2 a, it is characterised in that bias circuit in second controller First, second switch is in series with and ground reference between, in a common node, first opens first, second switched fabric Close and driven by control signal and second switch is driven by the inversion signal of control signal；

It is connected between the normal phase input end and the common node of the second comparator in the first controller and belongs to coupling element First electric capacity, the inverting input of the second comparator are input into the second reference voltage, the second comparator normal phase input end and earth terminal Between be connected with a resistance, belong to the second capacitance connection of coupling element between earth terminal and ground reference.

4. electric pressure converter according to claim 3, it is characterised in that first switch when control signal is high level Turn on and second switch shut-off, the voltage that bias circuit is provided is applied at common node, is drawn high second by coupling element and is compared The voltage of device normal phase input end exports the first pulse signal of high level to the second reference voltage, the second comparator is more than；

Control signal for low level when first switch shut-off and second switch connect, the current potential at the common node is clamped down on into ginseng Ground potential is examined, the voltage of the second comparator normal phase input end is dragged down to less than the second reference voltage by coupling element, second compares Device is output as low level first pulse signal.

5. electric pressure converter according to claim 2, it is characterised in that coupling element is pulse transformer, control Signal by second controller in a coupled capacitor be transferred to pulse transformer primary side winding one end, primary side around The other end of group is connected to ground reference；

One is connected between the one end for the primary side winding that a signal in first controller produces node and pulse transformer Individual coupled capacitor, the opposite other end of primary side winding are connected to earth terminal, produce and control so as to produce node in the signal The first pulse signal that the logic state of signal is consistent.

6. electric pressure converter according to claim 5, it is characterised in that the signal produce node and earth terminal it Between be connected with the resistance and a diode being arranged in parallel, the negative electrode of the diode is connected to signal and produces node and anode Earth terminal is connected to then.

7. electric pressure converter according to claim 2, it is characterised in that the anode of a commutation diode is connected to One end of the secondary side winding of transformator, the negative electrode of commutation diode are connected to output node, the secondary side winding of transformator Opposite other end is then directly connected to ground reference.

8. electric pressure converter according to claim 2, it is characterised in that one end of the secondary side winding of transformator is straight Output node is connected in succession, and a synchronization is connected between the opposite other end and ground reference of the secondary side winding of transformator Switch, wherein：

Synchro switch by being produced second pulse signal with the first pulse signal inversion signal each other by second controller Driving, the synchro switch is turned off when master switch is turned on and the synchro switch is connected when master switch is turned off；Or

Synchro switch is driven by second pulse signal produced by second controller, and in the first pulse signal, control master opens The synchro switch is turned off by the stage of shut-off by the control of the second pulse signal.

9. electric pressure converter according to claim 8 a, it is characterised in that sampling in ON time generator Keeper master switch connect but synchro switch shut-off stage, sampling and keep transformator secondary side winding with synchronously open The magnitude of voltage of the one end being connected is closed, the magnitude of voltage of sampling is converted into electricity by a voltage current adapter of ON time generator Flow and be charged to a charging capacitor in ON time generator；

One the 3rd switch and charging capacitor in ON time generator is connected in parallel on one between charge node and earth terminal, will The normal phase input end of threeth comparator of the control source at charge node in ON time generator and in the 3rd comparator Inverting input be input into the 3rd reference voltage；And

The clock signal of high level is produced by a monostable flipflop of the rising edge triggering second controller of control signal, should Clock signal is low level in remaining time in addition to the moment of the rising edge in control signal is for high level, so as to by Clock signal connects the 3rd switch to charging capacitor spark at the moment of the rising edge of control signal；

Charging capacitor proceeds by the timing of charge period after spark, until the voltage of charge node is more than the 3rd reference Voltage causes the comparative result of the 3rd comparator to be turned to high level timing by low level just to terminate, the high level of the 3rd comparator Comparative result triggering rest-set flip-flop resets, and the time period of the timing is used as the default ON time for connecting master switch.

10. electric pressure converter according to claim 9, it is characterised in that input voltage tends to increase causes sampling Magnitude of voltage when increasing therewith, default ON time tends to reducing；Or

Input voltage tends to reducing when causing the magnitude of voltage sampled to reduce therewith, and default ON time tends to increase.

11. electric pressure converters according to claim 2, it is characterised in that the 3rd in ON time generator opens Pass and charging capacitor are connected in one in parallel between charge node and earth terminal, during by the control source at charge node to conducting Between the 3rd comparator in generator normal phase input end and be input into the 3rd reference voltage in inverting input；

ON time generator includes a current source and multiple additional current sources for being charged for charging capacitor, and each is attached Plus between the current output terminal and charge node of current source, it is respectively connected with an electrical switch；

The clock signal of high level is produced by a monostable flipflop in the rising edge triggering second controller of control signal, The clock signal is low level with external remaining time for high level except the moment of the rising edge in control signal, so as to by Clock signal connects the 3rd switch to charging capacitor spark in the rising edge of control signal；

Charging capacitor proceeds by the timing of charge period after spark, until the voltage of charge node is more than the 3rd reference Voltage causes the comparative result of the 3rd comparator to be turned to high level timing by low level just to terminate, the high level of the 3rd comparator Comparative result triggering rest-set flip-flop resets, and the time period of the timing is used as the default ON time for connecting master switch.

12. electric pressure converters according to claim 11, it is characterised in that during detecting voltage pulsation, be set in pre- If the initial time of the period detecting voltage is less than the first reference voltage, and one of master switch is driven by the first pulse signal Or detecting voltage is modulated at the end of preset period of time more than the first reference voltage；

Priority time sequencing of the respective frequency values of one or more clock signals in preset period of time by appearance, by ON time One frequency comparator of generator is compared with upper frequency marginal value, lower frequency marginal value respectively, when any one frequency Value makes the binary system initial count value that an enumerator of ON time generator is arranged deduct 1 when being more than upper frequency marginal value, Or make the initial count value that enumerator is arranged add 1 when any one frequency values is less than lower frequency marginal value, all frequencies The completeer rear enumerator of value is calculated a total count value；

Total count value is defined during the upper critical count value that total count value is arranged more than enumerator and is equal to upper critical count value, or amounted to Total count value is defined during the lower critical count value that numerical value is arranged less than enumerator and is equal to lower critical count value, binary grand total Each in value characterizes high level or low level code element accordingly for turning on and off an electrical switch.

13. electric pressure converters according to claim 12, it is characterised in that in two preset period of time of arbitrary neighborhood In, the total count value in previous preset time period is more than initial count value, makes the electricity being switched in latter preset time period The quantity of electrical switch of the quantity of son switch than being switched in previous preset time period is more, then latter preset time period Interior default ON time is less than the default ON time in previous preset period of time；Or

Total count value in previous preset time period is less than initial count value, makes the electricity being switched in latter preset time period The quantity of electrical switch of the quantity of son switch than being switched in previous preset time period is few, then latter preset time period Interior default ON time is more than the default ON time in previous preset period of time；Or

Total count value in previous preset time period is equal to initial count value, makes the electricity being switched in latter preset time period The quantity of the electrical switch being switched in the quantity and previous preset time period of son switch is equal, then latter preset time period Interior default ON time is equal to the default ON time in previous preset period of time.

14. electric pressure converters according to claim 1, it is characterised in that the transformator also including one with it is secondary Side winding is around to being connected with two poles between one end of identical assists winding, one end of assists winding and an auxiliary capacitor Pipe, assists winding and the respective other end of auxiliary capacitor are connected to earth terminal, when secondary side winding has electric current to pass through its with it is auxiliary The diode forward helped between electric capacity turns on and flows through the electric current of assists winding and charges to the auxiliary capacitor, by auxiliary capacitor is First controller provides supply voltage.

15. electric pressure converters according to claim 14, it is characterised in that a upper electricity in the first controller is opened Dynamic model block has a junction field effect transistor and a controlling switch, and controlling switch is connected to junction field effect transistor Between control end and earth terminal, and controlling switch is to turn on when the voltage not up to one of auxiliary capacitor starts voltage level But it is off when reaching and starting voltage level；

Start the power up phase of incoming transport voltage in the electric pressure converter, alternating voltage is via defeated after a rectifier circuit rectifies Enter the drain electrode to the junction field effect transistor, make from junction field effect transistor source electrode the electric current for flowing out pass through a diode Charge for the auxiliary capacitor, until the voltage of auxiliary capacitor reaches startup voltage level to complete electrifying startup program, upper electricity is opened Controlling switch is turned off after the completion of dynamic program and is charged from assists winding to the auxiliary capacitor in the stage of assists winding conducting.

16. electric pressure converters according to claim 1, it is characterised in that also including a potentiometer, detecting electricity Pressure is that the potentiometer captures a partial pressure value to output voltage in output node and characterizes the size of output voltage.

17. electric pressure converters according to claim 1, it is characterised in that also including a sensing resistance, sensing , between output node and ground reference, it is to sense the pressure drop at resistance two ends and characterize to detect voltage for resistance and load in series Flow through the size of the load current of load.

18. electric pressure converters according to claim 1, it is characterised in that including a potentiometer, by this point Depressor captures a partial pressure value as feedback voltage in output node to the output voltage with ripple；Also including a sensing electricity Resistance, senses resistance and load in series between output node and ground reference, by the pressure drop at sensing resistance two ends as table The sensing voltage of load current size is levied；And

Also include wave filter, amplifier and adder, wave filter is used for the flip-flop filtered in feedback voltage but retains exchange The magnitude of voltage of composition, amplifier are used to amplify sensing voltage, and the magnitude of voltage and amplifier of the category alternating component of wave filter output is defeated Go out sensing voltage amplification magnitude of voltage by adder addition after as the detecting voltage.