TWI542135B - Voltage converter - Google Patents

Description

Voltage converter

The present invention relates generally to an electronic device for voltage conversion, and more specifically to instantaneously sensing an output voltage or an output current of a secondary side of a transformer used as a power switching, generating a transient response control signal, and utilizing a coupling element The control signal is transmitted to the primary side of the transformer for power switching to control the turn-off or turn-on of the primary side winding.

In the existing voltage converter, the voltage or current on the load side is collected, and the feedback signal of the collected load side is fed back to the driving component of the voltage converter by using a feedback network, for example, a typical pulse width modulation method. Or the pulse frequency modulation method or the like, the driving element uses the feedback signal to determine the duty ratio of the main switch that switches between on and off in the voltage converter, thereby scaling the output voltage of the voltage converter on the load side. It is known to those skilled in the art that the driving components of the voltage converter are used to drive the main switch, but the driving components do not directly draw the instantaneously varying load voltage from the load side, but rely on the feedback network to sense the load voltage. This kind of feedback mode will inevitably produce a delay effect. The bad result is that the driving component cannot synchronize with the changing state of the load voltage due to the delay to instantly switch the main switch, so the current output voltage value and load required for output to the load are required. There is a deviation between the actual voltage values that cause potential instability to the output voltage.

In an alternative embodiment, a voltage converter is disclosed in which a primary side winding of a transformer and a main switch are connected in series between an input voltage and a ground terminal, the secondary side winding connection of the transformer being provided to the load An output node of the output voltage and a reference ground potential; and a first controller for generating a first pulse signal to drive the main switch to switch between on and off; a second controller to characterize The output voltage magnitude and/or the detected voltage indicative of the magnitude of the load current is compared with a first reference voltage, and the logic state of a control signal generated by the comparison result is determined by the comparison result; a coupling element is connected to the first and second controls Between the devices, it passes the logic state of the control signal to the first controller, causing the first controller to determine the logic state of the first pulse signal according to the logic state of the control signal.

In the above voltage converter, the detection voltage is input to the inverting input end of the first comparator of the second controller, and the first reference voltage is input to the non-inverting input terminal; when the detection voltage is lower than the first reference voltage, the first comparison is performed. The high level comparison result sets the RS flip-flop of the second controller, so that the control signal output by the RS flip-flop is flipped from a low level to a high level; the second controller's on-time generator is low from the control signal The timing is started when the level is flipped to the rising edge of the high level, and the timing is completed until the end of the preset on-time. When the timing is completed, the signal output by the on-time generator is flipped from the low level to the high level and the RS flip-flop is reset. , the control signal is flipped from a high level to a low level.

In the above voltage converter, a first and a second switch are connected in series between a bias circuit of the second controller and the reference ground potential, wherein the first switch and the second switch are interconnected to a common node, and the first switch is The control signal is driven, and the second switch is driven by the inverted signal of the control signal; a first capacitor belonging to the coupling element is connected between the non-inverting input terminal of the second comparator in the first controller and the common node, The inverting input of the second comparator inputs a second reference voltage, and a resistor is connected between the non-inverting input of the second comparator and the ground, and a second capacitor belonging to the coupling element is connected between the ground and the reference ground potential .

In the above voltage converter, when the control signal is at a high level, the first switch is turned on and the second switch is turned off, and the voltage supplied from the bias circuit is applied to the common node, and the voltage of the non-inverting input terminal of the second comparator is pulled up by the coupling element. Up to be greater than the second reference voltage, the second comparator outputs a first pulse signal of a high level; when the control signal is low, the first switch is turned off and the second switch is turned on, and the potential at the common node is clamped to the reference ground The potential is pulled down by the coupling element to a voltage lower than the second reference voltage of the second comparator, and the second comparator outputs a first pulse signal of a low level.

In the above voltage converter, the coupling component is a pulse transformer, and the control signal is transmitted to one end of the primary side winding of the pulse transformer through a coupling capacitor in the second controller, and the other end of the primary side winding is connected to the reference ground potential; the first control A signal generating node and a terminal of the secondary side winding of the pulse transformer are connected with a coupling capacitor, and the opposite end of the secondary side winding is connected to the ground, thereby generating logic of the control signal at the signal generating node. The first pulse signal whose state is consistent.

In the above voltage converter, a resistor and a diode are arranged in parallel between the signal generating node and the ground, the cathode of the diode is connected to the signal generating node and the anode is connected to the ground.

In the above voltage converter, the anode of the rectifying diode is connected to one end of the secondary winding of the transformer, the cathode of the rectifying diode is connected to the output node, and the opposite end of the secondary winding of the transformer is directly connected to the reference ground. Potential.

In the above voltage converter, one end of the secondary winding of the transformer is directly connected to the output node, and a synchronous switch is connected between the opposite end of the secondary winding of the transformer and the reference ground potential, and the synchronous switch is controlled by the second controller. The driving of a second pulse signal generated as an inverted signal with the first pulse signal turns off the synchronous switch when the main switch is turned on and turns on the synchronous switch when the main switch is turned off. Or, still causing the synchronous switch to be driven by a second pulse signal generated by the second controller, at which time the second pulse signal is controlled by the first pulse signal (eg, at a low level) controlling the main switch to be turned off The control (for example, also at a low level) also turns off the synchronous switch, that is, both the main switch and the synchronous switch are turned off to enter the dead time.

In the above voltage converter, a sample holder in the on-time generator controls the voltage value of the end of the secondary winding of the transformer connected to the synchronous switch when the main switch is turned on but the synchronous switch is turned off, and is turned on. A voltage current converter of the time generator converts the sampled voltage value into a current to charge a charging capacitor in the on-time generator; a third switch in the on-time generator and the charging capacitor are connected in parallel at a charging node and Between the ground terminals, the voltage at the charging node is input to the non-inverting input terminal of the third comparator in the on-time generator and a third reference voltage is input to the inverting input terminal of the third comparator; and the control signal is The rising edge triggers a one-shot of the second controller to generate a high-level clock signal that is low except for the high level at the rising edge of the control signal and the rest of the time. Therefore, the third switch is turned on by the clock signal at the rising edge of the control signal, and the charging capacitor is temporarily discharged; the charging capacitor is placed in the transient state. After the charging period is started, until the voltage of the charging node is greater than the third reference voltage, the comparison result of the third comparator is ended from the low level to the high level timing, and the high level comparison result of the third comparator is triggered. The RS flip-flop is reset, and the time period of the timing is used as the preset on-time of the main switch.

In the above voltage converter, when the input voltage tends to increase and the sampled voltage value increases, the preset on-time tends to decrease; or when the input voltage tends to decrease, the sampled voltage value decreases, the preset is turned on. Time tends to increase.

In the above voltage converter, the third switch and the charging capacitor in the on-time generator are connected in parallel between a charging node and the ground, and the voltage at the charging node is input to the third comparator in the conduction time generator. The phase input terminal inputs a third reference voltage at the inverting input terminal; the on-time generator includes a fixed current source and a plurality of additional current sources for charging the charging capacitor, and the current output terminal and the charging node of each additional current source An electronic switch is connected between each other; a one-shot of the second controller is triggered by a rising edge of the control signal to generate a high-level clock signal, which is high except at the rising edge of the control signal The level is low outside the rest of the time, so that the third signal is turned on by the clock signal on the rising edge of the control signal to instantaneously discharge the charging capacitor; the charging capacitor starts to charge the charging period after the transient discharge until charging The voltage of the node is greater than the third reference voltage, causing the comparison result of the third comparator to be turned from the low level to the high level timing, High-level comparison result of the comparator triggers the reset RS flip-flop, the timer period as the main switch is turned ON preset time.

The voltage converter is configured to detect a voltage fluctuation, set the detection voltage to be lower than the first reference voltage at a start time of the preset time period, and drive the one or more switching cycles of the main switch by the first pulse signal to enable The detection voltage is modulated to exceed the first reference voltage at the end of the preset time period; the frequency values of the one or more clock signals in the preset time period are in the order of occurrence of the time, and a frequency comparator of the on-time generator Comparing with the upper frequency threshold and the lower frequency threshold respectively, when any one of the frequency values is greater than the upper frequency threshold, the initial count value of the binary set by the counter of the on-time generator is subtracted by 1, or when any one of the frequency values When the value is less than the lower frequency threshold, the initial count value set by the counter is incremented by 1. After all the frequency values are compared, the counter calculates a total value; when the total value is greater than the upper critical count value set by the counter, the defined total value is equal to the upper critical count value. Or the total value is equal to the lower critical count when the total value is less than the lower critical count value set by the counter , The total binary value of each of a high or low level characterizes the respective symbols used to turn off an electronic switch.

In the above voltage converter, in any two adjacent preset time periods, the total value in the previous preset time period is greater than the initial count value, so that the number of electronic switches that are turned on in the next preset time period is If the number of electronic switches that are turned on is greater than the previous preset time period, the preset conduction time in the latter preset time period is smaller than the preset conduction time in the previous preset time period; or the previous preset time The total value in the segment is smaller than the initial count value, so that the number of electronic switches that are turned on within the last preset time period is less than the number of electronic switches that are turned on in the previous preset time period, then the latter preset The preset conduction time in the time period is greater than the preset conduction time in the previous preset time period; or the total value in the previous preset time period is equal to the initial counting value, so that the electronic device that is turned on in the next preset time period The number of switches is equal to the number of electronic switches that are turned on in the previous preset time period, and the preset on-time in the latter preset time period is equal to the preset on-time in the previous preset time period.

In the above voltage converter, the transformer further includes an auxiliary winding wound in the same direction as the secondary side winding, and a diode is connected between one end of the auxiliary winding and one end of the auxiliary capacitor, and the auxiliary winding and the auxiliary capacitor are respectively One end is connected to the ground end, and when the secondary side winding has a current passing therethrough, the diode between the auxiliary capacitor and the auxiliary capacitor is forwardly conducting and the current flowing through the auxiliary winding is charged to the auxiliary capacitor, and the auxiliary capacitor is provided for the first controller voltage.

In the above voltage converter, a power-on starting module of the first controller has a junction field effect transistor and a control switch connected between the control terminal and the ground terminal of the junction field effect transistor, And the control switch is turned on when the voltage of the auxiliary capacitor does not reach a starting voltage level but is turned off when the starting voltage level is reached; when the voltage converter starts to be connected to the AC voltage, the AC voltage is passed through a The rectifier circuit is rectified and input to the drain of the junction field effect transistor, so that the current flowing from the source of the junction field effect transistor is charged to the auxiliary capacitor through a diode until the voltage of the auxiliary capacitor reaches the startup voltage level. To complete the power-on startup program, the power-on startup program is completed, the control switch is turned off, and the auxiliary winding is charged to the auxiliary capacitor during the period in which the auxiliary winding is turned on.

The voltage converter includes a voltage divider, and the detection voltage is a voltage divider value of the voltage divider at the output node and represents a magnitude of the output voltage. The sensing resistor is included, and the sensing resistor is connected in series with the load between the output node and the reference ground potential. The detection voltage is the voltage drop across the sensing resistor and characterizes the magnitude of the load current flowing through the load.

The voltage converter includes a voltage divider, wherein the voltage divider draws a voltage divider value as a feedback voltage at an output node at the output node; and further includes a sensing resistor, a sensing resistor and The load is connected in series between the output node and the reference ground potential, and the voltage drop across the sense resistor is used as a sense voltage that characterizes the magnitude of the load current; and a filter, an amplifier, and an adder are included, the filter is used to filter the feedback voltage In the DC component but retaining the voltage value of the AC component, the amplifier is used to amplify the sensing voltage, and the voltage value of the AC component of the filter output and the amplified voltage value of the sensing voltage of the amplifier output are added by the adder as the Detector Measure the voltage.

In an alternative embodiment, a pulse transformer is disclosed comprising a U-shaped first core bobbin with a set of side arms extending in parallel, and a second core bobbin including a strip, in use Providing a first and second through holes extending through the thickness of the printed circuit board on a printed circuit board on which the pulse transformer is mounted, and a set of side arm portions of the first core bobbin from the first side of the printed circuit board The first through hole and the second through hole are not inserted, and the front end faces of the set of side arm portions are directly pressed against one surface of the second core bobbin on the second side of the printed circuit board.

In the above pulse transformer, a planarized first and second spiral coils are disposed on a first side surface or a second side surface of the printed circuit board, and a series of concentric coils in the first spiral coil surround the first through hole Arranged, a series of concentric coils in the second helical coil are disposed around the second through hole. a region between the first and second through holes on the printed circuit board is provided with a strip-shaped slit penetrating through the thickness of the printed circuit board, and the first and second through holes are symmetrically distributed along the slit as a central symmetry line. Both sides of the gap.

In the above pulse transformer, the first and second helical coils appear as a square or circular spiral coil. Also included is an insulating paste applied to the printed circuit board for adhering the first and second core bobbins to the printed circuit board.

In the above pulse transformer, a plurality of first spiral coils are disposed inside the printed circuit board, and the first spiral coils of the first side surface or the second side surface of the printed circuit board are aligned and overlapped, and the plurality of first spiral coils are disposed inside the printed circuit board. The first spiral coils are each disposed around the first through hole; the second end of any of the upper first spiral coils is interconnected with the first end of the adjacent next first spiral coil, thereby a spiral coil is connected in series, and the first end of the first first spiral coil in the plurality of first spiral coils connected in series is used as one of an equivalent end of the same name or an equivalent name, and the last one The second end of the first helical coil serves as the other of the equivalent end of the same name or equivalent. For example, in the two first spiral coils adjacent to each other, an insulating layer belonging to the circuit board is disposed between any one of the first first spiral coils and the adjacent first spiral coil to space them. Also for example, the first end of the first first helical coil on the first side surface of the printed circuit board serves as an equivalent end of the same name (or a different name) of the plurality of first helical coil series structures, and is located in the printed circuit The second end of a first helical coil at the end of the second side surface of the plate serves as an equivalent different end (or the end of the same name) of the plurality of first helical coil series structures.

In the above pulse transformer, a plurality of second spiral coils are disposed inside the printed circuit board, and the second spiral coils of the first side surface or the second side surface of the printed circuit board are aligned and overlapped, and the plurality of second spiral coils are disposed inside the printed circuit board. The second helical coils are each disposed around the second through hole; any second end of the upper second helical coil is interconnected with the first end of the adjacent next second helical coil, thereby The two spiral coils are connected in series, and the first end of the first second helical coil is used as one of the equivalent end of the same name or the equivalent name in the plurality of second helical coils connected in series, one at the end The second end of the second helical coil serves as the other of the equivalent end of the same name or equivalent. For example, the first end of the first second helical coil on the first side surface of the printed circuit board serves as an equivalent end of the same name (or a different name) of the plurality of second helical coil serial structures, and is located on the printed circuit board The second end of the first helical coil at the end of the second side surface serves as an equivalent name end (or the same name end) of the plurality of second helical coil series structures.

In the above pulse transformer, a power transformer main transformer is also mounted on the printed circuit board. The primary side winding of the main transformer receives the input voltage and provides an output voltage for the load on the secondary side winding, and the primary side winding of the main transformer and a main switch are connected in series. a wafer with a first controller mounted on the printed circuit board for generating a first pulse signal for driving the main switch to switch between on and off; a wafer with a second controller mounted on the printed circuit On the board, a detection voltage that characterizes the magnitude of the output voltage and/or the magnitude of the load current is compared with a first reference voltage, and the logic state of a control signal generated by the comparison is determined by the comparison result; wherein the pulse transformer will control The logic state of the signal is passed to the first controller, causing the first controller to determine the logic state of the first pulse signal according to the logic state of the control signal, thereby determining whether the main switch is turned on or off.

In an alternative embodiment, a pulse transformer is disclosed comprising a U-shaped first core bobbin with a set of side arms extending in parallel, and a second core bobbin including a strip, in use Providing a first and second through holes extending through the thickness of the printed circuit board on a printed circuit board on which the pulse transformer is mounted; and a first wafer having a first center hole and a second hole having a second center hole a second wafer, the first and second wafers are mounted on the printed circuit board, the first central hole and the first through hole are coincidently aligned, and the second central hole and the second through hole are aligned and coincident; from the first side of the printed circuit board Inserting one of the set of side arm portions of the first core bobbin into the first center hole, the first through hole and the other while inserting the second center hole, the second through hole, and the set of side arm portions The respective front end faces are directly pressed against one surface of the second core bobbin on the second side of the printed circuit board.

In the above pulse transformer, the first wafer includes: a first substrate on which a first spiral wiring is disposed on one surface: two pins disposed near the first substrate, the first spiral wiring The two ends are respectively connected to the two pins through lead wires; a first plastic sealing body covers the first substrate, the first spiral cloth, and the lead wires, wherein the pins are used to receive a part of the lead wires by the first The molding body is covered, but another portion of the lead extends beyond the first molding body for soldering with the pad on the printed circuit board; the first center hole penetrates the first molding body and the first substrate, and the first portion A series of concentric spiral wires in a spiral wiring are disposed around the first center hole. If a first substrate carrying the first substrate is further disposed, the two pins of the first substrate and the first wafer are disposed adjacent to each other, and the first substrate is also covered by the first molding body, and the first center hole It also penetrates the first substrate.

In the above pulse transformer, a plurality of first spiral wires are disposed on the first substrate and they are vertically aligned with each other, and an insulating dielectric layer is disposed between the two first spiral wires adjacent to each other. a series of concentric spiral wirings in a first spiral wiring are disposed around the first central hole; any second end of the upper first spiral wiring and the first end adjacent to the next first spiral wiring are mutually Connecting all of the first spiral wires in series, wherein the first end of the first first spiral wire in the plurality of first spiral wires connected in series serves as an equivalent end of the same name or an equivalent name In one of the two, the second end of a first spiral wiring at the end serves as the other of the equivalent end of the same name or the equivalent name. For example, in the two first spiral wirings adjacent to each other, an insulating dielectric layer is provided between any of the previous first spiral wirings and the adjacent first spiral wiring to space them. Also for example, the first end of a first spiral-shaped wiring on the topmost substrate on the substrate serves as an equivalent-named end (or a different end) of the plurality of first spiral-shaped wiring series structures, and is located on the substrate The second end of the first spiral wiring of the lowest layer serves as an equivalent different end (or the same end) of the plurality of first spiral wiring series structures.

In the above pulse transformer, the second wafer includes: a second substrate on which a second spiral wiring is disposed on the surface of the second substrate: two pins disposed near the second substrate, and the second spiral wiring The two ends are respectively connected to the two pins through lead wires; a second plastic sealing body covers the second substrate, the second spiral cloth, and the lead wires, wherein the pins are used to receive a part of the lead wires by the second The plastic body is covered, but another portion of the lead extends beyond the second plastic body for soldering to the pads on the printed circuit board; the second central hole extends through the second plastic body and the second substrate, and A series of concentric spiral wirings in the two spiral wirings are arranged around the second center hole. If a second substrate carrying the second substrate is further disposed, the two pins of the second substrate and the second wafer are disposed adjacent to each other, and the second substrate is also covered by the second molding body, and the second center The holes also penetrate the second substrate.

In the above pulse transformer, a plurality of second spiral wirings are disposed on the second substrate and they are vertically aligned with each other, and an insulating dielectric layer is disposed between the two adjacent second spiral wirings. a series of concentric spiral wires in the second spiral wiring are arranged around the second center hole; the second end of any of the last second spiral wires is interconnected with the first end of the adjacent next second spiral wire Thereby, all the second spiral wires are connected in series, and the first end of the first second spiral wire in the plurality of second spiral wires connected in series is used as the equivalent end of the same name or the equivalent name Alternatively, the second end of a second spiral wiring at the end serves as the other of the equivalent end of the same name or the equivalent name. For example, in the two second spiral wirings adjacent to each other, an insulating dielectric layer is provided between any of the preceding second spiral wirings and the adjacent second spiral wiring to space them. Also for example, the first end of a second spiral wiring on the topmost substrate on the substrate serves as an equivalent end of the same name (or a different name) of the plurality of first spiral wiring series structures, and is located on the substrate The second end of one of the bottommost spiral wirings serves as an equivalent different name end (or the same name end) of the plurality of second spiral wiring series structures.

The pulse transformer described above further includes an insulating paste coated on the printed circuit board for adhering the first and second core bobbins to the printed circuit board. The first wafer and the second wafer are connected to each other by one or more connecting portions to make them a coplanar integrated structure, so that the first wafer and the second wafer are simultaneously mounted on the printed circuit board.

In an alternative embodiment, a pulse transformer is disclosed, including first and second wafers, the first wafer having a U-shaped first core bobbin and a first molding body having a first core bobbin molded The second wafer has a U-shaped second core bobbin and a second molding body having a second core bobbin; the first and second core bobbins each have a set of side arms extending in parallel a front end surface of each of the set of side arm portions of the first core bobbin is exposed from one side edge surface of the first molding body, and a front end surface of each of the side arm portions of the second core bobbin is from the second plastic package One side edge surface of the body is exposed such that the side edge surface of the side arm portion of the first molding body exposing the first core bobbin faces the side edge surface of the side arm portion of the second molding body exposing the second core bobbin, And the front end surface of any one of the side arm portions of the first core bobbin is aligned with the front end surface of one of the second core bobbins.

In the above pulse transformer, a middle portion is connected between a set of side arm portions of the first core bobbin, and the first coil having the first coil winding is wound on the middle portion of the first core bobbin, the first coil winding The two ends are respectively connected to two pins of the first wafer, the pins for receiving a part of the first coil winding are covered by the first plastic body, and the other part of the lead is extended to the outside of the first plastic body Butt welding with the pads on the printed circuit board.

In the above pulse transformer, a middle portion is connected between a set of side arm portions of the second core bobbin, and the second coil winding of the second wafer is wound on the middle portion of the second core bobbin, and the second coil winding is The two ends are respectively connected to two pins of the second wafer, the pins for receiving a part of the second coil winding are covered by the second plastic body, and the other part of the lead is extended to the second plastic body Butt welding with the pads on the printed circuit board.

In the above pulse transformer, when the first and second wafers are mounted side by side on the printed circuit board, the first molding body and the second molding body are disposed apart from each other, and the front end surface of the side arm portion of the first core core frame and the second magnetic core The front end faces of the side arm portions in the skeleton are aligned one-to-one in a spaced apart manner.

In the above pulse transformer, when the first and second wafers are mounted side by side on the printed circuit board, the first plastic body and the second plastic body are closely attached to each other, so that the side arm of the first plastic body exposing the first core frame The side edge surface of the portion and the side edge surface of the side arm portion of the second molding body exposing the second core bobbin are seamlessly fitted, the front end surface of the side arm portion of the first core bobbin and the second core bobbin The front end faces of the side arm portions are aligned one to one in such a manner as to be pressed against each other.

In the above pulse transformer, the first molding body and the second molding body are spaced apart and filled with an insulating material in a gap between them, a front end face of the side arm portion of the first core bobbin and a side arm in the second core bobbin The front end faces of the portions are aligned one to one in a manner spaced apart by an insulating material.

The technical solutions of the present invention will be clearly and completely described in conjunction with the embodiments, but the described embodiments are merely examples of the embodiments used in the description of the present invention and not all of the embodiments, based on the embodiments, The solutions obtained by those skilled in the art without creative efforts are within the scope of the present invention.

Referring to FIG. 1, the inventive spirit of the invention is exemplified by an AC-to-DC flyback FLYBACK voltage converter including a power stage transformer T for voltage conversion, the transformer T mainly having a primary side. Or the primary side winding L _P and the secondary side or secondary winding L _S , the first end of the primary side winding L _P receives the input voltage V _IN at the input node N ₁₀ as the name terminal and the primary side winding L _P A main switch Q1 is connected between the opposite second end and the ground GND. The basic working mechanism is embodied in that the main switch Q1 is switched between on and off by the primary side controller or the first controller 104. When the main switch Q1 is turned on, the primary side current flows through the primary side. The winding L _P and the main switch Q1 flow to the ground GND, but at this stage, the secondary side winding L _S has no current flowing, and the primary side winding L _P starts to store energy; once the main switch Q1 is turned off, the primary side current stops. The polarity of all the windings is reversed, and the transformer T begins to transfer energy to the secondary side winding L _S such that the secondary side winding L _S supplies the operating voltage and current to the load 18 during the period in which the main switch Q1 is turned off, and Charge is charged and stored at output node N ₂₀ to output capacitor C _{OUT ,} and output capacitor C _OUT may continue to provide an operating voltage to load 18 when no current flows through secondary side winding L _{S and} cannot directly supply operating current to load 18 . In some embodiments the transformer T also has an auxiliary winding L _AUX , the winding of the auxiliary winding L _AUX is wound in the same direction as the winding of the secondary side winding L _S , that is, once the main switch Q1 is turned off, a flow occurs. The current of the auxiliary winding L _AUX can be substantially charged to a capacitor C _AUX and serves as an operating voltage source for the first driver 104.

Referring to FIG. 1, the alternating current is rectified by the rectifier 101, and the bridge rectifier 101 includes four diodes such as the diodes D11 to D14 shown. Usually, a sinusoidal alternating voltage V _{AC of a} conventional mains is input to a pair of input lines, that is, busbars 12 and 14. The bridge rectifier 101 fully utilizes the positive half cycle and the negative half cycle of the original alternating current sinusoidal waveform to complete the sine of the alternating current. The waveform is converted to the same polarity for output. When the sinusoidal alternating voltage V _AC is full-wave rectified by the bridge rectifier 101, it is rectified and converted into a ripple voltage with an alternating current component. To further reduce the ripple of the ripple voltage, the alternating current is rectified and further utilized a CLC type. A filter filters out the ripple of the rectified voltage to obtain an input voltage V _IN . It can be observed in Fig. 1 that one end of the inductance L ₁ of the CLC type filter is connected to the respective cathodes of the diodes D ₁₁ and D _{13 of the} rectifier 101, and the opposite end of the inductance L ₁ is coupled to the primary at the node N ₁₀ a first end of the side winding L _P , and a capacitor C _{11 of the} CLC filter is connected between one end of the inductor L ₁ and the ground GND, and the other capacitor C _{12 of the} CLC filter is connected to the other end of the inductor L ₁ and Between ground GND. The anodes of the diodes D ₁₂ and D _{14 of the} bridge rectifier 101 are connected to the ground GND, wherein the bus bar 12 is connected to the anode of the diode D ₁₁ and the cathode of D ₁₂ and the bus bar 14 is connected to the diode D ₁₃ Anode and cathode of D ₁₄ .

Referring to FIG. 1, the voltage converter further includes an RCD clamp bit circuit or turn-off buffer circuit 103 in parallel with the primary side winding L _P . The turn-off snubber circuit 103 includes capacitors and resistors connected in parallel with each other, one end of each of which is connected to the node N ₁₀ and the other end of each of them is connected to the cathode of a diode in the turn-off snubber circuit 103, the two poles The anode of the body is then connected to the second end of the primary side winding L _P . The function of the shutdown buffer circuit 103 is to limit the superposition of the peak voltage and the secondary coil reflection voltage caused by the energy of the leakage inductance of the high-frequency transformer when the main switch Q1 is turned off, and the timing of the superposition voltage is turned from the saturation state of the main switch Q1. During the turn-off process, the energy in the leakage inductance can be charged to its capacitor by turning off the diode of the buffer circuit 103, and the voltage on the capacitor may rush to the superposition of the back electromotive force and the leakage inductance voltage, and the function of the capacitor Then the energy of this part is absorbed. When the primary side winding L _P and the main switch Q1 enter the conducting phase again from the off state, the energy on the capacitance of the shutdown buffer circuit 103 is released by turning off the resistance of the buffer circuit 103 until the voltage on the capacitor reaches the next main switch. Q1 turns off the back electromotive force before.

Referring to FIG. 1, the first end of the secondary side winding L _S is connected to the output node N ₂₀ as a different name end, and the opposite second end of the secondary side winding L _S is connected to the first end of a synchronous switch Q2 as a name end. And the second end of the synchronous switch Q2 is connected to the reference ground potential VSS. The output capacitor C _OUT is connected between the output node N ₂₀ and the ground reference VSS, or provide an output voltage V _O load 18 as an operating voltage to the load 18 at the output node N _20. It should be noted that one of the limit switches Q1 and Q2 is turned on and the other must be turned off. For example, the primary side switch Q1 of the primary side requires the secondary side synchronous switch Q2 to be turned off during the turn-on phase, and vice versa, the primary side. The main switch Q1 requires the secondary side synchronous switch Q2 to be turned on during the off phase. The main switch Q1 and the synchronous switch Q2 each have a first end, a second end and a control end, which serve as electronic switches, and the high and low logic levels of the signal applied to the control end determine that the first end and the second end are conductive. Still disconnected. In the normal operating phase of the voltage converter, the first controller 104 of the first pulse signal S generated by _a primary side for driving the main switch Q1 is switched between OFF and ON state, the second controller 105 of the secondary side The generated second pulse signal S _{2 is} used to drive the synchronous switch Q2 to switch between the off and on states. In addition, when the synchronous switch Q2 is driven by the second pulse signal S ₂ generated by the second controller 105, there is still a dead time between the main switch Q1 and the synchronous switch Q2, so it may also occur in the A pulse signal S ₁ controls the phase in which the main switch Q1 is turned off. The second pulse signal S ₂ controls the case where the synchronous switch Q2 is turned off.

Referring to Figure 1, in addition to the secondary winding L _S, L _AUX auxiliary winding of a first phase terminal end additionally provided as connected to the anode of a diode D _AUX, and the cathode of the corresponding diode is connected to the D _AUX One end of the capacitance C _AUX, and the other end of the capacitance C _AUX is connected to the GND ground terminal, and an opposite second end as the auxiliary winding L _AUX name end connected to the ground terminal GND. When the main switch Q1 is turned on, the secondary side winding L _S and the auxiliary winding L _AUX have their opposite ends of the same name being negative and no current flows, and the output capacitor C _OUT supplies power to the load 18. Conversely, when the main switch Q1 is turned off, the polarity of the secondary side winding L _S and the auxiliary winding L _AUX are reversed, and their respective synonyms are positive with respect to the same name end and have current flow, and energy transfer of the primary side winding L _P To the secondary side winding L _S and the auxiliary winding L _AUX , in other words, when the main switch Q1 is turned off, not only the secondary side winding L _S supplies the load current to the load 18 but also the output capacitor C _OUT , and the auxiliary winding L _AUX is also returned The auxiliary capacitor C _AUX acting as a power source is charged. In FIG. 1, the voltage V _CC held at one end of the capacitor C _AUX is taken as the power supply voltage of the first controller 104. The capacitor C _Y is a safety capacitor connected between the primary side ground GND and the secondary side reference ground potential VSS, and can filter out the noise voltage generated by the distributed capacitance between the primary side and the secondary side winding, or filter the primary Common mode interference due to coupling capacitance between the side and secondary side windings.

Referring to FIG. 1, the second controller 105 on the secondary side immediately captures the change state of the output voltage V _O at the node N ₂₀ or instantaneously senses the change of the load current I _O (ie, output current) flowing through the load 18, and thereby generating a control signal SQ, and the first controller 104 of the primary side requires the use of high and low logic level state control signal SQ way to further generate a first pulse signals S1, and accordingly the pulse signals S ₁ through the first main switch decision Q1 needs to be turned on or needs to be turned off. Because the second controller 105 generates a change in the control signal SQ with respect to the voltage V _O or the current I _O that is almost transient, the first controller 104 generates the first pulse signal S1 to respond immediately to the change of the control signal SQ, then A pulse signal S1 is equivalent to a change in the instantaneous tracking voltage V _O or current I _O . As to how the second controller 105 generates a control signal SQ, and how the second controller 105 and the first controller 104 use the coupling element 106 to interactively transfer information, etc., will be described in detail hereinafter.

Referring to Figure 2, in the TL431 feedback network, resistors R ₁ and R ₂ are voltage-samped for output voltage V _O , resistor R _{3 is} used for loop gain adjustment, capacitors C ₁ and C ₂ are compensation capacitors, and resistor R ₅ is Compensation resistor. The general working principle is: when the output voltage V _O rises, the control terminal of the three-terminal programmable shunt regulator in the TL431 (corresponding to the inverting input of a voltage error amplifier) is input with the resistors R ₁ and R ₂ The voltage divider value increases as the output voltage V _O rises, but the voltage at the cathode of the three-terminal programmable shunt regulator diode (corresponding to the output of the voltage error amplifier) drops, causing the light to flow through The primary current I _D of the light-emitting element connected between the cathode of the shunt regulator diode and the resistor R ₃ in the coupler 17 is increased, and the transistor in-line current of the received light intensity on the other side of the photocoupler 17 is connected. The output current that has passed is also increased, so that the voltage of the feedback 埠COMP of the primary side controller 16 is lowered to cause the duty ratio of the pulse signal of the control main switch Q1 to decrease, thereby achieving a reduction in the output voltage V _O . Vice versa, when the output voltage V _O decreases, the adjustment process is similar but the trend of each corresponding response state is reversed, and finally the duty ratio of the pulse signal controlling the main switch Q1 is increased to achieve the rise of the output voltage V _O . . The function of the resistor R ₄ is to additionally inject a current into the TL431 to prevent the TL431 from operating normally due to the injection current being too small. If the resistance value R _{3 is} appropriately selected, the resistor R ₄ can be omitted. The feedback network of Figure 2 must reserve sufficient gain and phase margin to ensure stability of the overall system, such as an open loop gain of at least 45° phase margin, typically allowed to range from 45° to 75°. Obviously, the biggest problem with this form of compensation is that the control mode is complicated and the delay effect is very obvious. The primary side controller 16 cannot detect the secondary side immediately, and the present invention advocates abandoning such a feedback network.

Referring to FIG. 3, the coupling component 106 of FIG. 1 specifically uses a coupling capacitor. Referring to FIG. 4, the coupling component 106 of FIG. 1 specifically employs a pulse transformer. In addition, other piezoelectric elements or optical coupling elements and the like are also suitable as the coupling element 106 as long as they can be referred to as a primary side controller or a first controller 104 and a secondary side controller or second controller 105. Interchange information information.

Referring to FIG. 5, a safety capacitor C _X is connected between the input lines 12 and 14 to suppress the difference model interference and filter out the high frequency clutter signal. In the reduction diagram, an input capacitor C _{IN is} connected to the input node. Between the ground terminal GND and the AC voltage V _AC input to the set of input lines 12 and 14 is rectified by the bridge rectifier 101 described above and then filtered by the input capacitor C _IN to obtain an input voltage V _IN . The voltage converter converts the input voltage V _IN through the voltage of the power stage to provide an output voltage V _O to the load on a set of output lines 22, 24. In the present invention, a rectifying circuit is further provided on the input lines 12, 14. The anode of one rectifying diode D ₂₁ of the rectifying circuit is connected to the input line 12, and the other rectifying diode D ₂₂ of the rectifying circuit is The anode is then connected to the input line 14. Further, the respective cathodes of the diodes D ₂₁ and D ₂₂ are interconnected and connected to the 汲 terminal of a high voltage start-up element JFET belonging to the first controller 104, and also at the 汲 terminal of the JFET and the diodes D ₂₁ and D ₂₂ limiting resistor R connected between a respective cathode ₂₁ shown in FIG. 1, the source terminal of a junction field effect transistor JFET connected to the anode of a diode D _31, the diode D ₃₁ is connected to the cathode The ungrounded end of the auxiliary capacitor C _AUX as the power supply is mentioned, and a current limiting resistor R ₃₁ is connected between the gate control terminal and the source terminal of the JFET, and the connection between the gate of the JFET and the ground GND is connected. a control switch SW _31, SW control gate switch ₃₁ is connected to a first terminal of the JFET and a second electrode terminal connected to the ground terminal GND. When the input line 12, while the access plug listed AC power, applied to the switch SW switches the control gate electrode ₃₁ of the driving control signal CTRL start switch SW ₃₁ into a conducting state, the switch SW is controlled gate electrode ₃₁ to ground potential will GND turns on the JFET of the negative threshold voltage, so the generated current charges from the drain of the JFET to the source through the diode D ₃₁ to the ungrounded end of the capacitor C _AUX . The forward voltage drop across resistor R ₃₁ rises, but the voltage across the JFET gate to source drops, and eventually the voltage across the JFET source and gate is approximately equal to the voltage of a JFET pinch off voltage. The value, which corresponds to the actual voltage drop from the JFET gate G to the source S direction, is equal to the negative of this pinch-off value. When the JFET charges the capacitor C _AUX until its stored voltage V _CC rises to the startup voltage level, an unillustrated drive control module is triggered to enter a working state, and the drive control module is used to generate an initial pulse signal and make the main The switch Q1 is switched between on and off by the initial pulse signal to start operation, and the voltage converter completes the start of the Start-Up program. After the start of the program, the capacitor C _AUX is charged by the auxiliary winding L _AUX through the diode D _AUX connected to its first terminal. In addition, although not shown in FIG. 1, it should be recognized that a voltage divider may be connected between the first end of the auxiliary winding L _AUX and the ground GND to input the divided voltage of the voltage divider sampling to the first controller. 104, whereby the first controller 104 utilizes the voltage divider to perform current zero crossing (ZCD) detection of the secondary side winding or overvoltage detection of the secondary side output voltage. And a first end of the main switch Q1 is connected to a second end of the primary side winding L _P , and a second end of the main switch Q1 is connected with a sensing resistor R _S between the source and the ground GND. By multiplying the current value of the primary side winding L _P by the resistance value of the sensing resistor R _S , a voltage V _S indicating the magnitude of the current flowing through the primary side can be obtained. If the voltage V _{S is} input to the first controller 104, the first The controller 104 limits this voltage V _S to a predetermined limit voltage V _LIMIT to monitor the primary side current and achieve overcurrent protection.

Referring to FIG. 1, after the startup program is completed to switch the main switch Q1 between on and off for the first time, once the main switch Q1 is turned off, the first end of the secondary side winding L _S is positively polarized, The voltage drawn at the first end of the secondary side winding L _S can be used as the starting voltage ST to turn on the secondary controller 105 on the secondary side. The second controller 105 immediately monitors the output voltage V _{O of the} secondary side and monitors the current I _O flowing through the load 18 in a specific manner, for example, by using the reference ground potential VSS connected in series at the output node N ₂₀ and the secondary side. A voltage divider obtained by a voltage divider R _D1 and R _D2 to obtain a divided voltage value which is substantially generated at a node where the resistors R _D1 and R _D2 are interconnected and fed back as a feedback voltage V _FB Go to the second controller 105. And a load 18 and a sense resistor R _C are arranged in series between the output node N ₂₀ and the reference ground potential VSS of the secondary side, and the current I _O flowing through the load 18 can be sensed by the sense resistor R _C The falling V _{CS is represented} by the resistance of the sense resistor R _C , in other words, the sensed voltage drop V _CS can be used to characterize the magnitude of the load current value flowing through the load 18 and the sense resistor R _C .

Referring to FIG. 6A, some components of the first controller 104 and the second controller 105 are shown to achieve the above-mentioned changes in the sense voltage drop V _CS and the feedback voltage V _FB to instantly control the conduction of the main switch Q1. Or the purpose of shutting down. The first controller 104 and the second controller 105 rely on the coupling element 106 for data interaction. The coupling element 106 includes two coupling capacitors C ₂₁ and C ₂₂ . The working mechanism of the first and second controllers 104, 105 will be described below. . It is to be noted that the first controller 104 and the second controller 105 are merely exemplary of the following structures for explaining the inventive spirit of the present invention, and the embodiments have various equivalent modifications, and any implementation based on the implementation For example, the solutions obtained without creative labor are within the scope of the present invention.

In the second controller 105, there is a first switch SW ₄₁ and a second switch SW ₄₂ each of which includes a first end and a second end and a control end, as an electronic switch, the level of the signal applied by the control end The logic state determines whether the first end and the second end are turned off or turned on. The two are connected in series between the bias circuit 105d and the reference ground potential VSS, for example, the first end of the first switch SW ₄₁ is connected to the bias circuit 105d and the second end is connected to the first end of the second switch SW ₄₂ The second end of the second switch SW ₄₂ is connected to the reference ground potential VSS, and the first switch SW ₄₁ and the second switch SW _{42 are} controlled by a control signal SQ generated by the Q output of the RS flip-flop 105a, such as a control signal. SQ is coupled to the control terminal of the first switch SW _41, the signal is coupled via a control signal SQ inverted by inverter 105e generated to the control terminal of the second switch SW ₄₂ is, of course, also be a control signal SQ is also coupled through a buffer and then a first control terminal of the switch SW _41. That is, the first switch SW ₄₁ turns on the second switch SW _{42 is} switched off or should the first switch SW ₄₁ SW _{42 is} turned off the second switch should be turned on.

For the second controller 105, a voltage divider value of the output voltage V _O , that is, a feedback voltage V _FB , is divided by the resistors R _D1 and R _{D2 of the} voltage divider, and the feedback voltage V _{FB is} input to the second control. One of the first comparators A1 of the comparator 105 has an inverting input, and a first reference voltage V _REF is input to the non-inverting input of the first comparator A1. Alternatively, as a method of replacing the feedback voltage V _FB , the sensing resistor R _C connected in series with the load 18 is drawn to the sensing voltage V _CS characterizing the magnitude of the flow through the load 18, and the sensing voltage V _{CS is} input to the second controller 105. The inverting input of the first comparator A1. In addition, the output of the first comparator A1 is connected to the set terminal S of the RS flip-flop 105a, and the signal S _ON output by the one of the second controllers 105 is input to the reset terminal R of the RS flip-flop 105a. And a one-shot or one-click circuit 105b is connected between the Q output of the RS flip-flop 105a and the on-time generator 105c. In the second controller 105, the first switch SW ₄₁ and the second switch SW ₄₂ are located on a branch of the reference ground potential VSS, and the node N ₂ is the second end of the first switch SW ₄₁ and the second switch SW ₄₂ A common node at the first end interconnection, node N _{4 is} connected to the reference ground potential VSS, and node N ₄ is a node at the second end of the second switch SW ₄₂ .

For the first controller 104, it includes a second comparator A2, and further a second comparator having a positive input terminal connected to a node A2 is N _1, and has a ground terminal GND connected to a node N _3, A resistor R ₄₁ connected between the node N ₁ and the node N ₃ is also provided. A second reference voltage V _TH is input to the inverting input of the second comparator A2. Wherein the node N ₁ of the first controller 104 and second controller 105 is connected to node N belongs to a coupling capacitor C ₂₁ of element 106, the first controller 104 of the node N ₃ between the 105 and the second controller ₂ A capacitor C ₂₂ belonging to the coupling element 106 is connected between the nodes N ₄ . Although the twisted pair structure of the coupling element 106 and the Ethernet network are completely different, they have similar data transmission functions. For example, the node N ₁ can be regarded as the receiving interface RX1+ of the first controller 104, and the node N ₃ can be regarded as Corresponding to the receiving interface RX2- of the first controller 104, the node N ₂ can be regarded as the transmitting interface TX1+ of the second controller 105, and the node N ₄ can be regarded as the sending of the second controller 105. Interface TX2-.

The interaction between the first controller 104 and the second controller 105 to discuss the implementation of the first pulse signal S ₁ of the main switch Q1 is now discussed from a system perspective, which needs to be explained with the aid of FIGS. 6A and 6B. . When the inverting terminal of the first comparator A1 in the second controller 105 separately inputs the feedback voltage V _FB or separately inputs the sensing voltage V _CS , when the feedback voltage V _FB or the sensing voltage V _CS starts to be higher than the positive phase end When a reference voltage V _{REF is} low, that is, an event occurring at time T ₁ in FIG. 6B, the output of the first comparator A1 is a logic high level, so the RS flip-flop 105a is set to output the output terminal Q. The control signal SQ jumps to a logic high level, so that the control signal SQ turns on the first switch SW ₄₁ in FIG. 6A, but the signal inverted by the inverter signal 105 is inverted to the logic low level, so the signal is turned off. Two switches SW ₄₂ . Since the second switch SW _{42 is} turned off when the first switch SW _{41 is} turned on, the reference ground potential VSS potential can be lower than the ground GND potential, so that a signal is transmitted from the second controller 105 to the first controller 104, Along the biasing circuit 105d, the first switch SW ₄₁ , the node N ₂ , the capacitor C ₂₁ , the node N ₁ , the resistor R ₄₁ , the node N ₃ , the capacitor C ₂₂ , the node N ₄ , and the reference ground potential VSS A current path is formed on loop LOOP1, at which point the positive voltage source provided by bias circuit 105d begins to charge capacitor C ₂₁ in coupling element 106 through first switch SW ₄₁ and node N _{2 that} are turned on, then node N ₂ That is, the change state of the charging voltage V _TX1 at the transmission interface TX1+ is gradually increased as shown in FIG. 6B. And the change state of the charging voltage V _RX1 at the node N ₁ , that is, the receiving interface RX1+ is also as shown in FIG. 6B. Since the voltage across the capacitor C ₂₁ cannot be abruptly changed, the voltage V _RX1 at the time T ₁ has almost the maximum value, and the capacitance C between the plates ₂₁ of the voltage gradually raising the reception voltage V _RX1 RX1 + at the interface gradually decreased. At this stage, since the charging voltage V _RX1 at the node N ₁ , that is, the receiving interface RX1+ is greater than the second reference voltage V _TH , the output result of the second comparator A2, that is, the generated first pulse signal S ₁ is a logic high level. Thus, the main switch Q1 is turned on by the first pulse signal S ₁ coupled to the control terminal of the main switch Q1. It should be noted that since the first pulse signal S ₁ has started to control the main switch Q1, in the start-up phase of the voltage converter, the output of the drive control circuit in the first controller 104 is used for control. an initial pulse signal of the primary switch Q1 stops generating, complete control is started by the main switch Q1 of the first pulse signal S _1, except the voltage converter can restart the power required again with the initial pulse signal to start the main switch Q1.

6B, a first pulse signal S T ₁ time ₁ caused this state continues until time T ₂ to the time T _2, on-time generator 105c set on-time T _ON ends, so that the on-time generator 105c generates A logic high level signal S _ON is sent as a reset signal to the reset terminal S of the RS flip-flop 105a, so that the control signal SQ outputted from the Q output terminal of the RS flip-flop 105a is flipped to a logic low level, thereby controlling the signal SQ off. The first switch SW ₄₁ in FIG. 6A is turned off, but the signal in which the control signal SQ is inverted by the inverter 105e is at a logic high level, so that the second switch SW ₄₂ is turned on. Since the second switch SW _{42 is} turned on when the first switch SW _{41 is} turned off, from the second controller 105 to the first controller 104, there will be along the node N ₂ , the second switch SW ₄₂ , the node N ₄ , the capacitor C ₂₂ , node N ₃ , resistor R ₄₁ , node N ₁ , capacitor C ₂₁ return to node N _{2 to} form a closed loop LOOP2, and a portion of the charge stored by capacitor C ₂₁ and capacitor C ₂₂ is neutralized and neutralized by resistor R ₄₁ Consumption. Therefore, starting from time T ₂ , the discharge of the capacitor C ₂₁ causes the charging voltage V _TX1 at the node N ₂ , that is, the transmission interface TX1+ to be gradually decreased. At the time T ₂ , the voltage of the capacitor C ₂₁ cannot be abruptly changed, resulting in the node N ₁ . That is, the voltage V _RX1 at the receiving interface RX1+ is pulled down to a negative value that occurs briefly, and as the capacitor C ₂₁ and the capacitor C ₂₂ discharge the charge, the voltage V _RX1 at the receiving interface RX1+ is close to the static zero potential at the time T ₃ , and N ₂ at a node that is the transmission voltage V _TX1 interface TX1 + at close to T ₃ time static at zero potential, at this stage since the node at N ₁ i.e. receives the voltage V _RX1 interface RX1 + is less than the second reference example, near zero potential The voltage V _TH causes the output of the second comparator A2, that is, the generated first pulse signal S _{1 to} be a logic low level, so that the main switch Q1 is turned off by the first pulse signal S ₁ . As seen from FIG. 6B, the on-time T _ON between the time T _{1 and the} time T ₂ is the phase in which the main switch Q1 is turned on, and the off-time T _OFF between the time T _{2 and the} time T ₃ is that the main switch Q1 is turned off. The stage, referring again to FIG. 1, has explained above that the second pulse signal S ₂ is the first pulse signal S ₁ or the inverted signal of the control signal SQ, so the second pulse signal S _{2 is} at the on time T _ON and logic state of the off time T _OFF of the pulse signals S ₁ and the first contrast, can be generated synchronizing switch S ₂ of the second pulse signal for controlling the secondary side by the second control means 105 Q2.

During the period in which the main switch Q1 is turned on, the primary side current flows through the primary side winding L _P for energy storage. At this time, since the synchronous switch Q2 is turned off, no current flows through the secondary side winding L _S , and the output capacitor C _OUT supplies power to the load 18 . . At the stage when the main switch Q1 is turned off, the primary side current is reduced to zero, the primary side winding L _P releases energy, and the energy of the primary side winding L _P is transferred to the secondary side winding L _S and the auxiliary winding L _AUX , at which time the synchronous switch Q2 is turned on. Therefore, a current flows through the secondary side winding L _S and the synchronous switch Q2, the secondary side winding L _S supplies a load current to the load 18 and charges the output capacitor C _OUT , and the auxiliary winding L _AUX also charges the capacitor C _AUX serving as a power source. Generating on on-time controller 105c determines the on-time T _ON delay mode measure, in conjunction with FIGS. 6A and 6B, the example may be triggered by a control signal SQ RS 105a outputted from the flip-flop rising Rising-edge at time T ₁ of a single The steady state flip-flop 105b generates a narrow clock pulse CLK1 of the continuous nanosecond level. It should be noted that the narrow clock pulse CLK1 is only high level on the rising edge of the control signal SQ, and the other time is low level. The clock pulse CLK1 notifies the on-time generator 105c to start timing, and the on-time generator 105c retransmits the high-level signal S _ON by the on-time generator 105c at the timing when the timing is just after the preset on-time T _ON ends. The controller 105a, therefore, this control mode can be regarded as a control mode of constant on-time substantially. According to the inventive spirit of the present invention, the duration of the preset constant on-time T _ON during each switching cycle is also It can be adjusted, for example, we can design a minimum constant on-time T _ON-MIN or a maximum constant on-time T _ON-MAX that meets the requirements.

Referring to Figure 6C, an alternative embodiment based on Figure 6A is shown. Considering that the switching frequency f of the main switch Q1 decreases as the input voltage V _IN increases or as the input voltage V _IN decreases, and the frequency f decreases as the on-time T _ON increases or The on-time T _ON decreases and increases. If the switching frequency f is too small, the core flux of the transformer T cannot be restored to the starting point of the hysteresis loop, causing the core to be oversaturated, for example, the input voltage V _{IN is} increased. If the switching frequency f is too small, the transformer T will be saturated. At this time, once the core cannot withstand the voltage, it is easy to burn. In this embodiment we will overcome this problem. When the main switch Q1 is turned on but the synchronous switch Q2 is turned off, the secondary side winding L _S has no current, but can be from the second end of the secondary side winding L _S like the front end and the first end of the synchronous switch Q2 connected at a node to retrieve sampled voltage V _SAM amount of this node, and a second terminal of the secondary winding L _S of the voltage V _SAM period is approximately equal to the number of turns of the secondary winding L _S ratio of the primary NS The parameter NP of the side winding L _P is then multiplied by the value NS/NP multiplied by the input voltage V _IN , that is to say the voltage V _{SAM is} related to the magnitude of the input voltage V _IN . Based on this correlation, the conduction time of perceived magnitude of the voltage generator 105c of V _SAM, whereby as a basis to generate the appropriate on-time T _ON to suppress the switching frequency f of the magnetic core is reduced to an abnormal state caused by the saturation. As shown in FIGS. 6C and 6D, the sense voltage drop V _CS or the feedback voltage V _{FB is} smaller than the first reference voltage V _{REF , which} causes the first comparator A1 to output a high level to the set terminal S of the RS flip-flop 105a. The control signal SQ generated by the Q output of the RS flip-flop 105a is inverted from a low level to a high level, and the output of the control signal SQ to the monostable flip-flop 105b causes the monostable flip-flop 105b to be low-powered at the control signal SQ. The clock signal CLK1 is generated at the time when the rising edge of the flipping to the high level is turned flat. The on-time generator 105c includes a sample holder (S/H) 105c-1 and a voltage-current converter 105c-2, and further includes a third switch SW ₅₁ and a capacitor C _T , wherein the sample holder 105c-1 The input end is connected to the second end of the secondary side winding L _S as the name end, the output end of the sample holder 105c-1 is connected to the voltage input end of the voltage current converter 105c-2, and the power supply voltage V _DD is a voltage current converter 105c-2 to provide operating voltage, current output end of the capacitor C _T and the voltage-current converter 105c-2 connected to the node N _T, relative to the other end of the capacitor C _T is connected to the ground terminal GND. A first terminal of the third switch SW ₅₁ is connected to a node N _T and a second end connected to the ground terminal GND so that the third switch SW ₅₁ and the capacitor C _T is the parallel relationship, the control terminal of the third switch SW ₅₁ of the input monostable The clock signal CLK1 generated by the flip-flop 105b. On-time generator 105c further includes an end a third comparator A3, the positive-phase input terminal of the third comparator A3 is connected to the capacitor C _T is charging i.e. node N _T, in a third inverting input of comparator A3 is The terminal inputs a third reference voltage V _P .

Referring to Figure 6C, on-time generator 105c adjusted on-time T _ON working mechanism is that the use of the sample holder 105c-1 sampling voltage V _SAM second end as the name of the end of the secondary winding L _S, and the sampling timing, for example, It may be a time when the main switch Q1 is turned on and the synchronous switch Q2 is turned off. If the input voltage V _IN is larger, the voltage value held by the sample holder 105c-1 is larger, and the current output by the voltage current converter 105c-2 is increased. Big. Vice versa, the smaller the input voltage V _{IN is, the} smaller the voltage value held by the sample holder 105c-1 is, resulting in the smaller the current output by the voltage current converter 105c-2. Since the clock signal CLK1 for driving the third switch SW ₅₁ is at a high level only at the rising edge of the control signal SQ generated by the RS flip-flop 105a, the other time is a low level, so that the rising edge of the control signal SQ When the third switch SW ₅₁ is turned on instantaneously, the charge stored at one end of the capacitor C _T , that is, the node N _T is released at the moment when the third switch SW ₅₁ is turned on, so the third comparator A3 At this point, the output will generate and output a low level signal S _ON . In Fig. 6D, the timing of the rising edge of the control signal SQ is the timing at which the preset period T _SET starts. After the rising edge of the control signal SQ ends, the clock signal CLK1 is turned back to the low level again. As long as the third switch SW _{51 is} turned on and then turned off, the capacitor C _{T is} again subjected to the current output by the voltage-current converter 105c-2. Charging. Once the continuous charging capacitance C _T in the conduction period T _ON, the voltage at the node N _T during the off-period T _OFF after the end of the on period T _ON is greater than the third reference voltage start V _P. The final result is that the signal S _ON generated at the output of the third comparator A3 is raised from the low level in the on period T _ON to the high level in the off period T _OFF , and the signal S _ON is input again. The reset terminal R of the RS flip-flop 105a, so the high level signal S _ON resets the RS flip-flop 105a, causing the control signal SQ generated at the Q output thereof to fall from the high level in the on period T _ON to the off period T Low level within _OFF . Control signal SQ in the OFF period T _OFF is a continuous low level until the end of the off period T _OFF further continued low until the next sensing piezoelectric drop or V _CS than the first feedback voltage V _FB reference The voltage V _{REF is} small, and the first comparator A1 asserts a high level again to set the RS flip-flop 105a to output a high level. And the output terminal of the third comparator A3 produces the signal S _ON during the off-period duration T _OFF is high until the end of the off period T _OFF is a further continuation of the high level until the next unless the SQ control signal There is a rising edge, so that the clock signal CLK1 appears high level to turn on the third switch SW ₅₁ , so that the node N _{T of the} capacitor C _T is transiently discharged, and the third comparator A3 generates the low level signal S again. _ON .

Referring to FIG. 6C, the larger the input voltage V _IN is, the larger the voltage value held by the sample holder 105c-1 is, and the larger the current value outputted by the voltage current converter 105c-2 is, thereby reducing the charging time, and soon. Let the voltage at the node N _T at one end of the capacitor C _T exceed the third reference voltage V _P , which is equivalent to the length of the shortening period T _ON during the entire switching period, and the control signal SQ is high level during the period T _ON and is The on-time of the main switch Q1, so the on-time T _{ON is} shortened when the input voltage V _IN is larger, corresponding thereto, the control signal SQ is the low level in the period T _OFF and is the off-time of the main switch Q1. In other words, although the increase of the input voltage V _{IN is} intended to lower the switching frequency f, the effect of shortening the on-time T _ON is to suppress the degree of reduction of the switching frequency f. Vice versa, once the input voltage V _{IN is} smaller, the smaller the voltage value held by the sample-and-holder 105c-1 is, the smaller the current value outputted by the voltage-current converter 105c-2 is, and the charging time is delayed, and finally The slower speed causes the voltage at the node N _T at one end of the capacitor C _{T to} exceed the third reference voltage V _P , which is equivalent to the length of time during which the period T _ON is appropriately extended throughout the switching period, so the input voltage V _{IN is} more Small, causing the on-time T _{ON of the} main switch to be extended. In other words, although the input voltage V _{IN is} lowered to increase the switching frequency f, the effect that the on-time T _ON is extended is to suppress the increase in the switching frequency f. It will be apparent that this embodiment of the invention provides excellent protection of the relative steady state of the switching frequency f.

For example, in the discontinuous DCM mode, the switching frequency f = (2 × I _O × L × V _O ) ÷ {(V _IN ) ² × (T _ON ) ² }, where L is the equivalent inductance value of the transformer T, according to the present invention The scheme provided above, obviously, whether the input voltage V _{IN is} decreased or increased, the variation value of the calculated value of (V _IN ) ² ×(T _ON ) ² in the functional relationship is not large, and the switching frequency f can be suppressed. The amount of change/amplitude thus avoids damage to the transformer T entering saturation.

Referring to Figure 7A, the most significant difference compared to the embodiment of Figure 6A is that the component type of the coupling element 106 is altered while the other features are substantially the same. The coupling element 106 is a pulse transformer PT, wherein the circuitry of the second controller 105 and the manner in which the control signal SQ is generated have been explained above and will not be described again. In this embodiment, the pulse transformer PT acts as a transmission medium for data signal interaction between the first controller 104 and the second controller 105, and has a primary side or a primary winding L _PT1 and a secondary side or second. The side winding L _PT2 , the primary side winding L _{PT1 is} connected to the second controller 105, and the secondary side winding L _{PT2 is} connected to the first controller 104. The primary side winding L _{PT1 is provided} with a first end for receiving the control signal SQ generated by the RS flip-flop 105a and a second end coupled to the reference ground potential VSS, and the second side winding L _PT2 having the first end The terminal can generate a first pulse signal S ₁ for driving the main switch Q1 and a second terminal for coupling to the ground GND, such as a different name. Although the control signal SQ is directly input to the first end of the primary side winding L _PT1 , and the output result of the first end of the secondary side winding L _PT2 is directly feasible as the first pulse signal S _{1 ,} in order to protect The signal is not misdirected and the present invention provides the embodiment of Figure 7A. The control signal SQ can be transmitted to the input of a buffer A4, and the output of the buffer A4, that is, the node N ₅ and the first end of the primary winding L _PT1 is connected with a capacitor C ₅₂ , the primary side winding L _PT1 a second terminal connected at node N ₇ to a lower reference potential or said ground potential VSS. A capacitor C ₅₁ is connected between the first end of the secondary side winding L _PT2 and a signal generating node N _S for outputting the first pulse signal S ₁ , and the second end of the secondary side winding L _PT2 is at a node N ₆ Connect to ground GND. And optionally connecting a cathode of a diode D ₅₁ to the node N _S and an anode connected to the ground GND at the node N ₆ , and optionally connecting a resistor between the node N _S and the node N ₆ R ₅₁ . The working mechanism of the pulse transformer PT is embodied in that the capacitor C ₅₂ isolates the direct current, and when the control signal SQ is turned to a high level, the capacitor C _{52 is} charged, and the first end of the primary side winding L _PT1 is also raised as the potential of the terminal. Located in the transmission interface of the primary winding L _PT1 at the first end node of FIG. 7B TX1 + voltage waveform V _TX1 coarse, primary winding L _PT1 considered node at a second end TX2 - transmission interface, a control signal pulse transformer PT The SQ is transferred to the secondary side winding L _PT2 , and the first end of the secondary side winding L _PT2 is also lifted like the terminal end, as shown in FIG. 7B at the receiving interface RX1+ at the first end node of the secondary side winding L _PT2. The coarse waveform of _RX1 is regarded as the receiving interface RX2- at the node of the second end of the secondary side winding L _PT2 . In this process, the potential of the node N _S is also synchronously raised due to the coupling of the capacitor C ₅₁ . If the Schottky diode D ₅₁ is used, the clamping effect of the diode D ₅₁ can also make the potential of the node N _S It rapidly increases to output a high-level first pulse signal S ₁ at the node N _S . Conversely, once the control signal SQ is turned low, the capacitor C ₅₂ is discharged through the primary side winding L _PT1 , and the capacitor C ₅₁ is also discharged through the secondary side winding L _PT2 and the resistor R ₅₁ , so that the signal generating node The potential of N _S drops rapidly, thereby generating a low-level first pulse signal S ₁ at the signal generating node N _S , and the first pulse signal S ₁ changes synchronously as the logic state of the control signal SQ is inverted. The second pulse signal S ₂ is an inverted signal of the first pulse signal S ₁ , and the waveform diagram is as shown in FIG. 7B .

Referring to FIG. 7C, this embodiment is slightly different from FIG. 7A. In the embodiment of FIG. 7A, the inverting input terminal of the first comparator A1 in the second controller 105 is input with the feedback voltage V _FB or the sensing voltage V. One of the _CSs , but the output of the filter 105g and the output of the amplifier 105h in the embodiment of Fig. 7C are added by an adder 105i and then fed to the inverting input of the first comparator A1. Ripple actual waveform ripple voltage at the output node N ₂₀ of the embodiment shown in FIG. 8 in the output node N ₂₀ or FIG. 1 is later described in detail with upcoming AC component and a DC component, ripple The average voltage value of the voltage corresponds to the voltage level of the DC component, and the total ripple voltage minus the voltage value of the DC component is substantially equal to the voltage value of the AC component. Since the feedback voltage V _FB is the divided voltage value taken at the output node N ₂₀ , it is essentially a partial voltage of the actual ripple voltage. Further characterization of the sensing voltage V _CS is the magnitude of the load current I _O, showing a direct current component DC load current I _O characteristics is much greater than with alternating current component with it, so that the sensing voltage V _CS is cross A DC signal whose average voltage value is equal to the voltage value of its DC component. In Fig. 7C, the actual ripple voltage is supplied to a filter 105g for filtering out the DC component of the actual ripple voltage and retaining and outputting only the AC component. It can be considered that the filter 105g will feed back the voltage V _FB . The total voltage value minus the voltage value of the DC component among them gives the voltage value of the AC component among them. In FIG. 7C, the voltage drop generated by the load current I _O on the sense resistor R _C , that is, the sense voltage V _CS is supplied to an amplifier 105h, and the sense voltage V _CS is amplified by the amplifier 105h and output. The filter 105g outputs a signal of the AC component obtained by filtering out the DC component of the feedback voltage V _FB to the adder 105i, and the amplifier 105h outputs the signal with the AC component and the DC component amplified by the sensing voltage V _CS to the adder. 105i, the adder 105i adds the signal output from the filter 105g and the signal output from the amplifier 105h to the inverting input terminal of the first comparator A1. The embodiment of Figure 7C is identical to Figure 7A except that the inverting input of the first comparator A1 is not the direct feedback voltage V _FB or the sense voltage V _CS . And the adder 105i adds the signal output from the filter 105g and the signal output from the amplifier 105h to the inverting input terminal of the first comparator A1 to replace the feedback voltage of the inverting input terminal of the first comparator A1. V _FB or sense voltage V _{CS is} also applicable to the embodiment of Figures 6A and 6C.

Referring to Figure 8, the maximum difference between the embodiment of FIG. 1 in this embodiment is a secondary winding L _S as a first end connected to the dotted end of the output node N ₂₀ by a rectifying diode D _REC. And the synchronous switch Q2 in FIG. 1 can also be discarded. At this time, the second end of the secondary side winding L _S can be directly coupled to the reference ground potential VSS as the name terminal. The anode of the rectifying diode D _REC is connected to the first end of the secondary side winding L _S and the cathode is connected to the output node N ₂₀ , and the starting voltage ST can be drawn from the cathode of the rectifying diode D _REC . If the synchronous switch Q2 is canceled, it is not necessary to generate the second pulse signal S ₂ . Otherwise, the operational working mechanism of FIG. 8 is the same as that of FIG. 1 and will not be described here.

In the voltage converter, if the load 18 becomes light or no load, the load current I _O will be significantly reduced, which also causes the switching frequency f of the main switch Q1 to decrease, and the light load of the load 18 mentioned here is light load. The situation or the empty load is relative to its overloaded Heavy load case. Moreover, the switching frequency f is closely related to whether the voltage converter enters the audio zone. If the switching frequency f is too low, parasitic oscillation will occur. For example, if the electric user hears the howling sound from the transformer, the switching frequency f may be reduced to about 20 Hz.

Referring to Fig. 9, in this embodiment, the audio converter adaptively determines the audio discomfort caused by the reduction of the switching frequency f. Regardless of the embodiment of FIG. 6A or FIG. 7A or FIG. 7C, one of the feedback voltage V _FB or the sensing voltage V _CS or the signal output by the adder 105i is regarded as the detection signal DE, so the detection signal DE can be used. To characterize the instantaneous magnitude of the output voltage V _O and/or the load current I _O provided to the load 18. The detection signal DE is input to the inverting input terminal of the first comparator A1, and the first reference voltage value V _{REF is} input to the non-inverting input terminal of the first comparator A1, and when the detection signal DE is lower than the first reference voltage value At V _REF , the high level of the output of the first comparator A1 sets the set terminal S of the RS flip-flop 105a, and the RS flip-flop 105a starts outputting the control signal SQ of the high level, and the high-power is generated when the on-time generator 105c is generated. When the flat signal S _{ON is} supplied to the reset terminal R of the RS flip-flop 105a, the RS flip-flop 105a starts outputting the control signal SQ of the low level, which has been described in detail above and will not be described again. In the embodiment of Fig. 9, only a portion of the components of the voltage converter are illustrated, while an optional but non-essential embodiment of the on time generator 105c is also deliberately shown. In FIG. 9 and FIG. 10, once the detection signal DE is lower than the first reference voltage value V _REF , the timing at which the control signal SQ transitions from the low level to the high level triggers the one shot 115b to be issued. Clock signal CLK. In the embodiment of FIG. 10, two adjacent time periods in which the detection signal DE is lower than the first reference voltage value V _REF are taken as an example. For example, a detection signal DE occurs in a first time period TIME1 (for example, some A detection signal DE1) is lower than the first reference voltage value V _REF , at which time the voltage converter modulates the output voltage V _O and/or the load current I _O by generating the control signal SQ1 to turn on the main switch Q1. Therefore, by the voltage modulation, the end period detection signal DE of the first period TIME1 just returns to a state larger than the first reference voltage value V _REF , and then the detection signal DE occurs in a second period TIME 2 (for example, a certain detection) When the signal DE2) is lower than the first reference voltage value V _REF again, the voltage converter needs to control the increase of the output voltage V _O and/or the load current I _O by the control of the control signal SQ2 to turn on the main switch Q1. The modulation causes the second period TIME2 end point detection signal DE to return to be greater than the first reference voltage value V _REF , thus looping.

Referring to FIG. 10, during the first time period TIME1, the detection signal DE1 is lower than the first reference voltage value V _REF . At the start time of the first time period TIME1, the high level comparison result of the first comparator A1 causes the RS flip-flop 105a to be set. The bit generates a high level control signal SQ1. At this moment, the control signal SQ1 is flipped from the previous low level to the rising edge of the high level, so that the monostable flip-flop 105b is clicked to emit a high-level narrow pulse. The clock signal CKL1, this process can be understood in conjunction with FIG. 6A and FIG. 7A or FIG. 7C. CKL1 clock signal generated by a monostable flip-flop 105b trigger timing generator 105c starts timer T _ON1 on-time, the signal S _ON1 A3 emitted from the third comparator in the main switch Q1 is turned ON time duration T _ON1 Is low. After the end of the on-time T _ON1 , the third comparator A3 in the on-time generator 105c issues a high-level signal S _ON1 as a reset signal, causing the RS flip-flop 105a to reset and inverting the control signal SQ1 to a low state. During the first time period TIME1, the main switch Q1 may have a plurality of switching periods instead of the number of illustrations, and a preset time period T _SET -A is counted from the start time point of the first time period TIME1, after one or more switches The period until the end of the preset time period T _SET -A, the detection voltage DE is larger than the first reference voltage V _REF according to the expected setting, and the control signal SQ1 is at a low level, and the time is followed by the clock signal CLK1. The next high-level narrow clock signal has not appeared yet, so the capacitor C _T has no transient discharge, and the signal S _ON1 output from the third comparator A3 is maintained at a high level.

Referring to FIG. 10, after the end of the first time period TIME1, due to the voltage modulation effect of the voltage converter, the detection signal DE is returned to a state greater than the first reference voltage value V _REF , and the comparison result of the first comparator A1 is Low level. After a period of time, the detection signal DE2 is again lower than the first reference voltage value V _REF in a second period TIME2, and the high level comparison result of the first comparator A1 causes the RS to be triggered at the start time of the second period TIME2. The controller 105a sets a control signal SQ2 that generates a high level. At this moment, the control signal SQ2 is flipped from the previous low level to the rising edge of the high level, so that the one shot 115b is clicked and emits a high level. The narrow pulse is also the clock signal CKL2. The clock signal CKL2 generated by the one-shot 115b triggers the capacitor C _{T to be} discharged lower than the third reference voltage V _P . At this time, the on-time generator 105c starts the timing of the on-time T _ON2 , and the main switch Q1 is turned on. S _ON2 signal on-time T _ON2 third comparator A3 emitted continuously at a low level. After the end of the on-time T _ON2 , the capacitor C _{T is} charged to exceed the third reference voltage V _P , and the third comparator A3 in the on-time generator 105c issues a high-level signal S _ON2 as a re-signal, allowing the RS flip-flop 105a Reset and turn control signal SQ2 to a low state. Also in the second time period TIME2, the main switch Q1 may have a plurality of switching periods instead of the number of illustrations, and one preset time period T _SET -B is timed from the starting time point of the second time period TIME2, after one or more The switching period until the end of the preset time period T _SET -B, the detection voltage DE is greater than the first reference voltage V _REF as expected to meet the load demand, at which time the control signal SQ2 is low, and the time Moreover, since the next high-level narrow clock signal subsequent to the clock signal CLK2 has not appeared yet, the capacitor C _T has no transient discharge, and the signal S _ON2 output from the third comparator A3 is maintained at the high level.

Referring to FIG. 9, the feedback voltage V _FB or the sense voltage V _CS or the output signal of the adder 105i generated by the adjacent previous preset time period T _SET -A and the subsequent preset time period T _SET -B will be low. Taking the case of the first reference voltage V _REF as an example, it is clarified how the present invention avoids the transformer T howling and directs the switching frequency f out of the audio zone when the switching frequency f is too low. Any one of the feedback voltage V _FB or the sensing voltage V _CS or the output signal of the adder 105i is regarded as the detection signal DE. In FIGS. 9 and 10, the clock signal CLK1 generated at the time of the control signal SQ1 in the previous preset period T _SET -A has the frequency value F because the number of high-level narrow pulses of the clock signal CLK1 may be more than the number of times during the period Once, so there may be one or more cases of frequency value F. In Fig. 9, a clock generator 113 is provided which includes at least an oscillator 113a which generates an oscillation signal and outputs it to the frequency divider 113b, and a frequency divider 113b which changes the frequency of the oscillation signal to provide An upper frequency threshold F _H and a lower frequency threshold F _{L are} output to the frequency comparator 114 as a reference frequency, whereby the frequency comparator 114 can increase the frequency value F of the clock signal CLK1 triggered by the rising edge of the control signal SQ1. It is compared with the upper frequency threshold F _H and the lower frequency threshold F _L . The counter 115 has an addition calculator and a subtraction counter, and the initial count value of the counter 115 can be pre-assigned. When a certain frequency value F is greater than the upper frequency threshold F _H , the limit counter 115 is decremented based on the initial value of the assigned count. 1. When a certain frequency value F is lower than the lower frequency threshold F _L , the limit counter 115 is incremented by 1 based on the initial value of the assigned count, so that whether the addition or the subtraction is performed is all compared by the frequency comparator 114. As a result, the result of the comparison is passed to the counter 115, by which the counter 115 executes the previously defined arithmetic rules. In the preset time period T _SET -A, according to the comparison of the magnitude of the corresponding frequency value F of each high-level narrow pulse clock signal CLK1 with the reference frequency, the counter 115 is sequentially incremented or decremented by one. Moreover, based on the number of types corresponding to the frequency value F (e.g., 5 different frequency values), the same number of counts (e.g., 5 counts) is executed by the counter 115, and the final counter 115 produces a total value. In addition, the counter 115 is further defined with a counting condition, that is, the counter 115 is defined with an upper critical count value and a lower critical count value, and once the total value exceeds the upper critical count value, the defined total value is equal to the upper critical count value, or when When the total value is lower than the lower critical count value, the defined total value is equal to the lower critical count value. Or when the total value is equal to one of the upper critical count value or the lower critical count value, the defined total value does not need to be changed.

For ease of understanding, it is assumed that in an exemplary but non-limiting embodiment, a plurality of high-level narrow pulse clock signals CLK1 corresponding to five different frequencies within a preset time period T _SET -A may also be considered as a clock signal CLK1. The total number of frequency values F is five. In this case, the initial value of the count of the counter 115 is exemplified by the binary symbol BIT[00] embodied as a two-digit element, and the lower critical count value is defined as a two-ary binary symbol BIT[00] ], and the upper critical count value is defined as the two-ary binary symbol BIT [11]. When the total number of frequency values F of the clock signal CLK1 is five, each frequency value is compared with the frequency threshold value F _H and the lower frequency threshold value F _L according to the time node appearing, and is executed by the frequency comparator 114. The results obtained before and after comparison are assumed to be: the first frequency value is lower than the lower frequency threshold F _L , the second frequency value is higher than the upper frequency threshold F _H , and the third frequency value is lower than the lower frequency threshold F _L The fourth frequency value is higher than the upper frequency threshold F _H , and the fifth frequency value is lower than the lower frequency threshold F _L . According to the counting rule defined above, the counter 115 pairs the high-level narrow pulse clock signal CLK1 The number counting, the counting step performed by the counter 115 five times before and after the counting initial value BIT[00] is embodied in the comparison result triggering counter 115 of the frequency comparator 114 when the first frequency value is lower than the lower frequency threshold F _L frequency comparator when the counter is active and the adder adds 1 to the second frequency value higher than the upper frequency threshold comparison result F _H 114 triggers counter 115 and an effective subtraction counter decremented, the third frequency value is lower than the critical frequency F _L frequency comparison result adder 114 triggers counter 115 effectively counter and adding one, a fourth frequency higher than the frequency comparator when the comparison result of the threshold value F _H counter 114 triggers counter 115 is valid and the subtraction When the first frequency value and the fifth frequency value are lower than the lower frequency threshold value F _L , the comparison result of the frequency comparator 114 triggers the addition counter of the counter 115 to be valid and increases by 1, so that the initial value BIT[00] is counted one after another. The total value obtained after the total of five counts is BIT [01]. In another example, it is assumed that the above-mentioned count initial value BIT[00] and lower critical count value BIT[00] and upper critical count value BIT[11] are unchanged, but the range of five frequency values has changed. The counting step performed by the counter 115 five times before and after counting the initial value BIT[00] is embodied by: the comparison result of the frequency comparator 114 triggering the subtraction of the counter 115 when the first frequency value is higher than the upper frequency threshold F _H The counter is valid and decremented. 1. The second frequency value is higher than the upper frequency threshold F _H. The comparison result of the frequency comparator 114 triggers the subtraction counter of the counter 115 to be valid and decremented. The third frequency value is higher than the upper frequency threshold F. The comparison result of the frequency comparator 114 at the time _H triggers the subtraction counter of the counter 115 to be valid and decrements. The fourth frequency value is higher than the upper frequency threshold F _H. The comparison result of the frequency comparator 114 triggers the subtraction counter of the counter 115 to be valid and subtracted. 1. When the fifth frequency value is higher than the upper frequency threshold F _H , the comparison result of the frequency comparator 114 triggers the subtraction counter of the counter 115 to be valid and decremented by 1, in which case the total value is smaller than the lower critical count value BIT [ 00], so the assigned lower critical count value BIT[00] is ultimately considered as the total value. In another reverse example, it is assumed that the count initial value BIT[00] and the lower critical count value BIT[00] and the upper critical count value BIT[11] are unchanged, but the range of the five frequency values is changed, the counter 115 The counting step performed five times before and after counting the initial value BIT[00] is performed when the first frequency value is lower than the lower frequency threshold F _L and the comparison result of the frequency comparator 114 triggers the addition counter of the counter 115 to be valid and When the first frequency value is lower than the lower frequency threshold F _L , the comparison result of the frequency comparator 114 triggers the addition counter of the counter 115 to be valid and increases, and the frequency of the third frequency value is lower than the lower frequency threshold F _L . The comparison result of the comparator 114 triggers the addition counter of the counter 115 to be valid and increases 1. When the fourth frequency value is lower than the lower frequency threshold F _L , the comparison result of the frequency comparator 114 triggers the addition counter of the counter 115 to be valid and adds 1, five frequency values below the lower threshold frequency F _L when the comparison result of the frequency comparator 114 triggers counter 115 and adder plus an effective counter, in which case the total number is greater than the fifth threshold after the count Numerical BIT [11], so the assigned threshold count BIT [11] ultimately deemed total value.

Referring to FIGS. 9 and 10, the counter 115 described above counts the frequency value F of the clock signal CLK1 in the last preset time period T _SET -A, and the total value is finally transmitted and encoded/burned by the counter 115. Stored in a register 116. On the count of a predetermined frequency value _SET -A period T F. The significance of the next adjacent one of the predetermined conduction time period T _SET -A T _ON2 relative to the predetermined period T _SET -A the on-time T _ON1 is adjusted, and the basis for implementing the adjustment is the total value corresponding to the frequency value F. Adjusting the on-time T _ON2 manner Referring to Figure 9, generator 105c to the on-time of FIG. 9, includes a fixed current source 110 and the two optional additional current sources 111 and 112, further comprising a third switch SW ₅₁ And a capacitor C _T , the supply voltage V _DD provides an operating voltage for the fixed current source 110 and the two additional current sources 111, 112. Wherein the output current I ₀ 110 fixed current source directly to the node N _T C _T at the end and can continue the charging to the capacitor C _T, C _T relative to the other end of the capacitor connected to the ground terminal GND. But the connection between the node N _T additional current sources 111 and the capacitor C _T to an end of a fourth switch SW _61, a first terminal for receiving the fourth current source 111 outputs an additional switch SW ₆₁ of the current I ₁ and a second end connected to the node N _T, only the control terminal of the fourth switch SW ₆₁ receives a high level so that the fourth switch SW ₆₁ is turned on, additional current source 111 will be output from the current I ₁ from the N _T C _T is the capacitance at node Charging. Similarly current, is connected between the node N _T additional current source 112 and another capacitor C _T to the other end of the fifth switch SW _62, a first output terminal for receiving an additional current source 112 of the fifth switch SW ₆₂ and the I ₂ a second terminal connected to node N _T, only the control terminal of the fifth switch SW ₆₂ receives a high level such that the fifth switch SW ₆₂ is turned on, additional current source 112 outputs a current I ₂ at the node N _T will Charge the capacitor C _T . A first terminal connected to a third voltage to current converter switches 105c-2 SW ₅₁ to node N _T and a second end connected to the ground terminal GND so that the third switch SW ₅₁ and the capacitor C _T is the parallel relationship, the third a control input terminal of the switch SW ₅₁ monoflop 105b a predetermined high level by the rising edge of the clock signal CLK1 to the control signal SQ1 is formed within a period T _SET -A on, the third switch SW ₅₁ is connected to a transient If the capacitor C _{T is} stored at one end, that is, the node N _T , the charge is released at the moment when the third switch SW ₅₁ is turned on, so the output of the third comparator A3 generates a low level at this time. The signal S _ON1 . After the rising edge of the control signal SQ1 high-level clock signal CLK1 pulse is narrow down to a low level, a fixed current source 110 to begin charging node capacitance C _T N _T, if the fourth switch SW ₆₁ is turned the additional current sources 111 and a fixed current source 110 with charging capacitor C _T to node N _T, if the fifth switch SW ₆₂ is turned the additional current source 112 and a fixed current source 110 charges the capacitor C _T N _T nodes together. CKL1 clock signal generated by a monostable flip-flop 105b trigger timing generator 105c starts timer T _ON1 on-time, the signal S _ON1 A3 emitted from the third comparator in the main switch Q1 is turned ON time duration T _ON1 Is low. Once the capacitor C _T continuously charged during the on-period T _ON1, after the conduction period T _ON1 voltage N _T at the node capacitance C _T starts than the third reference voltage V _P so large that the output of the third comparator A3 is generated The signal S _ON1 is flipped to a high level within the off period T _OFF1 at the end of the on period T _ON1 , and the signal S _{ON1 is} again input to the reset terminal R of the RS flip flop 105a, so the high level signal S _ON1 is reset The RS flip-flop 105a causes the control signal SQ1 generated at the Q output to fall from the high level in the on period T _ON1 to the low level in the off period T _OFF1 , thereby turning off the main switch Q1. If the main switch Q1 detects that the voltage DE is still lower than the first reference voltage V _REF after the first switching cycle, the main switch Q1 will start to execute the second switching cycle, and so on, until the preset time period T _SET -A At the end, the detection voltage DE is intended to be larger than the first reference voltage V _REF as expected. According to this switching mode, the main switch Q1 is turned on during the on period T _ON1 and turned off during the off period T _OFF1 , and can be looped multiple times throughout the preset period T _SET -A.

The second controller 105 generates a high-level narrow pulse of the control signal SQ2 in the next preset time period T _SET -B and the timing of the rising edge thereof according to the total value of the counter 115 in the last preset time period T _SET -A CLK2. This working mechanism is embodied in that if the switching frequency f is too low in the last preset time period T _SET -A, the transformer T enters the audio zone of the howling, so that the final total value of the counter 115 is greater than the preset due to the accumulated algorithm. An initial count value, which is stored in the register 116, and the binary symbol written by the register 116 is used as a control signal for controlling whether the electronic switch, that is, the fourth switch SW ₆₁ and the fifth switch SW ₆₂ are turned on, Once the switching frequency f is too low, the total value is greater than the initial count value. For example, the total value written by the register 116 is the bit BIT[01], or the upper critical count value BIT[11] regarded as the total value is written, and the ratio is initial. The value symbol BIT[00] is large.

According to the example described above, the total value BIT[01] is used as the control signal of the fourth switch SW ₆₁ and the fifth switch SW ₆₂ , and the higher bit 0 controls the fourth switch SW _{61 to be} turned off, and the lower bit 1 The fifth switch SW _{62 is} controlled to be turned on. Or the total value BIT[11] is used as the control signal of the fourth switch SW ₆₁ and the fifth switch SW ₆₂ , the higher bit 1 controls the fourth switch SW _{61 to be} turned on, and the lower bit 1 controls the fifth switch SW ₆₂ Turn on. It should be noted that the on-time generator 105c in FIG. 9 merely shows a schematic diagram of the modeling, and some common-sense contents are not shown. For example, the control signal data of the register is known in some embodiments. It is necessary to first decode through the decoder and then use a set of decoded signals to effectively turn the corresponding switch on or off.

DE occurs when the detection voltage is lower than the first reference voltage V _{REF SET} -B within a next predetermined period T, the rising edge of the high level narrow pulse control signal SQ2 within the preset period T _SET -B trigger clock Once the signal CLK2 so that the third switch SW ₅₁ is turned on transient, the charge at the node N _T relieved by the storage capacitance C _T of the third switch SW _51, the output terminal of the third comparator A3 is generated at this time Low level signal S _ON2 . After the rising edge of the control signal SQ2 clock signal CLK2 of a high level narrow pulses down to a low level, a fixed current source 110 to begin charging node capacitance C _T N _T, if the fourth switch SW ₆₁ is turned the additional current sources 111 and also with fixed current source 110 to the charging node capacitance C _T N _T, if the fifth switch SW ₆₂ is turned the additional current source 112 and a fixed current source 110 charges the capacitor C _T N _T nodes together. The total value BIT[01] of the register 116 controls the fourth switch SW _{61 to be} turned off to control the fifth switch SW _{62 to be} turned on, so the current I ₂ outputted by the additional current source 112 and the current I ₀ outputted by the fixed current source 110 are directly delivered to The capacitor C _T is charged at one end node N _T of the capacitor C _T , and it is apparent that the sum of the currents (I ₀ +I ₂ ) is faster than the simple current I ₀ , and the following preset period T _SET -B is relative to The last preset time period T _SET -A can quickly fill the capacitor C _T faster. By the same token, the total value BIT[11] of the register 116 controls the fourth switch SW ₆₁ and the fifth switch SW _{62 to be} turned on, so the current I ₁ output by the additional current source 111, the current I ₂ output by the additional current source 112, and the fixed current 110 output from the current source I ₀ is directly supplied to node N _T at the end of the capacitor C _T is the capacitance C _T charge, apparently sum of the currents _{(I 0 + I 1 + I} 2) with respect to a simple current I ₀ charge faster, Therefore, the capacitor C _T can be quickly filled up faster in the next preset time period T _SET -B relative to the last preset time period T _SET -A. CKL2 clock signal generated by a monostable flip-flop 105b trigger timing generator 105c starts timer T _ON2 on-time, the signal S _ON2 A3 emitted from the third comparator in the main switch Q1 is turned ON time duration T _ON2 Is low. Once the capacitor C _T continuously charged during the on-period T _ON2, after the conduction period T _ON2 voltage N _T at the node capacitance C _T starts than the third reference voltage V _P so large that the output of the third comparator A3 is generated The signal S _ON2 is flipped to a high level in the off period T _OFF2 at the end of the on period T _ON2 , and the signal S _ON2 is input to the reset terminal R of the RS flip-flop 105a again, so the high level signal S _ON2 is reset The RS flip-flop 105a causes the control signal SQ2 generated at its Q output to fall from the high level in the on period T _ON2 to the low level in the off period T _OFF2 , thereby turning off the main switch Q1. If the main switch Q1 detects that the voltage DE is still lower than the first reference voltage V _REF after the first switching cycle, the main switch Q1 will start to execute the second switching cycle, and so on, until the preset time period T _SET -B At the end, the detection voltage DE is intended to be larger than the first reference voltage V _REF as expected. According to this switching mode, the main switch Q1 is turned on during the ON period T _ON2 and turned OFF during the OFF period T _OFF2 , and can be looped multiple times throughout the preset period T _SET -B.

It goes without saying that an additional current source 111 and/or current source 112 are not introduced in the preset time period T _SET -A, but an additional current source 111 and/or current source 112 are introduced in the preset time period T _SET -B. Therefore, the conduction time period T _{ON2 in the} preset time period T _SET -B is larger because the charging current is larger, the charging time speed of the capacitance C _T is faster than the conduction period T _ON1 and the voltage at the node N _T is faster than the third reference voltage. V _{P is} large, and as a result, the subsequent conduction period T _{ON2 is} smaller than the conduction period T _ON1 . Considering that the switching frequency f of the main switch Q1 decreases as the conduction period T _ON increases or increases as the conduction period T _ON decreases, when the load 18 is lightly loaded or unloaded, the switch of the conduction period T _ON1 phase When the frequency f is too small to cause the transformer T to enter the howling audio zone, since the subsequent conduction period T _ON2 becomes smaller, the value of the switching frequency f is appropriately increased, and the transformer T is released from the howling audio zone.

The relative magnitude relationship between the substantially ON period T _ON1 and the ON period T _ON2 is highly correlated with the count initial value of the counter 115. In the exemplary but non-limiting embodiment, the fourth switch SW ₆₁ or the fifth switch SW is the BIT [01] or BIT [10] during the preset time period T _SET -A phase counter 115. ₆₂ one of them will be turned on and the other will be turned off, then the current I ₁ output by the additional current source 111 or the current I ₂ output by the additional current source 112 will be together with the current I _{0 of the} fixed current source 110 during the on period T _{In the ON1} phase, the capacitor C _{T is} charged, and the total charging current value is (I ₁ +I ₀ ) or (I ₂ +I ₀ ), and the initial value of the count is BIT[01], for example, in the initial value BIT[01 On the basis of the above, the counting steps performed five times before and after the order of occurrence of different frequencies are: the first frequency value > the upper frequency threshold F _H , the comparison result of the frequency comparator 114 triggers the subtraction counter of the counter 115 to be valid and Decrease 1, the second frequency value < lower frequency threshold F _L , the comparison result of the frequency comparator 114 triggers the addition counter of the counter 115 to be valid and adds 1, the third frequency value > the upper frequency threshold F _H frequency comparator The comparison result of 114 triggers the subtraction of the counter 115 And is decremented when valid, <threshold frequency F _L when the comparison result of the frequency comparator 114 triggers counter 115 and effectively counter plus 1 adder, a fifth frequency value> fourth threshold frequency value of the frequency F _H on The comparison result of the frequency comparator 114 triggers the subtraction counter of the counter 115 to be valid and decremented by 1, in which case the final total value is BIT[00], that is, the total charging current for the capacitor C _T charging total during the conduction period T _ON2 phase. value I _0, the capacitance C _T charge conduction period T _ON2 phase total time required is larger than the capacitance C _T charged in the conduction period T _ON1 phase time, corresponding to the conduction period T _ON2 is to be greater than the conduction period T _ON1, Thereby, the switching frequency f is adjusted from a larger value of the preset time period T _SET -A to a smaller value of the preset time period T _SET -B.

In summary, in the previous preset time period T _SET -A in FIG. 10, the control signal SQ1 of the second controller 105 on the secondary side is transmitted to the first controller 104 on the primary side through the coupling element 106, so that The first pulse signal S ₁ generated by a controller 104 controls the main switch Q1 to have an on-time T _ON1 in the switching period. In the latter predetermined time period T _SET -B in FIG. 10, the control signal SQ2 of the second controller 105 on the secondary side is transmitted to the first controller 104 on the primary side through the coupling element 106, so that the first controller 104 generates The first pulse signal S ₁ controls the main switch Q1 to have an on-time T _ON2 in the switching period. When the preset period T _SET -A counter 115 triggers the rising edge of the control signal SQ1, the number of frequency values F of the CLK1 is counted according to the counting rule, and the calculated final total value is greater than the initial count value, so that the latter preset period On-time T _{ON2 in} T _SET -B < On-time T _ON1 . Vice versa, when the calculated total value is less than the initial count value, the on-time T _ON2 > the on-time T _{ON1 in the} latter preset time period T _SET -B is made. When the calculated final total value is equal to the initial count value, the on-time T _{ON2 in the} latter preset time period T _SET -B is made to be the on-time T _ON1 . The reason is that the total value is updated once every time the detection voltage DE is lower than the first reference voltage V _REF , and the symbols in the total value directly determine the switching of the switches SW ₆₁ and SW ₆₂ . no. That is, when the next occurrence of the detection voltage DE is lower than the first reference voltage V _REF , the total value calculated by the last detection voltage DE lower than the first reference voltage V _REF determines the next detection voltage. The conduction time of the stage where DE is lower than the first reference voltage V _REF . It should be noted that although the present invention is based on the two-symbol and two additional additional current sources 111, 112 as an example to explain the inventive spirit, in the actual topology, the initial value and the upper and lower count thresholds are counted. In fact, it is not limited by the number of two-bit symbols, and the number of additional current sources is not limited by the number of two branches.

In the above disclosure, the data transmission medium between the first and second controllers 104, 105, that is, the architecture of the pulse transformer PT employed by the coupling element 106 of the present invention is very important, in the corresponding diagram below. The structure of the pulse transformer PT will be described in detail in 11A to 13C.

Referring to Figure 11A, it is contemplated that all of the electronic components in the overall system of the voltage converter will be surface mounted or patched onto the PCB circuit board, and in this embodiment will be utilized as part of the physical structure of the pulse transformer PT. . It should be emphasized that the circuit board 200 in FIG. 11A is not a complete view of the PCB, and only shows the local area that needs to be used. An adjacent one of the first through holes 201 and one second through hole 202 are preliminarily formed on the circuit board 200 in a manner of drilling or etching or laser cutting, which penetrates the thickness of the circuit board 200. As an optional rather than an essential item, a strip-shaped slit 203 may also be formed in a region where the circuit board 200 is located between the first through hole 201 and the second through hole 202, and the slit 203 also penetrates the thickness of the circuit board 200. As an optional rather than an essential item, the first through hole 201 and the second through hole 202 are symmetrically arranged on the opposite sides of the slit 203, respectively, with the slit 203 as a center symmetry line. As an option, not an essential item, the first through hole 201 and the second through hole 202 are square. A spiral coil 202a is formed around the first through hole 201 on the surface of the circuit board 200, for example, as a primary side winding of the pulse transformer PT, and the spiral coil 202a has a plurality of concentric square-shaped conductive rings, the series of concentric squares. The conductive ring surrounds the first through hole 201, and the conductive rings of each turn are disposed on the same plane on the circuit board 200. The center position of the spiral coil 202a substantially coincides with the center position of the first through hole 201. Similarly, another spiral coil 202b is formed around the second through hole 202 on the same surface of the circuit board 200, for example, as a secondary side winding of the pulse transformer PT, and the spiral coil 202b has a plurality of concentric square-shaped conductive rings. The series of concentric square conductive rings surround the second through holes 202, and the conductive rings of the respective rings are disposed on the same plane on the circuit board 200. The center position of the spiral coil 202b and the center position of the second through hole 202 substantially coincide. The spiral coil 202a has a head end of the head end as a twist end and a head end having the opposite end end as a different name end. Similarly, the spiral coil 202b has a head end of the head end as a twist end and a head end having the opposite end end as a different name end. The topography or structure of the spiral coils 202a and 202b is various, for example, a spiral shaped back shallow groove is formed around the first through hole 201 on the upper surface or the lower surface of the circuit board 200, including from the inside to the outside. Concentric square trenches, when filled or embedded with conductive materials such as metal copper or the like in these concentric square trenches, a plurality of concentric square-shaped conductive rings can be formed as the spiral coil 202a. Similarly, a spiral shallow groove is formed around the second through hole 202 on the upper surface or the lower surface of the circuit board 200. When the conductive material is filled or embedded in the concentric square grooves, a plurality of concentric lines can be formed. A square shaped conductive ring acts as a helical coil 202b. In various other alternative embodiments, the helical coil 202a or 202b is directly mounted to the upper surface of the circuit board 200, such as by adhesion, deposition, sputtering, plating, etc., including a series of multi-turn concentric square metal coils. For example, they are plated with a metal material simultaneously with other metal wiring or wire diameter TRACE on the circuit board 200. Although the figure is exemplified by a square spiral coil 202a or 202b, in other embodiments not illustrated, the coils of the spiral coil 202a or 202b may be provided in a series of concentric rings or various polygonal shapes or the like. Although FIG. 11A only draws a single-layered helical coil 202a or 202b, in other alternative embodiments, for the helical coil 202a, a plurality of unillustrated helical coils may be disposed inside the circuit board 200. The spiral coils 202a of the top or bottom layer are aligned and aligned in a direction perpendicular to the circuit board 200, so that the spiral coils of different levels are arranged in parallel with each other, and these additional additions inside the circuit board 200 are performed. A spiral coil (not shown) is disposed around the first through hole 201 like the spiral coil 202a. Also for the spiral coil 202b, a plurality of layers of unillustrated helical coils may be disposed inside the circuit board 200 to coincide with the top or bottom spiral coils 202b in a direction perpendicular to the circuit board 200, so that different The hierarchical spiral coils are disposed in a plane-parallel manner with each other, and at this time, these additional spiral coils (not shown) inside the circuit board 200 are arranged around the second through holes 202 like the spiral coils 202b. In a multi-layer helical coil structure, different levels of helical coils are spaced apart and laminated with an insulating layer belonging to the printed circuit board 200 to be electrically insulated, but any two spiral coils adjacent to each other must satisfy An interconnection condition: the second end (or first end) of the previous helical coil must pass through the interconnection built into the circuit board 200 at the first end (or the second end) of the adjacent next helical coil The line is electrically connected, and these multi-layer spiral coils are connected in series. For example, in a multi-layer helical coil, the first end (or the second end) of the first spiral coil of the top or bottom layer serves as an equivalent end of the same name (or a different name) of the plurality of helical coils, and the bottom layer or The second end (or first end) of one of the last helical coils of the top layer serves as the equivalent different end (or the end of the same name) of the plurality of helical coils.

Referring to Fig. 11A, the pulse transformer PT includes at least a U-shaped (or saddle-shaped) core skeleton 210 and a core skeleton 211 including a strip, and the core skeleton 210 includes side arm portions 210a extending in parallel in the same direction. And the side arm portion 210b further includes a middle portion 210c substantially perpendicular to the side arm portions 210a, 210b, the side arm portions 210a and 210b being respectively coupled to both sides of the middle portion portion 210c, substantially both the side arm portions 210a and 210b and the middle portion 210c is an integrated structure. When one side arm portion 210a of the U-shaped core bobbin 210 is inserted into the first through hole 201, the opposite side arm portion 210b of the U-shaped core bobbin 210 is correspondingly inserted into the second through hole 202, thereby The core bobbin 210 is mounted on the circuit board 200, and in order to form a closed magnetic circuit loop, it is also necessary to combine the core bobbin 211 with the core bobbin 210. In FIG. 11B, the core bobbin 210 is inserted from the front side of the circuit board 200, and the front end faces (or broken sections or cut faces) of the two side arm portions 210a, 210b of the core bobbin 210 are on the circuit board 200. The opposite side is closely attached to one surface of the core bobbin 211 to construct a magnetic circuit. It is worth noting that in order to avoid an understanding bias due to differences in terms or terms, the front end face END FACE of the side arm referred to herein is relative to the side face SIDE FACE of the side arm. A slit 204 is reserved between a side surface of one side arm portion 210a of the core bobbin 210 and a sidewall of the first through hole 201. Similarly, a side surface of the other side arm portion 210b of the core bobbin 210 and the second through hole 202 A gap 204 is also reserved between the side walls. In FIG. 11B, in view of the fact that the core bobbin 210 and the core bobbin 211 are polymerized together in a separable form, if the electronic device incorporating the pulse transformer PT is vibrated or dropped, the core skeleton may collapse. Preferably, some insulating glue is placed on the circuit board 200 to bond or hold the two on the circuit board 200 without sloshing. Note that the main function of the printed circuit board 200 herein is to install the above transformer T and the package wafer integrated with the first controller 104 and the package wafer integrated with the second controller 105, except for the PCB board. A corner area on 200 or a relatively rare area of a patch element is reserved for a position for perforation, and a first through hole 201 and a second through hole 202 are prepared to install a pulse transformer PT at the reserved position. . The main switch Q1 and the synchronous switch Q2 may be separately mounted on the PCB circuit board 200, or the main switch Q1 and the first controller 104 may be integrated in one package wafer and then mounted on the PCB circuit board 200, and/or The synchronous switch Q2 and the second controller 105 are integrated in one package wafer and then mounted on the PCB circuit board 200.

Referring to Fig. 12A, another structure of the pulse transformer PT still includes a U-shaped core bobbin 210 and a rectangular parallelepiped or square-shaped core bobbin 211, but has a first alternative to the helical coils 202a and 202b. Wafer 301 and a second wafer 302. The first wafer 301 of the flat square shape is disposed at a relatively near center position with a first central hole 314 penetrating the thickness of the first wafer 301, and the first wafer 301 further has at least two pins 312 and 313, the pin 312 And 313 are used for butt welding with pads on circuit board 200, such as by soldering with surface mount technology. The second wafer 302 of the flat square shape is provided with a second center hole 324 penetrating the thickness of the second wafer 302 near the center position, and the second wafer 302 further has at least two pins 322 and 323, pins 322 and 323 Used for butt welding with pads on circuit board 200. At this time, adjacent first through holes 201 and second through holes 202 are still formed on the circuit board 200. When the first wafer 301 is mounted on the circuit board 200, its square first center hole 314 should be aligned with the square first through hole 201 of the circuit board 200 when the second wafer 302 is mounted on the circuit board 200. Its second central aperture 324, such as a square, should be aligned with the square second via 202 of the circuit board 200. Since the first center hole 314 and the first through hole 201 overlap, one side arm portion 210a of the U-shaped core bobbin 210 can easily be inserted through the both, and the other side arm portion 210b of the U-shaped core bobbin 210 Correspondingly, the second central hole 324 and the second through hole 202 overlapped at the same time. In Fig. 12B, the core bobbin 211 is combined with the core bobbin 210, and the core bobbin 210 is inserted from the front side of the circuit board 200, and the front end faces of the two side arm portions 210a, 210b of the core bobbin 210 are respectively The other side of the opposite side of the circuit board 200 is closely attached to one surface of the core bobbin 211 to construct a magnetic circuit. Referring to FIG. 12B, a slit 204 is reserved between a side surface of one side arm portion 210a of the core bobbin 210 and a sidewall of each of the first through hole 201 and the first center hole 314, and the other side arm of the core bobbin 210 A slit 204 is also reserved between the side surface of the portion 210b and the sidewalls of each of the second through hole 202 and the second center hole 324.

Referring to FIG. 12C-1, the relationship between the first wafer 301 and the second wafer 302 is modified on the basis of FIG. 12A. In the embodiment of FIG. 12A, the first wafer 301 and the second wafer 302 are each a separate wafer, and they are independent wafers. It is necessary to patch the board 200 separately, but in the possible embodiment of FIG. 12C-1, the first wafer 301 and the second wafer 302 are integrally connected as a whole, and the first wafer 301 and the second wafer 302 can be used. The sync patch is mounted on the circuit board 200. In the top view of FIG. 12C-2, the first wafer 301 and the second wafer 302 are arranged side by side, wherein one corner 311a of the first wafer 301 and one corner 321a of the second wafer 302 are close to each other, and both They are connected together by a connecting portion 331. The other corner portion 311b of the first wafer 301 and the other corner portion 321b of the second wafer 302 are close to each other, and the two are connected together by the connecting portion 332. The connecting portions 331, 332 may be moved to other positions of the gap between the first and second wafers in addition to the corners of the wafer, as long as the first wafer 301 and the second wafer 302 of the interconnect are substantially coplanar, It can be mounted on the circuit board 200 at the same time.

Referring to Figure 12D, a perspective view of the first wafer 301 and the second wafer 302 is shown based on Figure 12A. The first wafer 301 includes a spiral wiring 315 and the second wafer 302 includes a spiral wiring 325, and the topography with respect to the spiral wirings 315 and 325 is separately shown in FIG. 12E. Optionally, in FIG. 12E, one substrate 317 is used to carry a germanium substrate 316, and the substrate 316 may also be used alone. The substrate 317 and the substrate 316 are respectively provided with holes at the center of the substrate 316. A spiral wiring 315 is disposed around the hole in the center position thereof, and the center position of the spiral wiring 315 substantially coincides with the center position of each of the substrate 317 and the substrate 316, because the spiral wiring 315 is a conductor and passes through the substrate 316. The insulating layer of the surface is insulated from the substrate 316. Another substrate 326 disposed side by side with the substrate 316 is carried by a substrate 327 which can be used alone. The substrate 327 and the substrate 326 are each provided with a hole at a central position thereof, and are wound on the upper surface of the substrate 326. The hole in its center position is arranged with a spiral wiring 325 in which the center position of the spiral wiring 325 substantially coincides with the center position of each of the substrate 327 and the substrate 326, since the spiral wiring 325 is a conductor, it is required to pass through the upper surface of the substrate 326. The insulating dielectric layer is insulated from the substrate 326. Here, the substrates 317 and 327 have various options to ensure the implementation of the present invention. In addition to the insulating substrate, a typical metal lead frame or the like may be used instead. Although FIG. 12E only draws a single layer of spiral wiring 315 or 325, in other alternative embodiments, for the substrate 316, a plurality of unillustrated spiral wirings and spirals may be disposed thereon. The wirings 315 are aligned and aligned in a direction perpendicular to the substrate 316 such that the different levels of spiral wiring are disposed in a plane-parallel manner with each other, and at this time, these additional spiral wirings are provided on the substrate 316 (not It is illustrated that it is arranged around the first central hole 314 like the spiral wiring 315. Also for the substrate 326, a plurality of layers of unillustrated spiral wiring may be disposed thereon to coincide with the spiral wiring 325 in a direction perpendicular to the substrate 316, so that different levels of spiral wiring are interposed. These are disposed in a plane-parallel manner with each other, and at this time, these additional added spiral wirings (not shown) on the substrate 326 are arranged around the second center hole 324 like the spiral wiring 315. In the architecture of a multi-layer spiral wiring, different levels of spiral wiring are spaced apart and an insulating dielectric layer (for example, ruthenium dioxide or the like) is disposed therebetween so as to be electrically insulated from each other, but adjacent to each other. The two spiral wires must satisfy an interconnection condition: the second end (or first end) of the last spiral wire must pass through the first end (or the second end) of the adjacent next spiral wire. The interconnection lines built into the insulating dielectric layer are electrically connected in such a manner that the multilayer spiral wirings are connected in series. For example, in a multi-layer spiral wiring, the first end (or the second end) of the first spiral wiring at the top or bottom layer serves as an equivalent end of the same name (or a different name) of the plurality of spiral wiring series structures, and is located The second end (or first end) of one end of the spiral wiring of the bottom layer or the top layer serves as an equivalent different name end (or the same name end) of the plurality of spiral wiring series structures.

Referring to FIGS. 12D and 12A, the first wafer 301 has a molding body 311, and the second wafer 302 has a molding body 321 . In the first wafer 301, the molding body 311 covers the substrate 316 and the spiral wiring 315 formed on the upper surface thereof, and if the substrate 317 is further provided, it is also covered by the molding body 311. One end of the spiral wiring 315 (like the name end) is connected to the adjacent substrate 317, the lead 312 of the substrate 316 by a wire 318 formed by wire bonding WIRE BONDING, and the opposite end of the spiral wiring 315 (such as a different name end) The other leads 318 formed by wire bonding WIRE BONDING are connected to the adjacent substrate 317, the lead 313 of the substrate 316, and the lead 318 also needs to be covered by the molding body 311. The portion of the lead 312 for receiving the lead 318 is covered by the molding body 311, but a portion of the lead 312 extends beyond the molding body 311 for soldering to the pad on the circuit board 200, the same pin. The portion 313 for receiving the lead 318 is covered by the molding body 311, but a portion of the lead 313 extends beyond the molding body 311 for butt welding with the pads on the circuit board 200. Similarly, in the second wafer 302, the molding body 321 covers the substrate 326 and the spiral wiring 325 formed on the upper surface thereof, and if the substrate 327 is further provided, it is also covered by the molding body 321 . One end of the spiral wiring 325 (like the name end) is connected to the adjacent substrate 327, the lead 322 of the substrate 326 by a wire 328 formed by wire bonding WIRE BONDING, and the opposite end of the spiral wiring 325 (such as a different name) The other leads 328 formed by wire bonding WIRE BONDING are connected to the adjacent substrate 327, the lead 323 of the substrate 326, and the lead 328 is also covered by the molding body 321 , for example, epoxy resin. Material preparation of the class. The portions of pins 322 and 323 for receiving leads 318 are covered by a molding 311, but each of pins 322 and 323 also has a portion extending beyond the molding 311 for interfacing with pads on circuit board 200. welding.

Referring to FIG. 12D and FIG. 12A, in the first wafer 301, a square first central hole 314 simultaneously penetrates the respective thicknesses of the molding body 311, the substrate 316, and the substrate 317 (if selected), and the first center hole 314 is basically Located at the center of each of the molding body 311, the substrate 316, and the substrate 317, the spiral wiring 315 serves as a primary side winding of the pulse transformer PT, and a series of concentric square conductive rings surround the first center hole 314, and is spirally The center position of the wiring 315 and the center position of the first center hole 314 substantially coincide. Correspondingly, in the second wafer 302, a square second central hole 324 simultaneously passes through the respective thicknesses of the molding body 321, the substrate 326, and the substrate 327 (if selected), and the second center hole 324 is substantially located in the plastic package. The center position of each of the body 321, the substrate 326, and the substrate 327, wherein the spiral wiring 325 serves as a secondary side winding of the pulse transformer PT, and a series of concentric square conductive rings surround the second center hole 324, and the spiral wiring The center position of the 325 and the center position of the second center hole 324 substantially coincide. For the embodiment of FIG. 12C-1 and FIG. 12C-2, in the molding process MOLDING step, the molding body 311 of the first wafer 301 and the molding body 321 of the second wafer 302 are simultaneously integrally molded, one corner of the molding body 311. The portion 311a and the corner portion 321a of the molding body 321 are adjacent to each other, are close to each other in position, and are bridged by the connecting portion 331 (also a molding material) therebetween, and the other corner of the molding body 311 311b is adjacent to one corner 321b of the molding body 321, and is positioned close to each other, and bridges the two by a joint portion 332 (also a molding material) therebetween. In the embodiment of FIG. 12B, a region between the first through hole 201 and the second through hole 202 on the circuit board 200 may be formed as a strip-shaped narrow slit 203 or may not be prepared. In the embodiment of FIGS. 12A to 12E, in the positional relationship, the middle portion 210c of the core bobbin 210 and the core bobbin 211 are both parallel to the plane in which the flat first wafer 301 and the second wafer 302 are located, and also in the circuit. The plates 200 are parallel, but the side arm portions 210a and the side arm portions 210b of the core frame 210 connected at both ends of the middle portion 210c are perpendicular to the plane in which the first wafer 301 and the second wafer 302 are located, and are also associated with the circuit board 200. vertical. When the first wafer 301 and the second wafer 302 are mounted on the circuit board 200, the substrate 316 and the substrate 317, the substrate 326 and the substrate 327, and the flat molded bodies 311, 321 for molding them are both the circuit board 200 Parallel.

Referring to Fig. 13A, another structure of the pulse transformer PT has a first wafer 401 and a second wafer 402. The first wafer 401 includes a U-shaped or saddle-shaped core skeleton 410, and the second wafer 402 includes a U. Shape or saddle-shaped core frame 420. In the first wafer 401, as shown in Fig. 13B, the core bobbin 410 includes parallel extending side arm portions 410a and side arm portions 410c further including a middle portion 410b substantially perpendicular to the side arm portions 410a, 410c, and the middle portion portion 410b is connected Between the side arm portions 410a, 410c. A first coil winding 415 is wound around the middle portion 410b, and one end of the first coil winding 415 (like the name end) is directly connected to the pin 412 by soldering or by various other connection methods, and the first coil winding 415 is opposite to the other. One end (such as a different name end) is directly electrically connected to the pin 413 by soldering or by various other connections, and the pins 412, 413 are adjacent to the core bobbin 410. The molding body 411 encapsulates the core bobbin 410 and the first coil winding 415, and the portion of the pin 412 for receiving the first coil winding 415 is covered by the molding body 411, but the pin 412 has a part. Extending beyond the molding body 411 for butt welding with the pads on the circuit board 200, the same portion of the pin 413 for receiving the first coil winding 415 is covered by the molding body 411, but the pin 413 is also A portion extends beyond the molding body 411 for butt welding with the pads on the circuit board 200. In the second wafer 402, as shown in Fig. 13B, the core bobbin 420 includes parallel extending side arm portions 420a and side arm portions 420c further including a middle portion 420b substantially perpendicular to the side arm portions 420a, 420c, and the middle portion portion 420b is connected Between the side arm portions 420a, 420c. A second coil winding 425 is wound around the middle portion 420b, and one end of the second coil winding 425 (for example, the same name end) is directly connected to the lead 422 by soldering or by various other connections, and the second coil winding 425 is opposite. The other end (such as a different name end) is directly electrically connected to the pin 423 by soldering or by various other connections, and the pins 422, 423 are adjacent to the core bobbin 420. The molding body 421 molds the core bobbin 420 and the second coil winding 425, and the portion of the pin 422 for receiving the second coil winding 425 is covered by the molding body 421, but the pin 422 has a part. Extending beyond the molding body 411 for docking soldering with the pads on the circuit board 200, the same portion of the pin 423 for receiving the second coil winding 425 is covered by the molding body 421, but the pin 423 is also A portion extends beyond the molding body 421 for butt welding with the pads on the circuit board 200. In the embodiment of FIGS. 13A to 13C, in the positional relationship, the middle portion 410b of the core bobbin 410, the side arm portions 410a, 410c are coplanar and parallel to the plane in which the flat first wafer 401 is located, and the core bobbin 420 is The midsection portion 420b and the side arm portions 420a, 420c are coplanar and parallel to the plane in which the flat second wafer 402 is located. And when the first wafer 401 and the second wafer 402 are mounted side by side on the circuit board 200, the core bobbin 410, the core bobbin 420, and the flat-shaped molding bodies 411, 421 corresponding to those used for molding them, and the circuit board 200 parallel.

Referring to Fig. 13A, for the core bobbin 410 and the core bobbin 420, the front end surface 410a-1 of the side arm portion 410a of the core bobbin 410 is required to be exposed from one side surface 411a of the molding body 411, and the front end surface 410a-1 is actually It is a cut surface or a broken cross section of the side arm portion 410a which is perpendicular to the longitudinal direction of the side arm portion 410a, and the front end surface 410c-1 of the side arm portion 410c of the core bobbin 410 is required to be from one side surface 411a of the molded body 411. The front end surface 410c-1 is actually a cut surface or a broken cross section which belongs to the side arm portion 410c and which is perpendicular to the longitudinal direction of the side arm portion 410c. And the front end surface 420a-1 of the side arm portion 420a of the core frame 420 is exposed from one side surface 421a of the molding body 421, and the front end surface 420a-1 is actually the length of the side arm portion 420a and the side arm portion 420a. A cutting surface or a broken section perpendicular to the direction is required to expose the front end surface 420c-1 of the side arm portion 420c of the core bobbin 420 from one side surface 421a of the molding body 421, and the front end surface 420c-1 actually belongs to A cut surface or a broken cross section of the side arm portion 420c that is perpendicular to the longitudinal direction of the side arm portion 420c. It is also defined that the side surface 411a of the molding body 411 must face the side surface 421a of the molding body 421 when the pulse transformer PT is used, wherein the facing side faces of the regulating side surface 411a and the side surface 421a are disposed so that the front end surface 410a of the side arm portion 410a of the core core 410 is disposed. -1 can be aligned with the front end face 420a-1 of the side arm portion 420a of the core bobbin 420, and also allows the front end face 410c-1 of the side arm portion 410c of the core bobbin 410 to be coupled to the side arm of the core bobbin 420 The front end face 420c-1 of the portion 420c is aligned so as to be along the side arm portion 410a of the core bobbin 410 to the side arm portion 420a of the core bobbin 420, and along the side arm portion 420c from the core bobbin 420 to the magnetic The side arm portion 410c of the core bobbin 410 builds a closed core magnetic circuit between the two core bobbins 410 and 420.

Referring to FIG. 13B, a method of using the pulse transformer PT, when the first wafer 401 and the second wafer 402 are mounted on the circuit board 200, the first wafer 401 and the second wafer 402 are brought close to each other until the first wafer 401 The side surface 411a of the molded body 411 touches one side surface 421a of the molding body 421 of the second wafer 402, and the side surface 411a and the side surface 421a are bonded to each other without a gap. At this time, the front end surface 410a-1 of the side arm portion 410a of the core bobbin 410 and the front end surface 420a-1 of the side arm portion 420a of the core bobbin 420 are fitted together without a gap, and the side arm portion 410c of the core bobbin 410 The front end surface 410c-1 and the front end surface 420c-1 of the side arm portion 420c of the core bobbin 420 are attached to each other without a gap. Corresponding to the positional relationship, the side arm portion 410a of the core bobbin 410 and the side arm portion 420a of the core bobbin 420 are butted, and the side arm portion 410c of the core bobbin 410 and the side arm portion 420c of the core bobbin 420 are butted, thereby The core bobbin 410 and the core bobbin 420 may be spliced to form a desired toroidal core structure.

Referring to FIG. 13C, this embodiment is slightly different from FIG. 13B. FIG. 13B restricts that the side surface 411a of the molding body 411 completely and closely fits the side surface 421a of the molding body 421, but in FIG. 13C, the first wafer 401 and the first wafer are When the two wafers 402 are mounted side by side on the circuit board 200, the first wafer 401 and the second wafer 402 are brought close to each other, but a slit 430 is left between the side surface 411a of the molding body 411 and the side surface 421a of the molding body 421. It is required that the side surface 411a of the molding body 411 of the first wafer 401 touches the side surface 421a of the molding body 421 of the second wafer 402 to face each other, and the front end surface 410a-1 of the side arm portion 410a of the core bobbin 410 and the magnetic core The front end faces 420a-1 of the side arm portions 420a of the skeleton 420 are face-to-face aligned with each other, and the front end face 410c-1 of the side arm portion 410c of the core bobbin 410 and the front end face 420c-1 of the side arm portion 420c of the core bobbin 420 Face to face alignment. Correspondingly, in the positional relationship, the side arm portion 410a of the core bobbin 410 and the side arm portion 420a of the core bobbin 420 are butted together with each other in a gap manner, and similarly, the side arm portion of the core bobbin 410 is similar. The 410c and the side arm portions 420c of the core bobbin 420 are butted to each other with a gap therebetween, so that the core bobbin 410 and the core bobbin 420 can be spliced to form a desired toroidal core structure, except that the side of the core bobbin 410 The arm portion 410a and the side arm portion 420a of the core bobbin 420 are broken and an air gap is formed at the disconnected position, and the side arm portion 410c of the core bobbin 410 and the side arm portion 420c of the core bobbin 420 are disconnected and An air gap is formed at the disconnected position, and an air gap between the front end surface 410a-1 and the front end surface 420a-1 and an air gap between the front end surface 410c-1 and the front end surface 420c-1 are used to prevent magnetic saturation. When an air gap is left in the magnetic core of the pulse transformer PT, since the magnetic permeability of the air is only a few thousandth of the magnetic permeability of the iron core, the magnetomotive force almost falls on the air gap, so that the air gap is left. The average magnetic permeability of the magnetic core will be greatly reduced, not only the residual magnetic flux density will be reduced, but also the maximum magnetic flux density can reach the saturation magnetic flux density, so that the magnetic flux increment is increased, and the transformer core is no longer prone to magnetic saturation. In this embodiment, an optional insulating material 450 is also filled in the gap 430 remaining between the side surface 411a of the molding body 411 and the side surface 421a of the molding body 421. The insulating material 450 can not only electrically isolate, but on the other hand It is also possible to effectively enhance the bonding strength of the first wafer 401 and the second wafer 402 on the circuit board 200.

The exemplary embodiments of the specific structures of the specific embodiments have been described above by way of illustration and the accompanying drawings. Various changes and modifications will no doubt become apparent to those skilled in the <RTIgt; Accordingly, the appended claims are to cover all such modifications and modifications The scope and content of any and all equivalents are intended to be within the scope and spirit of the invention.

T‧‧‧Power Stage Transformer
L _P ‧‧‧ primary side winding
L _PT1 ‧‧‧ primary side winding
L _PT2 ‧‧‧secondary winding
L _S ‧‧‧secondary winding
N ₁ ‧‧‧ nodes
N ₁₀ ‧‧‧Input node
N ₂ ‧‧‧ nodes
N ₂₀ ‧‧‧Output node
N ₃ ‧‧‧ nodes
N ₄ ‧‧‧ nodes
N ₅ ‧‧‧ nodes
N ₆ ‧‧‧ nodes
N ₇ ‧‧‧ nodes
N _T ‧‧‧ nodes
N _S ‧‧‧ node
V _IN ‧‧‧ input voltage
GND‧‧‧ ground terminal
Q‧‧‧output
Q1‧‧‧Main switch
Q2‧‧‧Synchronous switch
C _OUT ‧‧‧ output capacitor
L _AUX ‧‧‧Auxiliary winding
C _AUX ‧‧‧ capacitor
D11 to D14‧‧‧ diode
D _AUX ‧‧‧ diode
D ₅₁ ‧‧‧Schottky diode
D _REC ‧‧‧Rected Diode
V _AC ‧‧‧Sinusoidal AC voltage
V _IN ‧‧‧ input voltage
V _O ‧‧‧Output voltage
I _O ‧‧‧Load current
I _D ‧‧‧ primary current
L ₁ ‧‧‧Inductance
D ₁₁ , D ₁₂ , D ₁₃ , D ₁₄ , D ₂₁ , D ₂₂ , D ₃₁ ‧‧‧ diode
C ₁ and C ₂ ‧‧‧ capacitors
C ₁₁ ‧‧‧ capacitor
C ₁₂ ‧‧‧ capacitor
C _OUT ‧‧‧ output capacitor
Capacitance C _Y ‧‧‧
C _X ‧‧‧Safety Capacitor
C _IN ‧‧‧Input Capacitor
C _AUX ‧‧‧Auxiliary Capacitor
C ₂₁ and C ₂₂ ‧‧‧ coupling capacitors
C _T ‧‧‧ capacitor
C ₅₁ ‧‧‧ capacitor
C ₅₂ ‧‧‧ capacitor
VSS‧‧‧reference ground potential
V _CC ‧‧‧ voltage
V _S ‧‧‧ voltage
V _LIMIT ‧‧‧Limit voltage
V _FB ‧‧‧ feedback voltage
V _CS ‧‧‧ Sense pressure drop
V _REF ‧‧‧First reference voltage
V _TH ‧‧‧second reference voltage
V _TX1 ‧‧‧Charging voltage
V _RX1 ‧‧‧ voltage
V _SAM ‧‧‧Voltage sampling
V _DD ‧‧‧Power supply voltage
V _P ‧‧‧ third reference voltage
S ₁ ‧‧‧first pulse signal
S ₂ ‧‧‧second pulse signal
SQ‧‧‧ control signal
SQ2‧‧‧ control signal
S _ON ‧‧‧ signal
R ₁ , R ₂ , R ₃ , R ₄ and R ₅ ‧ ‧ resistance
R ₂₁ , R ₃₁ ‧‧‧ current limiting resistor
R ₄₁ ‧‧‧resistance
R _S ‧‧‧resistance resistor
R _D1 and R _D2 ‧‧‧resistors
R _C ‧‧‧Sensor resistance
CTRL‧‧‧ signal
JFET‧‧‧High-voltage starting element
SW ₃₁ ‧‧‧Control switch
SW ₄₁ ‧‧‧First switch
SW ₄₂ ‧‧‧Second switch
SW ₅₁ ‧‧‧third switch
SW ₆₁ ‧‧‧fourth switch
SW ₆₂ ‧‧‧ fifth switch
G‧‧‧ gate
S‧‧‧ source
ST‧‧‧Starting voltage
A1‧‧‧First comparator
A2‧‧‧Second comparator
A3‧‧‧ third comparator
A4‧‧‧ buffer
R‧‧‧Reset end
RX1+‧‧‧ receiving interface
RX2-‧‧‧ receiving interface
TX1+‧‧‧Send interface
TX2-‧‧‧Send interface
LOOP1‧‧‧ loop
LOOP2‧‧‧ loop
T _ON ‧‧‧ On time
T _OFF ‧‧‧Shutdown time
CLK1‧‧‧Narrow clock pulse
CKL2‧‧‧ clock signal
T _ON-MIN ‧‧‧Minimum constant on time
T _ON-MAX ‧‧‧Maximum constant on time
T _SET ‧‧‧Preset time period
f‧‧‧Switching frequency
Number of turns of NS‧‧‧ secondary side winding L _S
Number of turns of NP‧‧‧ primary side winding L _P
PT‧‧‧pulse transformer
DE‧‧‧Detection signal
TIME1‧‧‧First time
T _SET -A‧‧‧Preset time period
T _ON2 ‧‧‧ On time
F _H ‧‧‧frequency threshold
F _L ‧‧‧ frequency threshold
101‧‧‧Rectifier
103‧‧‧Shutdown snubber circuit
104‧‧‧First controller
105‧‧‧Second controller
105a‧‧‧RS trigger
105b‧‧‧Click circuit
105c‧‧‧ On-time generator
105c-1‧‧‧Sampling holder (S/H)
105c-2‧‧‧Voltage current converter
105d‧‧‧bias circuit
105e‧‧‧Inverter
105g‧‧‧ filter
105h‧‧Amplifier
105i‧‧‧Adder
106‧‧‧Coupling components
111, 112‧‧‧Additional current source
113‧‧‧clock generator
113a‧‧‧Oscillator
113b‧‧‧divider
114‧‧‧Frequency comparator
115‧‧‧ counter
116‧‧‧ Register
12, 14‧‧‧ Busbar
16‧‧‧primary side controller
17‧‧‧Optocoupler
18‧‧‧load
200‧‧‧ boards
201‧‧‧ first through hole
202‧‧‧Second through hole
202a, 202b‧‧‧ spiral coil
203‧‧‧ gap
210‧‧‧Magnetic core skeleton
210a, 210b‧‧‧ side arm
210c‧‧‧Mid section
211‧‧‧ magnetic core skeleton
22, 24‧‧‧ output line
301‧‧‧First chip
302‧‧‧second chip
311‧‧‧plastic body
312 and 313‧‧‧ pins
314‧‧‧First Center Hole
315‧‧‧Spiral wiring
316‧‧‧substrate
317‧‧‧Substrate
318‧‧‧Acceptance lead
321‧‧‧plastic body
321b‧‧‧ corner
322 and 323‧‧‧ pins
324‧‧‧ second central hole
325‧‧‧ spiral wiring
326‧‧‧Substrate
327‧‧‧Substrate
328‧‧‧Leader
332‧‧‧Connecting Department
401‧‧‧First chip
402‧‧‧second chip
410‧‧‧Magnetic core skeleton
410a, 410c‧‧‧ side arm
Middle section of 410b‧‧‧
411‧‧‧plastic body
411a‧‧‧ side
412, 413‧‧‧ pins
415‧‧‧First coil winding
420‧‧‧Magnetic core skeleton
420a, 420c‧‧‧ side arm
420c-1‧‧‧ front face
420b‧‧‧ mid section
421‧‧‧Flat plastic body
421a‧‧‧ side
422, 423‧‧‧ pin
425‧‧‧second coil winding
430‧‧‧ gap
450‧‧‧Insulation materials

The features and advantages of the present invention will become apparent from the following detailed description of the appended claims. Figure 2 shows the feedback network of the voltage converter using TL431 for feedback. Figures 3 to 4 are schematic diagrams of the coupling elements using capacitors and pulse transformers, respectively. Figure 5 is a starter module with the first driver on the primary side. Figure 6A is a diagram of the manner in which the second controller on the secondary side transmits a control signal to the first driver with a capacitive coupling element. Fig. 6B is based on Fig. 6A to generate first and second pulse signals as the output voltage or current magnitude changes. FIG. 6C is a mode in which the on-time of the main switch is adjustable in the second controller based on FIG. 6A. Fig. 6D is a waveform diagram of adjusting the on-time based on Fig. 6C. Figure 7A is a diagram of the manner in which the second controller on the secondary side transmits a control signal to the first driver with a pulse transformer. Fig. 7B is based on Fig. 7A to generate first and second pulse signals as the output voltage or current magnitude changes. Fig. 7C is a comparison of the output results of the introduced filter and amplifier based on Fig. 7A and then compared with the reference voltage. Figure 8 replaces the secondary side synchronous switch with a rectifying diode on the secondary side. Figure 9 is a diagram of adjusting the on-time of the main switch when the load becomes light. Figure 10 is a diagram showing the main switch on-time determined based on a control signal clamped by the previous control signal in Figure 9. 11A to 11B are views showing the structure of a pulse transformer in a first embodiment thereof. 12A to 12E show the structure of a pulse transformer in a second embodiment thereof. 13A to 13C show the structure of a pulse transformer in a third embodiment thereof.

T‧‧‧Power Stage Transformer

L _P ‧‧‧ primary side winding

L _S ‧‧‧secondary winding

N ₁₀ ‧‧‧Input node

N ₂₀ ‧‧‧Output node

V _IN ‧‧‧ input voltage

GND‧‧‧ ground terminal

Q1‧‧‧Main switch

Q2‧‧‧Synchronous switch

C _OUT ‧‧‧ output capacitor

L _AUX ‧‧‧Auxiliary winding

C _AUX ‧‧‧ capacitor

D _AUX ‧‧‧ diode

V _AC ‧‧‧Sinusoidal AC voltage

V _IN ‧‧‧ input voltage

V _O ‧‧‧Output voltage

I _O ‧‧‧Load current

L ₁ ‧‧‧Inductance

D ₁₁ , D ₁₂ , D ₁₃ , D ₁₄ , D ₂₁ , D ₂₂ ‧‧‧ diode

C ₁₁ ‧‧‧ capacitor

C ₁₂ ‧‧‧ capacitor

C _OUT ‧‧‧ output capacitor

C _AUX ‧‧‧Auxiliary Capacitor

VSS‧‧‧reference ground potential

V _FB ‧‧‧ feedback voltage

V _CS ‧‧‧ Sense pressure drop

S ₁ ‧‧‧first pulse signal

S ₂ ‧‧‧second pulse signal

R ₂₁ ‧‧‧ current limiting resistor

R _S ‧‧‧resistance resistor

R _D1 and R _D2 ‧‧‧resistors

R _C ‧‧‧Sensor resistance

ST‧‧‧Starting voltage

RX1+‧‧‧ receiving interface

RX2-‧‧‧ receiving interface

TX1+‧‧‧Send interface

TX2-‧‧‧Send interface

101‧‧‧Rectifier

103‧‧‧Shutdown snubber circuit

104‧‧‧First controller

105‧‧‧Second controller

106‧‧‧Coupling components

12, 14‧‧‧ Busbar

18‧‧‧load

Claims (18)

A voltage converter comprising a primary winding of a transformer and a main switch connected in series between an input voltage and a ground, the secondary winding of the transformer being connected to an output node and a reference ground for supplying an output voltage to the load Between potentials; and a first controller for generating a first pulse signal to drive the main switch to switch between on and off; a second controller that characterizes the output voltage and/or characterizes the load current The detection voltage is compared with a first reference voltage, and the logic state of a control signal generated by the comparison result is determined by the comparison result; a coupling element is connected between the first controller and the second controller, and the logic of the control signal is The state is passed to the first controller such that the first controller determines the logic state of the first pulse signal based on the logic state of the control signal. The voltage converter of claim 1, wherein the detection voltage is input to the inverting input terminal of the first comparator of the second controller, and the first reference voltage is input to the non-inverting input terminal; At the first reference voltage, the high level comparison result of the first comparator sets the RS flip-flop of the second controller, so that the control signal output by the RS flip-flop is flipped from a low level to a high level; The on-time generator starts timing from the time when the control signal is flipped from the low level to the rising edge of the high level, and the timing is completed until the time when the preset on-time ends, and the signal output by the on-time generator is low when the timing is completed. Flip to high and reset the RS flip-flop to toggle the control signal from high to low. The voltage converter of claim 2, wherein the first and second switches are connected in series between a bias circuit of the second controller and the reference ground potential, and the first and second switches are interconnected. At a common node, the first switch is driven by the control signal and the second switch is driven by the inverted signal of the control signal; the connection between the non-inverting input of the second comparator of the first controller and the common node is coupled a first capacitor of the component, an inverting input of the second comparator, a second reference voltage, a resistor connected between the non-inverting input of the second comparator and the ground, and a second capacitor belonging to the coupling component connected to the ground Between the reference ground potential and the ground potential. The voltage converter of claim 3, wherein when the control signal is at a high level, the first switch is turned on and the second switch is turned off, and the voltage provided by the bias circuit is applied to the common node, and is pulled by the coupling element. The voltage of the positive input of the high second comparator is greater than the second reference voltage, and the second comparator outputs the first pulse signal of the high level; when the control signal is low, the first switch is turned off and the second switch is turned on, The potential at the common node is clamped to a reference ground potential, the voltage of the second comparator non-inverting input is pulled lower by the coupling element to be lower than the second reference voltage, and the second comparator outputs a first pulse signal of a low level. The voltage converter of claim 2, wherein the coupling element is a pulse transformer, and the control signal is transmitted to one end of the primary side winding of the pulse transformer through a coupling capacitor in the second controller, and the primary side winding is further One end is connected to the reference ground potential; a signal generating node in the first controller is connected with a coupling capacitor between one end of the secondary side winding of the pulse transformer, and the other end of the secondary side winding is connected to the ground end, thereby The signal generating node generates a first pulse signal that is consistent with the logic state of the control signal. The voltage converter of claim 5, wherein a resistor and a diode are arranged in parallel between the signal generating node and the ground, and the cathode of the diode is connected to the signal generating node. The anode is connected to the ground. The voltage converter according to claim 2, wherein an anode of a rectifying diode is connected to one end of a secondary winding of the transformer, a cathode of the rectifying diode is connected to an output node, and a secondary side of the transformer The opposite end of the winding is directly connected to the reference ground potential. The voltage converter according to claim 2, wherein one end of the secondary winding of the transformer is directly connected to the output node, and a connection between the opposite end of the secondary winding of the transformer and the reference ground potential is synchronized. a switch, wherein: the synchronous switch is driven by a second pulse signal generated by the second controller and having an inverted signal with the first pulse signal, and the synchronous switch is turned off when the main switch is turned on and when the main switch is turned off Turning on the synchronous switch; or the synchronous switch is driven by a second pulse signal generated by the second controller, and the synchronous switch is turned off by the second pulse signal when the first pulse signal controls the main switch to be turned off . The voltage converter of claim 8, wherein one of the on-time generators samples and holds the secondary winding of the transformer during a phase in which the main switch is turned on but the synchronous switch is turned off. The voltage value of the end connected to the synchronous switch, a voltage current converter of the on-time generator converts the sampled voltage value into a current to charge a charging capacitor in the on-time generator; a third in the on-time generator The switch and the charging capacitor are connected in parallel between a charging node and the ground, and the voltage at the charging node is input to the non-inverting input of the third comparator in the on-time generator and is input to the inverting input of the third comparator. a third reference voltage; and a one-shot of the second controller triggered by the rising edge of the control signal to generate a high-level clock signal, the clock signal being high except at the rising edge of the control signal Externally, it is low for the rest of the time, so that the third switch is connected to the charging capacitor by the clock signal at the rising edge of the control signal. State discharge; the charging capacitor starts to charge the charging period after the transient discharge until the voltage of the charging node is greater than the third reference voltage, causing the comparison result of the third comparator to be turned from the low level to the high level timing, and the third The high level comparison result of the comparator triggers the RS flip-flop reset, and the time period of the timing is used as the preset on-time of the main switch. The voltage converter of claim 9, wherein the preset on-time tends to decrease when the input voltage tends to increase, causing the sampled voltage value to increase; or the input voltage tends to decrease to cause sampling When the voltage value decreases, the preset on-time tends to increase. The voltage converter of claim 2, wherein the third switch and the charging capacitor in the on-time generator are connected in parallel between a charging node and the ground, and the voltage at the charging node is input to the on-time. a positive phase input of the third comparator in the generator and a third reference voltage at the inverting input; the on time generator includes a current source and a plurality of additional current sources for charging the charging capacitor, each additional An electronic switch is connected between the current output end of the current source and the charging node; a one-shot trigger in the second controller generates a high-level clock signal by a rising edge of the control signal, the clock signal is in addition to The rising edge of the control signal is at a high level except for a high level, so that the clock signal is turned on at the rising edge of the control signal to turn on the third switch to temporarily discharge the charging capacitor; the charging capacitor is after the transient discharge Start timing of the charging period until the voltage of the charging node is greater than the third reference voltage, causing the comparison result of the third comparator to be flipped by the low level The high-level timing is ended, and the high-level comparison result of the third comparator triggers the reset of the RS flip-flop, and the time period of the timing is used as the preset on-time of the main switch. The voltage converter according to claim 11, wherein when the voltage fluctuation is detected, the detection voltage is lower than the first reference voltage at a start time of the preset time period, and the main pulse is driven by the first pulse signal. After one or more switching cycles of the switch, the detection voltage is modulated to exceed the first reference voltage at the end of the preset time period; the respective frequency values of the one or more clock signals in the preset time period are in the order of occurrence time, A frequency comparator of the on-time generator compares with the upper frequency threshold and the lower frequency threshold, respectively, and sets a binary initial count value of a counter of the on-time generator when any one of the frequency values is greater than the upper frequency threshold Subtract 1 or add 1 to the initial count value set by the counter when any of the frequency values is less than the lower frequency threshold. The counter calculates a total value after all frequency values are compared; the total value is greater than the upper critical count value set by the counter. When the total value is defined equal to the upper critical count value, or when the total value is less than the lower critical count value set by the counter Yi total value is equal to the threshold count, the total binary value of each of a high or low level characterizes the respective symbols used to turn off an electronic switch. The voltage converter of claim 12, wherein, in any two adjacent preset time periods, the total value in the previous preset time period is greater than the initial count value, so that the latter preset time period The number of electronic switches that are turned on is greater than the number of electronic switches that are turned on within the previous preset time period, and the preset conduction time in the latter preset time period is smaller than the pre-predetermined time period. Set the conduction time; or the total value in the previous preset time period is smaller than the initial count value, so that the number of electronic switches that are turned on in the next preset time period is higher than the electronic one that is turned on in the previous preset time period. If the number of switches is small, the preset on-time in the last preset period is greater than the preset on-time in the previous preset period; or the total value in the previous preset period is equal to the initial count value, so that the latter The number of electronic switches that are turned on within the preset time period is equal to the number of electronic switches that are turned on within the previous preset time period, and the preset conduction time in the latter preset time period is equal to the previous preset. The preset on time during the time period. The voltage converter of claim 1, wherein the transformer further comprises an auxiliary winding wound in the same direction as the secondary winding, and a pole is connected between one end of the auxiliary winding and one end of the auxiliary capacitor. The other end of the body, the auxiliary winding and the auxiliary capacitor are connected to the ground end, and when the secondary side winding has a current passing therethrough, the diode between the auxiliary capacitor and the auxiliary capacitor is forwardly conducting and the current flowing through the auxiliary winding charges the auxiliary capacitor The auxiliary capacitor supplies a power supply voltage to the first controller. The voltage converter of claim 14, wherein one of the first controllers has a junction field effect transistor and a control switch, and the control switch is connected to the junction field effect transistor. Between the control terminal and the ground of the crystal, and the control switch is turned on when the voltage of the auxiliary capacitor does not reach a starting voltage level but is turned off when the starting voltage level is reached; the voltage converter begins to access the alternating current During the power-on phase of the voltage, the AC voltage is rectified by a rectifier circuit and input to the drain of the junction field effect transistor, so that the current flowing from the source of the junction field effect transistor is charged by the diode through the diode. Until the voltage of the auxiliary capacitor reaches the startup voltage level to complete the power-on startup program, the power-on startup program is completed, the control switch is turned off, and the auxiliary winding is charged to the auxiliary capacitor during the period in which the auxiliary winding is turned on. The voltage converter of claim 1, further comprising a voltage divider, wherein the voltage is detected by the voltage divider to extract a voltage divider value at the output node and characterize the output voltage. . The voltage converter of claim 1, further comprising a sensing resistor, the sensing resistor is connected in series with the load between the output node and the reference ground potential, and the detecting voltage is a voltage drop across the sensing resistor. It also characterizes the magnitude of the load current flowing through the load. The voltage converter of claim 1, wherein a voltage divider is provided, wherein the voltage divider draws a voltage divider value as a feedback voltage at an output node at the output node; A sensing resistor is included, the sensing resistor is connected in series with the load between the output node and the reference ground potential, and the voltage drop across the sensing resistor is used as a sensing voltage to characterize the magnitude of the load current; and a filter, an amplifier, and An adder that filters the DC component of the feedback voltage but retains the voltage value of the AC component. The amplifier is used to amplify the sense voltage, and the voltage value of the AC component of the filter output and the amplification voltage of the sense voltage output by the amplifier The value is added by the adder as the detected voltage.