TWI536409B - Pulse transformer - Google Patents

Pulse transformer Download PDF

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Publication number
TWI536409B
TWI536409B TW104130213A TW104130213A TWI536409B TW I536409 B TWI536409 B TW I536409B TW 104130213 A TW104130213 A TW 104130213A TW 104130213 A TW104130213 A TW 104130213A TW I536409 B TWI536409 B TW I536409B
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TW
Taiwan
Prior art keywords
spiral
circuit board
voltage
printed circuit
end
Prior art date
Application number
TW104130213A
Other languages
Chinese (zh)
Other versions
TW201711067A (en
Inventor
Tien-Chi Lin
Yu-Ming Chen
Jung-Pei Cheng
Pei-Lun Huang
Original Assignee
Alpha & Omega Semiconductor Cayman Ltd
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Application filed by Alpha & Omega Semiconductor Cayman Ltd filed Critical Alpha & Omega Semiconductor Cayman Ltd
Priority to TW104130213A priority Critical patent/TWI536409B/en
Application granted granted Critical
Publication of TWI536409B publication Critical patent/TWI536409B/en
Publication of TW201711067A publication Critical patent/TW201711067A/en

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Description

Pulse transformer

The invention relates mainly to an electronic device for voltage conversion, and more specifically to instantaneously sensing an output voltage or an output current of a secondary side of a transformer used as a power switching, and generating a transient response control signal and using a coupling element The control signal is transmitted to the primary side of the transformer for power switching to control the opening or conduction of the primary side winding.

In the existing voltage converter, the voltage or current on the load side is collected, and the feedback signal of the collected load side is fed back to the driving component of the voltage converter by using a feedback network, for example, a typical pulse width modulation method. Alternatively, the pulse frequency modulation method or the like uses a feedback signal to determine the duty ratio of the main switch that switches between on and off in the voltage converter, thereby scaling the output voltage of the voltage converter on the load side. It is known to those skilled in the art that the driving components of the voltage converter are used to drive the main switch, but the driving components do not directly draw the instantaneously varying load voltage from the load side, but rely on the feedback network to sense the load voltage. This kind of feedback mode will inevitably produce a delay effect. The bad result is that the driving component cannot synchronize with the changing state of the load voltage due to the delay to instantly switch the main switch, so the current output voltage value and load required for output to the load are required. There is a deviation between the actual voltage values that cause potential instability to the output voltage.

In an alternative embodiment, a voltage converter is disclosed in which a primary side winding of a transformer and a main switch are connected in series between an input voltage and a ground terminal, the secondary side winding connection of the transformer being provided to the load An output node of the output voltage and a reference ground potential; and a first controller for generating a first pulse signal to drive the main switch to switch between on and off; a second controller to characterize The output voltage magnitude and/or the detected voltage indicative of the magnitude of the load current is compared with a first reference voltage, and the logic state of a control signal generated by the comparison result is determined by the comparison result; a coupling element is connected to the first and second controls Between the devices, it passes the logic state of the control signal to the first controller, causing the first controller to determine the logic state of the first pulse signal according to the logic state of the control signal.

In the above voltage converter, the detection voltage is input to the inverting input end of the first comparator of the second controller, and the first reference voltage is input to the non-inverting input terminal; when the detection voltage is lower than the first reference voltage, the first comparison is performed. The high level comparison result sets the RS flip-flop of the second controller, so that the control signal output by the RS flip-flop is flipped from a low level to a high level; the second controller's on-time generator is low from the control signal The timing is started when the level is flipped to the rising edge of the high level, and the timing is completed until the end of the preset on-time. When the timing is completed, the signal output by the on-time generator is flipped from the low level to the high level and the RS flip-flop is reset. , the control signal is flipped from a high level to a low level.

In the above voltage converter, a first and a second switch are connected in series between a bias circuit of the second controller and the reference ground potential, wherein the first switch and the second switch are interconnected to a common node, and the first switch is The control signal is driven, and the second switch is driven by the inverted signal of the control signal; a first capacitor belonging to the coupling element is connected between the non-inverting input terminal of the second comparator in the first controller and the common node, The inverting input of the second comparator inputs a second reference voltage, A resistor is connected between the non-inverting input of the comparator and the ground, and a second capacitor belonging to the coupling element is connected between the ground and the reference ground potential.

In the above voltage converter, when the control signal is at a high level, the first switch is turned on and the second switch is turned off, and the voltage supplied from the bias circuit is applied to the common node, and the voltage of the positive input terminal of the second comparator is pulled up by the coupling element. Up to be greater than the second reference voltage, the second comparator outputs a first pulse signal of a high level; when the control signal is low level, the first switch is turned off and the second switch is turned on, and the potential at the common node is clamped to the reference ground The potential is pulled down by the coupling element to a voltage lower than the second reference voltage of the second comparator, and the second comparator outputs a first pulse signal of a low level.

In the above voltage converter, the coupling component is a pulse transformer, and the control signal is transmitted to one end of the main winding of the pulse transformer through a coupling capacitor in the second controller, and the other end of the main winding is connected to the reference ground potential; the first control A coupling capacitor is connected between a signal generating node and a terminal of the secondary winding of the pulse transformer, and the opposite end of the secondary winding is connected to the ground, thereby maintaining a logic state of the signal generating node and the control signal. Consistent first pulse signal.

In the above voltage converter, a resistor and a diode are arranged in parallel between the signal generating node and the ground, the cathode of the diode is connected to the signal generating node and the anode is connected to the ground.

In the above voltage converter, the anode of the rectifying diode is connected to one end of the secondary winding of the transformer, the cathode of the rectifying diode is connected to the output node, and the opposite end of the secondary winding of the transformer is directly connected to the reference ground. Potential.

In the above voltage converter, one end of the secondary winding of the transformer is directly connected to the output node, and a synchronous switch is connected between the opposite end of the secondary winding of the transformer and the reference ground potential, and the synchronous switch is controlled by the second controller. The generated and the first pulse signal are mutually opposite The driving of a second pulse signal of the number turns off the synchronous switch when the main switch is turned on and turns on the synchronous switch when the main switch is turned off. Or, still causing the synchronous switch to be driven by a second pulse signal generated by the second controller, at which time the first pulse signal (eg, at a low level) controls the phase at which the main switch is turned off, and the second pulse signal (For example, also at a low level) control also turns off the synchronous switch, that is, both the main switch and the synchronous switch are turned off to enter the dead time.

In the above voltage converter, a sample holder in the on-time generator controls the voltage value of the end of the secondary winding of the transformer connected to the synchronous switch at the stage where the main switch is turned on but the synchronous switch is turned off, and is turned on. A voltage current converter of the time generator converts the sampled voltage value into a current to charge a charging capacitor in the on-time generator; a third switch in the on-time generator and the charging capacitor are connected in parallel at a charging node and Between the ground terminals, the voltage at the charging node is input to the non-inverting input terminal of the third comparator in the on-time generator and a third reference voltage is input to the inverting input terminal of the third comparator; and the control signal is The rising edge triggers a one-shot of the second controller to generate a high-level clock signal that is low except for the high level at the rising edge of the control signal and the rest of the time. Therefore, the third switch is turned on by the clock signal at the rising edge of the control signal, and the charging capacitor is temporarily discharged; the charging capacitor is placed in the transient state. After the charging period is started, until the voltage of the charging node is greater than the third reference voltage, the comparison result of the third comparator is ended from the low level to the high level timing, and the high level comparison result of the third comparator is triggered. The RS flip-flop is reset, and the time period of the timing is used as the preset on-time of the main switch.

In the above voltage converter, when the input voltage tends to increase and the sampled voltage value increases, the preset on-time tends to decrease; or when the input voltage tends to decrease, the sampled voltage value decreases, the preset is turned on. Time tends to increase.

In the above voltage converter, the third switch and the charging capacitor in the on-time generator are connected in parallel between a charging node and the ground, and the voltage at the charging node is input to the guiding Passing a non-inverting input of a third comparator in the time generator and inputting a third reference voltage at the inverting input; the on-time generator includes a fixed current source and a plurality of additional current sources for charging the charging capacitor, An electronic switch is connected between the current output end of each additional current source and the charging node; a one-shot trigger in the second controller generates a high-level clock signal by a rising edge of the control signal, the clock The signal is low level except for the high level at the rising edge of the control signal, so that the clock signal is turned on at the rising edge of the control signal to turn on the third switch to charge the capacitor; the charging capacitor is instantaneous. After the state discharge, the charging period is started until the voltage of the charging node is greater than the third reference voltage, so that the comparison result of the third comparator is ended from the low level to the high level timing, and the high level comparison of the third comparator As a result, the RS flip-flop is triggered to reset, and the time period of the timing is used as the preset on-time of the main switch.

The voltage converter is configured to detect a voltage fluctuation, set the detection voltage to be lower than the first reference voltage at a start time of the preset time period, and drive the one or more switching cycles of the main switch by the first pulse signal to enable The detection voltage is modulated to exceed the first reference voltage at the end of the preset time period; the frequency values of the one or more clock signals in the preset time period are in the order of occurrence of the time, and a frequency comparator of the on-time generator Comparing with the upper frequency threshold and the lower frequency threshold respectively, when any one of the frequency values is greater than the upper frequency threshold, the initial count value of the binary set by the counter of the on-time generator is subtracted by 1, or when any one of the frequency values When the value is less than the lower frequency threshold, the initial count value set by the counter is incremented by 1. After all the frequency values are compared, the counter calculates a total value; when the total value is greater than the upper critical count value set by the counter, the defined total value is equal to the upper critical count value. Or the total value is equal to the lower critical count when the total value is less than the lower critical count value set by the counter , The total binary value of each of a high or low level characterized symbols corresponding to turning on or off an electronic switch.

In the above voltage converter, in any two adjacent preset time periods, the total value in the previous preset time period is greater than the initial count value, so that the next preset time period is turned on. The number of electronic switches is greater than the number of electronic switches that are turned on within the previous preset time period, and the preset conduction time in the latter preset time period is less than the preset conduction time in the previous preset time period; Or the total value in the previous preset time period is less than the initial count value, so that the number of electronic switches that are turned on in the last preset time period is less than the number of electronic switches that are turned on in the previous preset time period. , the preset on-time in the last preset time period is greater than the preset on-time in the previous preset period; or the total value in the previous preset period is equal to the initial count value, so that the next preset period The number of electronic switches that are turned on is equal to the number of electronic switches that are turned on within the previous preset time period, and the preset conduction time in the latter preset time period is equal to the preset in the previous preset time period. On time.

In the above voltage converter, the transformer further includes an auxiliary winding wound in the same direction as the secondary side winding, and a diode is connected between one end of the auxiliary winding and one end of the auxiliary capacitor, and the auxiliary winding and the auxiliary capacitor are respectively One end is connected to the ground end, and when the secondary side winding has a current passing therethrough, the diode between the auxiliary capacitor and the auxiliary capacitor is forwardly conducting and the current flowing through the auxiliary winding is charged to the auxiliary capacitor, and the auxiliary capacitor is provided for the first controller voltage.

In the above voltage converter, a power-on starting module of the first controller has a junction field effect transistor and a control switch connected between the control terminal and the ground terminal of the junction field effect transistor, And the control switch is turned on when the voltage of the auxiliary capacitor does not reach a starting voltage level but is turned off when the starting voltage level is reached; when the voltage converter starts to be connected to the AC voltage, the AC voltage is via a The rectifier circuit is rectified and input to the drain of the junction field effect transistor, so that the current flowing from the source of the junction field effect transistor is charged to the auxiliary capacitor through a diode until the voltage of the auxiliary capacitor reaches the startup voltage level. To complete the power-on startup program, the power-on startup program is completed, the control switch is turned off, and the auxiliary winding is charged to the auxiliary capacitor during the period in which the auxiliary winding is turned on.

The voltage converter includes a voltage divider, and the detection voltage is a voltage divider value of the voltage divider at the output node and represents a magnitude of the output voltage. The sensing resistor is included, and the sensing resistor is connected in series with the load between the output node and the reference ground potential. The detection voltage is the voltage drop across the sensing resistor and characterizes the magnitude of the load current flowing through the load.

The voltage converter includes a voltage divider, wherein the voltage divider draws a voltage divider value as a feedback voltage at an output node at the output node; and further includes a sensing resistor, a sensing resistor and The load is connected in series between the output node and the reference ground potential, and the voltage drop across the sense resistor is used as a sense voltage that characterizes the magnitude of the load current; and a filter, an amplifier, and an adder are included, the filter is used to filter the feedback voltage In the DC component but retaining the voltage value of the AC component, the amplifier is used to amplify the sensing voltage, and the voltage value of the AC component of the filter output and the amplified voltage value of the sensing voltage of the amplifier output are added by the adder as the Detector Measure the voltage.

In an alternative embodiment, a pulse transformer is disclosed comprising a U-shaped first core bobbin with a set of side arms extending in parallel, and a second core bobbin including a strip, in use Providing a first and second through holes extending through the thickness of the printed circuit board on a printed circuit board on which the pulse transformer is mounted, and a set of side arm portions of the first core bobbin from the first side of the printed circuit board The first through hole and the second through hole are not inserted, and the front end faces of the set of side arm portions are directly pressed against one surface of the second core bobbin on the second side of the printed circuit board.

In the above pulse transformer, a planarized first and second spiral coils are disposed on a first side surface or a second side surface of the printed circuit board, and a series of concentric coils in the first spiral coil surround the first through hole Arranged, a series of concentric coils in the second helical coil are disposed around the second through hole. a region between the first and second through holes on the printed circuit board is provided with a strip-shaped slit penetrating through the thickness of the printed circuit board, and the first and second through holes are symmetrically distributed along the slit as a central symmetry line. Both sides of the gap.

In the above pulse transformer, the first and second helical coils appear as a square or circular spiral coil. Also included is an insulating paste applied to the printed circuit board for adhering the first and second core bobbins to the printed circuit board.

In the above pulse transformer, a plurality of first spiral coils are disposed inside the printed circuit board, and the first spiral coils of the first side surface or the second side surface of the printed circuit board are aligned and overlapped, and the plurality of first spiral coils are disposed inside the printed circuit board. The first spiral coils are each disposed around the first through hole; the second end of any of the upper first spiral coils is interconnected with the first end of the adjacent next first spiral coil, thereby a spiral coil is connected in series, and the first end of the first first spiral coil in the plurality of first spiral coils connected in series is used as one of an equivalent end of the same name or an equivalent name, and the last one The second end of the first helical coil serves as the other of the equivalent end of the same name or equivalent. For example, in the two first spiral coils adjacent to each other, an insulating layer belonging to the circuit board is disposed between any one of the first first spiral coils and the adjacent first spiral coil to space them. Also for example, the first end of the first first helical coil on the first side surface of the printed circuit board serves as an equivalent end of the same name (or a different name) of the plurality of first helical coil series structures, and is located in the printed circuit The second end of a first helical coil at the end of the second side surface of the plate serves as an equivalent different end (or the end of the same name) of the plurality of first helical coil series structures.

In the above pulse transformer, a plurality of second spiral coils are disposed inside the printed circuit board, and the second spiral coils of the first side surface or the second side surface of the printed circuit board are aligned and overlapped, and the plurality of second spiral coils are disposed inside the printed circuit board. The second helical coils are each disposed around the second through hole; any second end of the upper second helical coil is interconnected with the first end of the adjacent next second helical coil, thereby The two spiral coils are connected in series, and the first end of the first second helical coil is used as one of the equivalent end of the same name or the equivalent name in the plurality of second helical coils connected in series, one at the end The second end of the second helical coil is used as an equivalent end of the same name or equivalent The other of the two names. For example, the first end of the first second helical coil on the first side surface of the printed circuit board serves as an equivalent end of the same name (or a different name) of the plurality of second helical coil serial structures, and is located on the printed circuit board The second end of the first helical coil at the end of the second side surface serves as an equivalent name end (or the same name end) of the plurality of second helical coil series structures.

In the above pulse transformer, a power transformer main transformer is also mounted on the printed circuit board. The primary side winding of the main transformer receives the input voltage and provides an output voltage for the load on the secondary side winding, and the primary side winding of the main transformer and a main switch are connected in series. a wafer with a first controller mounted on the printed circuit board for generating a first pulse signal for driving the main switch to switch between on and off; and a wafer with a second controller mounted on the printed circuit On the board, a detection voltage that characterizes the magnitude of the output voltage and/or the magnitude of the load current is compared with a first reference voltage, and the logic state of a control signal generated by the comparison is determined by the comparison result; wherein the pulse transformer will control The logic state of the signal is passed to the first controller, causing the first controller to determine the logic state of the first pulse signal according to the logic state of the control signal, thereby determining whether the main switch is turned on or off.

In an alternative embodiment, a pulse transformer is disclosed comprising a U-shaped first core bobbin with a set of side arms extending in parallel, and a second core bobbin including a strip, in use Providing a first and second through holes extending through the thickness of the printed circuit board on a printed circuit board on which the pulse transformer is mounted; and a first wafer having a first center hole and a second hole having a second center hole a second wafer, the first and second wafers are mounted on the printed circuit board, the first central hole and the first through hole are coincidently aligned, and the second central hole and the second through hole are aligned and coincident; from the first side of the printed circuit board Inserting one of the set of side arm portions of the first core bobbin into the first center hole, the first through hole and the other while inserting the second center hole, the second through hole, and the set of side arm portions The respective front end faces are directly pressed against one surface of the second core bobbin on the second side of the printed circuit board.

In the above pulse transformer, the first wafer includes: a first substrate on which a first spiral wiring is disposed on one surface: two pins disposed near the first substrate, the first spiral wiring The two ends are respectively connected to the two pins through lead wires; a first plastic sealing body covers the first substrate, the first spiral cloth, and the lead wires, wherein the pins are used to receive a part of the lead wires by the first The molding body is covered, but another portion of the lead extends beyond the first molding body for soldering with the pad on the printed circuit board; the first center hole penetrates the first molding body and the first substrate, and the first portion A series of concentric spiral wires in a spiral wiring are disposed around the first center hole. If a first substrate carrying the first substrate is further disposed, the two pins of the first substrate and the first wafer are disposed adjacent to each other, and the first substrate is also covered by the first molding body, and the first center hole It also penetrates the first substrate.

In the above pulse transformer, a plurality of first spiral wires are disposed on the first substrate and they are vertically aligned with each other, and an insulating dielectric layer is disposed between the two first spiral wires adjacent to each other. a series of concentric spiral wirings in a first spiral wiring are disposed around the first central hole; any second end of the upper first spiral wiring and the first end adjacent to the next first spiral wiring are mutually Connecting all of the first spiral wires in series, wherein the first end of the first first spiral wire in the plurality of first spiral wires connected in series serves as an equivalent end of the same name or an equivalent name In one of the two, the second end of a first spiral wiring at the end serves as the other of the equivalent end of the same name or the equivalent name. For example, in the two first spiral wirings adjacent to each other, an insulating dielectric layer is provided between any of the previous first spiral wirings and the adjacent first spiral wiring to space them. Also for example, the first end of a first spiral-shaped wiring on the topmost substrate on the substrate serves as an equivalent-named end (or a different end) of the plurality of first spiral-shaped wiring series structures, and is located on the substrate The second end of the first spiral wiring of the lowest layer serves as an equivalent different end (or the same end) of the plurality of first spiral wiring series structures.

In the above pulse transformer, the second wafer includes: a second substrate on which a second spiral wiring is disposed on the surface of the second substrate: two pins disposed near the second substrate, and the second spiral wiring The two ends are respectively connected to the two pins through lead wires; a second plastic sealing body covers the second substrate, the second spiral cloth, and the lead wires, wherein the pins are used to receive a part of the lead wires by the second The plastic body is covered, but another portion of the lead extends beyond the second plastic body for soldering to the pads on the printed circuit board; the second central hole extends through the second plastic body and the second substrate, and A series of concentric spiral wirings in the two spiral wirings are arranged around the second center hole. If a second substrate carrying the second substrate is further disposed, the two pins of the second substrate and the second wafer are disposed adjacent to each other, and the second substrate is also covered by the second molding body, and the second center The holes also penetrate the second substrate.

In the above pulse transformer, a plurality of second spiral wirings are disposed on the second substrate and they are vertically aligned with each other, and an insulating dielectric layer is disposed between the two adjacent second spiral wirings. a series of concentric spiral wires in the second spiral wiring are arranged around the second center hole; the second end of any of the last second spiral wires is interconnected with the first end of the adjacent next second spiral wire Thereby, all the second spiral wires are connected in series, and the first end of the first second spiral wire in the plurality of second spiral wires connected in series is used as the equivalent end of the same name or the equivalent name Alternatively, the second end of a second spiral wiring at the end serves as the other of the equivalent end of the same name or the equivalent name. For example, in the two second spiral wirings adjacent to each other, an insulating dielectric layer is provided between any of the preceding second spiral wirings and the adjacent second spiral wiring to space them. Also for example, the first end of a second spiral wiring on the topmost substrate on the substrate serves as an equivalent end of the same name (or a different name) of the plurality of first spiral wiring series structures, and is located on the substrate The second end of one of the bottommost spiral wirings serves as an equivalent different name end (or the same name end) of the plurality of second spiral wiring series structures.

The pulse transformer described above further includes an insulating paste coated on the printed circuit board for adhering the first and second core bobbins to the printed circuit board. The first wafer and the second wafer are connected to each other by one or more connecting portions to make them a coplanar integrated structure, so that the first wafer and the second wafer are simultaneously mounted on the printed circuit board.

In an alternative embodiment, a pulse transformer is disclosed, including first and second wafers, the first wafer having a U-shaped first core bobbin and a first molding body having a first core bobbin molded The second wafer has a U-shaped second core bobbin and a second molding body having a second core bobbin; the first and second core bobbins each have a set of side arms extending in parallel a front end surface of each of the set of side arm portions of the first core bobbin is exposed from one side edge surface of the first molding body, and a front end surface of each of the side arm portions of the second core bobbin is from the second plastic package One side edge surface of the body is exposed such that the side edge surface of the side arm portion of the first molding body exposing the first core bobbin faces the side edge surface of the side arm portion of the second molding body exposing the second core bobbin, And the front end surface of any one of the side arm portions of the first core bobbin is aligned with the front end surface of one of the second core bobbins.

In the above pulse transformer, a middle portion is connected between a set of side arm portions of the first core bobbin, and the first coil having the first coil winding is wound on the middle portion of the first core bobbin, the first coil winding The two ends are respectively connected to two pins of the first wafer, the pins for receiving a part of the first coil winding are covered by the first plastic body, and the other part of the lead is extended to the outside of the first plastic body Butt welding with the pads on the printed circuit board.

In the above pulse transformer, a middle portion is connected between a set of side arm portions of the second core bobbin, and the second coil winding of the second wafer is wound on the middle portion of the second core bobbin, and the second coil winding is The two ends are respectively connected to two pins of the second wafer, the pins for receiving a part of the second coil winding are covered by the second plastic body, and the other part of the lead is extended to the second plastic body Butt welding with the pads on the printed circuit board.

In the above pulse transformer, when the first and second wafers are mounted side by side on the printed circuit board, the first molding body and the second molding body are disposed apart from each other, and the front end surface of the side arm portion of the first core core frame and the second magnetic core The front end faces of the side arm portions in the skeleton are aligned one-to-one in a spaced apart manner.

In the above pulse transformer, when the first and second wafers are mounted side by side on the printed circuit board, the first plastic body and the second plastic body are closely attached to each other, so that the side arm of the first plastic body exposing the first core frame The side edge surface of the portion and the side edge surface of the side arm portion of the second molding body exposing the second core bobbin are seamlessly fitted, the front end surface of the side arm portion of the first core bobbin and the second core bobbin The front end faces of the side arm portions are aligned one-to-one in such a manner as to be low-pressure mutually.

In the above pulse transformer, the first molding body and the second molding body are spaced apart and filled with an insulating material in a gap between them, a front end face of the side arm portion of the first core bobbin and a side arm in the second core bobbin The front end faces of the portions are aligned one to one in a manner spaced apart by an insulating material.

101‧‧‧Rectifier

103‧‧‧ snubber circuit

104‧‧‧First controller

105‧‧‧Second controller

105a‧‧‧RS trigger

105b‧‧‧Click circuit

105c‧‧‧ On-time generator

105c-1‧‧‧Sampling holder

105c-2‧‧‧Voltage current converter

105d‧‧‧bias circuit

105e‧‧‧Inverter

105g‧‧‧ filter

105h‧‧Amplifier

105i‧‧‧Adder

106‧‧‧Coupling components

110‧‧‧Fixed current source

111‧‧‧Additional current source

112‧‧‧Additional current source

113‧‧‧clock generator

113a‧‧‧Oscillator

113b‧‧‧divider

114‧‧‧Frequency comparator

115‧‧‧ counter

116‧‧‧ Register

12,14‧‧‧ Busbar

16‧‧‧Main side controller

17‧‧‧Optocoupler

18‧‧‧load

200‧‧‧ boards

201‧‧‧ first through hole

202‧‧‧Second through hole

202a‧‧‧Spiral coil

202b‧‧‧Spiral coil

203‧‧‧ gap

204‧‧‧ gap

210‧‧‧Magnetic core skeleton

210a‧‧‧Side arm

210b‧‧‧Side arm

210c‧‧‧Mid section

211‧‧‧Magnetic core skeleton

22‧‧‧Output line

24‧‧‧Output line

301‧‧‧First chip

302‧‧‧second chip

311‧‧‧plastic body

311a‧‧ Corner

311b‧‧‧ corner

312‧‧‧ pin

313‧‧‧ pin

314‧‧‧First Center Hole

315‧‧‧Spiral wiring

316‧‧‧substrate

317‧‧‧Substrate

318‧‧‧Leader

321‧‧‧plastic body

321a‧‧‧ corner

321b‧‧‧ corner

322‧‧‧ pin

323‧‧‧ pin

324‧‧‧ second central hole

325‧‧‧ spiral wiring

326‧‧‧Substrate

327‧‧‧Substrate

328‧‧‧Leader

331‧‧‧Connecting Department

332‧‧‧Connecting Department

401‧‧‧First chip

402‧‧‧second chip

410‧‧‧Magnetic core skeleton

410a‧‧‧Side arm

Middle section of 410b‧‧‧

410c‧‧‧ lateral arm

410a-1‧‧‧ front face

410c-1‧‧‧ front face

411‧‧‧plastic body

411a‧‧‧ side

412‧‧‧ pin

413‧‧‧ pin

415‧‧‧First coil winding

420‧‧‧Magnetic core skeleton

420a‧‧‧Side arm

420b‧‧‧ mid section

420c‧‧‧ lateral arm

420a-1‧‧‧ front face

420c-1‧‧‧ front face

421‧‧‧ Plastic body

421a‧‧‧ side

422‧‧‧ pin

423‧‧‧ pin

425‧‧‧second coil winding

430‧‧‧ gap

450‧‧‧Insulation materials

A1‧‧‧First comparator

A2‧‧‧Second comparator

A3‧‧‧ third comparator

A4‧‧‧ buffer

C OUT ‧‧‧ output capacitor

C AUX ‧‧‧ capacitor

COMP‧‧‧Feedback埠

C 1 , C 11 , C 12 , C 2 , C 21 , C 22 , C Y , C T , C 51 , C 52 ‧‧‧ capacitor

C X ‧‧‧Safety Capacitor

C IN ‧‧‧Input Capacitor

CTRL‧‧‧Switching signal

CLK1‧‧‧ clock pulse

CLK2‧‧‧ clock signal

D AUX ‧‧‧ diode

D 11 , D 12 , D 13 , D 14 , D 21 , D 22 , D 31 , D 51 ‧ ‧ diode

D REC ‧‧‧Rected Diode

DE1, DE2‧‧‧ detection signal

GND‧‧‧ ground terminal

HV‧‧‧drain

I O ‧‧‧Load current

I 0 , I 1 , I 2 ‧ ‧ current

I D ‧‧‧ primary current

JFET‧‧‧High-voltage starting element

T‧‧‧Transformer

L P ‧‧‧main side winding

L S ‧‧‧ secondary winding

L AUX ‧‧‧Auxiliary winding

L 1 ‧‧‧Inductance

L PT1 ‧‧‧main side winding

L PT2 ‧‧‧ secondary winding

LOOP1, LOOP2‧‧‧ loop

N 10 ‧‧‧Input node

N 20 ‧‧‧Output node

N 1 , N 2 , N 3 , N 4 , N 5 , N 6 , N 7 , N T , N S ‧‧‧ nodes

NS, NP‧‧‧匝

PT‧‧‧pulse transformer

Q1‧‧‧Main switch

Q2‧‧‧Synchronous switch

Q‧‧‧output

R 21 ‧‧‧ current limiting resistor

R S ‧‧‧resistance resistor

R C ‧‧‧Sensor resistance

RX1, RX2‧‧‧ receiving interface

R 1 , R 2 , R 3 , R 4 , R 5 , R 31 , R 41 , R 51 ‧ ‧ resistance

R D1 , R D2 ‧‧‧resistance

R‧‧‧Reset end

S 1 ‧‧‧first pulse signal

S 2 ‧‧‧second pulse signal

ST‧‧‧Starting voltage

S‧‧‧Reset end

SQ, SQ1, SQ2‧‧‧ control signals

S ON , S ON1 , S ON2 ‧‧‧ signal

SW 31 ‧‧‧Control switch

SW 41 ‧‧‧First switch

SW 42 ‧‧‧Second switch

SW 51 ‧‧‧third switch

SW 61 ‧‧‧fourth switch

SW 62 ‧‧‧ fifth switch

TX1, TX2‧‧‧ send interface

T 1 , T 2 , T 3 ‧‧‧

T ON , T ON1 , T ON2 ‧‧‧ conduction period

T OFF , T OFF1 , T OFF2 ‧‧‧ disconnection period

T SET , T SET -A, T SET -B‧‧‧Preset time period

TIME1‧‧‧First time

TIME2‧‧‧Second time

V AC ‧‧‧Sinusoidal AC voltage

V IN ‧‧‧ input voltage

V CC ‧‧‧ voltage

V O ‧‧‧Output voltage

VSS‧‧‧reference ground potential

V FB ‧‧‧ feedback voltage

V CS ‧‧‧Sensor voltage

V REF ‧‧‧reference voltage

V RX1 ‧‧‧Charging voltage

V TH ‧‧‧second reference voltage

V P ‧‧‧ third reference voltage

V TX1 ‧‧‧Charging voltage

V DD ‧‧‧Power supply voltage

V SAM ‧‧‧ voltage

1 is a basic architecture of a voltage converter to which the present invention relates.

Figure 2 shows the feedback network of the voltage converter using TL431 for feedback.

Figures 3 to 4 are schematic diagrams of the coupling elements using capacitors and pulse transformers, respectively.

Figure 5 is a starter module with the first drive on the primary side.

Fig. 6A is a diagram showing the manner in which the second controller on the secondary side transmits a control signal to the first driver by the capacitive coupling element.

Fig. 6B is based on Fig. 6A to generate first and second pulse signals as the output voltage or current magnitude changes.

FIG. 6C is a mode in which the on-time of the main switch is adjustable in the second controller based on FIG. 6A.

Fig. 6D is a waveform diagram of adjusting the on-time based on Fig. 6C.

Fig. 7A shows the manner in which the second controller on the secondary side transmits a control signal to the first driver using a pulse transformer.

Fig. 7B is based on Fig. 7A to generate first and second pulse signals as the output voltage or current magnitude changes.

Fig. 7C is a comparison of the output results of the introduced filter and amplifier based on Fig. 7A and then compared with the reference voltage.

Fig. 8 is a synchronous switch in which the secondary side rectifying diode is replaced by the secondary side.

Figure 9 is a diagram of adjusting the on-time of the main switch when the load becomes light.

Figure 10 is a diagram showing the main switch on-time determined based on a control signal clamped by the previous control signal in Figure 9.

11A to 11B are views showing the structure of a pulse transformer in a first embodiment thereof.

12A to 12E show the structure of a pulse transformer in a second embodiment thereof.

13A to 13C show the structure of a pulse transformer in a third embodiment thereof.

The technical solutions of the present invention will be clearly and completely described in conjunction with the embodiments, but the described embodiments are merely examples of the embodiments used in the description of the present invention and not all of the embodiments, based on the embodiments, The solutions obtained by those skilled in the art without creative efforts are within the scope of the present invention.

Referring to FIG. 1, the inventive spirit of the present invention is illustrated by taking an AC-to-DC flyback FLYBACK voltage converter including a power stage transformer T for voltage conversion, the transformer T having a main side. Or the primary side winding L P and the secondary side or secondary winding L S , the first end of the primary side winding L P receives the input voltage V IN at the input node N 10 as the name terminal and the primary side winding L P is opposite A second switch Q1 is connected between the second end and the ground GND. The basic working mechanism is embodied in that the main switch Q1 is switched between on and off by the main side controller or the first controller 104. When the main switch Q1 is turned on, the main side current flows through the main side. The winding L P and the main switch Q1 flow to the ground GND, but no current flows through the secondary winding L S at this stage, and the primary winding L P starts to store energy; once the main switch Q1 is turned off, the current on the primary side stops. The polarity of all windings is reversed and the transformer T begins to transfer energy to the secondary winding L S such that the secondary winding L S supplies the operating voltage and current to the load 18 during the phase of the main switch Q1 being disconnected, and at the output node The N 20 charges and stores the charge to the output capacitor C OUT , and the output capacitor C OUT can continue to supply the operating voltage to the load 18 when no current flows through the secondary winding L S and cannot directly supply operating current to the load 18 . In some embodiments the transformer T also has an auxiliary winding L AUX , the winding of the auxiliary winding L AUX is the same as the winding of the secondary winding L S , that is, once the main switch Q1 is opened, a flow assist is generated. The current of winding L AUX can be substantially charged to a capacitor C AUX and serves as the operating voltage source for first driver 104 .

Referring to FIG. 1, the alternating current is rectified by the rectifier 101, and the bridge rectifier 101 includes four diodes such as the illustrated diodes D 11 to D 14 . Usually, a sinusoidal alternating voltage V AC of a conventional mains is input to a pair of input lines, that is, busbars 12 and 14. The bridge rectifier 101 fully utilizes the positive half cycle and the negative half cycle of the original alternating current sinusoidal waveform to complete the sine of the alternating current. The waveform is converted to the same polarity for output. When the sinusoidal alternating voltage V AC is full-wave rectified by the bridge rectifier 101, it is rectified and converted into a ripple voltage with an alternating current component. To further reduce the ripple of the ripple voltage, the alternating current is rectified and further utilized a CLC type. A filter filters out the ripple of the rectified voltage to obtain an input voltage V IN . It can be observed in Fig. 1 that one end of the inductance L 1 of the CLC type filter is connected to the respective cathodes of the diodes D 11 and D 13 of the rectifier 101, and the opposite end of the inductor L 1 is coupled to the main node at the node N 10 a first end of the side winding L P , and a capacitor C 11 of the CLC filter is connected between one end of the inductor L 1 and the ground GND, and the other capacitor C 12 of the CLC filter is connected to the other end of the inductor L 1 and Between ground GND. The anodes of the diodes D 12 and D 14 of the bridge rectifier 101 are connected to the ground GND, wherein the bus bar 12 is connected to the anode of the diode D 11 and the cathode of D 12 and the bus bar 14 is connected to the diode D 13 Anode and cathode of D 14 .

Referring to FIG. 1, the voltage converter further includes an RCD clamp bit circuit or a disconnect buffer circuit 103 in parallel with the main side winding L P . The disconnecting buffer circuit 103 includes capacitors and resistors connected in parallel with each other, one end of each of which is connected to the node N 10 and the other end of each of them is connected to the cathode of one of the diodes in the disconnecting buffer circuit 103, the pole The anode of the body is then connected to the second end of the primary side winding L P . The function of the disconnection buffer circuit 103 is to limit the superposition of the peak voltage and the secondary coil reflection voltage caused by the energy of the leakage inductance of the high-frequency transformer when the main switch Q1 is turned off, and the timing of the superimposed voltage is turned from the saturation state of the main switch Q1. During the disconnection process, the energy in the leakage inductance can be charged to its capacitor by disconnecting the diode of the buffer circuit 103, and the voltage on the capacitor may rush to the superposition value of the counter electromotive force and the leakage inductance voltage, and the function of the capacitor Then the energy of this part is absorbed. When the primary side winding L P and the main switch Q1 enter the conducting phase again from the off state, the energy on the capacitance of the disconnecting buffer circuit 103 is released by the resistance of the disconnecting buffer circuit 103 until the voltage on the capacitor reaches the next main switch. The back electromotive force before Q1 is disconnected.

Referring to FIG. 1, the first end of the secondary winding L S is connected to the output node N 20 as a different name end, and the opposite second end of the secondary winding L S is connected to the first end of a synchronous switch Q2 as the name end, and the The second end of the synchronous switch Q2 is connected to the reference ground potential VSS. The output capacitor C OUT is connected between the output node N 20 and the ground reference VSS, or provide an output voltage V O load 18 as an operating voltage to the load 18 at the output node N 20. It should be noted that one of the limit switches Q1 and Q2 is turned on and the other must be turned off. For example, the main switch Q1 on the primary side requires the synchronous switch Q2 on the secondary side to be turned off during the turn-on phase, and vice versa, on the primary side. The main switch Q1 requires the secondary side synchronous switch Q2 to be turned on during the off phase. The main switch Q1 and the synchronous switch Q2 each have a first end, a second end and a control end, which serve as electronic switches, and the high and low logic levels of the signal applied to the control end determine that the first end and the second end are conductive. Still disconnected. In the normal operating phase of the voltage converter, the first controller 104, a first pulse signal S generated by a primary side for driving the main switch Q1 is switched between OFF and ON state, the second controller 105 generates the secondary side The second pulse signal S 2 is used to drive the synchronous switch Q2 to switch between the off and on states. In addition, when the synchronous switch Q2 is driven by the second pulse signal S 2 generated by the second controller 105, there is still a dead time between the main switch Q1 and the synchronous switch Q2, so it may also occur in the A pulse signal S 1 controls the phase in which the main switch Q1 is turned off. The second pulse signal S 2 controls the case where the synchronous switch Q2 is turned off.

Referring to Figure 1, in addition to the secondary side coil L S, a secondary winding is additionally provided L AUX first end as dotted end connected to the anode of a diode D AUX, and the cathode corresponds to the diode D AUX is connected to the capacitor One end of C AUX , and the other end of the capacitor C AUX is connected to the ground GND, and the opposite second end of the auxiliary winding L AUX is connected to the ground GND as the name terminal. When the main switch Q1 is turned on, the secondary winding L S and the auxiliary winding L AUX have their opposite ends of the same name being negative and no current flows, and the output capacitor C OUT supplies power to the load 18. Conversely, when the main switch Q1 is turned off, the polarity of the secondary winding L S and the auxiliary winding L AUX are reversed, and their respective different names are positive with respect to the same name end and both have current flow, and the energy of the primary winding L P is transmitted to The secondary winding L S and the auxiliary winding L AUX , in other words, when the main switch Q1 is open, not only the secondary winding L S supplies the load current to the load 18 but also the output capacitor C OUT , and the auxiliary winding L AUX also acts as a power source. The auxiliary capacitor C AUX is charged. In FIG. 1, the voltage V CC held at one end of the capacitor C AUX is taken as the power supply voltage of the first controller 104. The capacitor C Y is a safety capacitor connected between the main ground terminal GND and the secondary side reference ground potential VSS, and can filter out the noise voltage generated by the distributed capacitance between the main side and the secondary side winding, or filter the main side and Common mode interference due to coupling capacitance between the secondary windings.

Referring to FIG. 1, the second controller 105 on the secondary side immediately captures the change state of the output voltage V O at the node N 20 or instantaneously senses the change of the load current I O (ie, output current) flowing through the load 18, and thereby generates The control signal SQ, and the first controller 104 on the primary side needs to further generate a first pulse signal S 1 by using the state of the high and low logic levels of the control signal SQ, and accordingly determines the main switch by the first pulse signal S 1 Q1 needs to be turned on or needs to be disconnected. Because the second controller 105 generates a change in the control signal SQ with respect to the voltage V O or the current I O that is almost transient, the first controller 104 generates the first pulse signal S 1 to respond immediately to the change of the control signal SQ, then The first pulse signal S 1 corresponds to a change in the instantaneous tracking voltage V O or current I O as well. As to how the second controller 105 generates a control signal SQ, and how the second controller 105 and the first controller 104 use the coupling element 106 to interactively transfer information, etc., will be described in detail hereinafter.

Referring to Figure 2, in the TL431 feedback network, resistors R 1 and R 2 are voltage-samped for output voltage V O , resistor R 3 is used for loop gain adjustment, capacitors C 1 and C 2 are compensation capacitors, and resistor R 5 is Compensation resistor. The general working principle is: when the output voltage V O rises, the control terminal of the three-terminal programmable shunt regulator in the TL431 (corresponding to the inverting input of a voltage error amplifier) is input with the resistors R 1 and R 2 The voltage divider value increases as the output voltage V O rises, but the voltage at the cathode of the three-terminal programmable shunt regulator diode (corresponding to the output of the voltage error amplifier) drops, causing the light to flow through The primary current ID of the light-emitting element connected between the cathode of the shunt regulator diode and the resistor R 3 in the coupler 17 is increased, and flows through the transistor that receives the received light intensity on the other side of the photocoupler 17 The output current also increases, so that the voltage of the feedback 埠COMP of the main-side controller 16 is lowered to cause the duty ratio of the pulse signal for controlling the main switch Q1 to decrease, thereby achieving a reduction in the output voltage V O . Vice versa, when the output voltage V O decreases, the adjustment process is similar but the trend of each corresponding response state is reversed, and finally the duty ratio of the pulse signal controlling the main switch Q1 is increased to achieve the rise of the output voltage V O . . The function of the resistor R 4 is to additionally inject a current into the TL431 to prevent the TL431 from operating normally due to the injection current being too small. If the resistance value R 3 is appropriately selected, the resistor R 4 can be omitted. The feedback network of Figure 2 must reserve sufficient gain and phase margin to ensure stability of the overall system, such as an open loop gain of at least 45° phase margin, typically allowed to range from 45° to 75°. Obviously, the biggest problem with this form of compensation is that the control mode is complicated and the delay effect is very obvious. The main controller 16 cannot detect the secondary side immediately, and the present invention advocates discarding the feedback network.

Referring to FIG. 3, the coupling component 106 of FIG. 1 specifically uses a coupling capacitor. Referring to FIG. 4, the coupling component 106 of FIG. 1 specifically employs a pulse transformer. In addition, other piezoelectric elements or optical coupling elements and the like are also suitable as the coupling element 106 as long as they can be referred to as the primary side controller or the first controller 104 and the secondary side controller or the second controller 105. Interchange information information.

Referring to FIG. 5, a safety capacitor C X is connected between the input lines 12 and 14 to suppress the difference model interference and filter out the high frequency clutter signal. In the reduction diagram, an input capacitor C IN is connected to the input node. Between the ground terminal GND and the AC voltage V AC input to the set of input lines 12 and 14 is rectified by the bridge rectifier 101 described above and then filtered by the input capacitor C IN to obtain an input voltage V IN . The voltage converter converts the input voltage V IN through the voltage of the power stage to provide an output voltage V O to the load on a set of output lines 22, 24. In the present invention, a rectifying circuit is further provided on the input lines 12, 14. The anode of one rectifying diode D 21 of the rectifying circuit is connected to the input line 12, and the other rectifying diode D 22 of the rectifying circuit is The anode is then connected to the input line 14. Further, the cathodes of the respective diodes D 21 and D 22 are interconnected and connected to the drain terminal HV of a high voltage starting element JFET belonging to the first controller 104, and may also be at the drain terminal HV and the diode D 21 of the JFET. D between the respective cathode 22 is connected to the current limiting resistor R shown in FIG. 121, the source terminal of a junction field effect transistor JFET connected to the anode of a diode D 31 is connected to cathode of diode D in FIG. 31 a, To the ungrounded end of the auxiliary capacitor C AUX as the power source mentioned above, and a current limiting resistor R 31 connected to the gate control terminal and the source terminal of the JFET, and the gate of the JFET and the ground GND Connected to a control switch SW 31 , the first end of the control switch SW 31 is connected to the gate of the JFET and the second end is connected to the ground GND. When the input line 12, while the access plug listed AC power applied to start driving the switch signal CTRL controls the switch SW 31 into a conducting state, the gate of control switch SW 31 will be connected to ground potential on the control gate 31 of the switch SW GND turns on the JFET of the negative threshold voltage, so the generated current flows from the drain of the JFET to the source through the diode D 31 to charge the ungrounded end of the capacitor C AUX . The forward voltage drop across resistor R 31 rises, but the gate-to-source voltage drops across the JFET, and the voltage across the JFET source and gate is approximately balanced to the pinch-off voltage of a JFET. The value, which corresponds to the actual voltage drop from the JFET gate G to the source S direction, is equal to the negative of this pinch-off value. When the JFET charges the capacitor C AUX until its stored voltage V CC rises to the startup voltage level, an unillustrated drive control module is triggered to enter a working state, and the drive control module is used to generate an initial pulse signal and make the main The switch Q1 is driven by the initial pulse signal to switch between on and off to start operation, and the voltage converter completes the start of the Start-Up program. After the start of the program, the capacitor C AUX is charged by the auxiliary winding L AUX through the diode D AUX connected to its first terminal. In addition, although not shown in FIG. 1, it should be recognized that a voltage divider may be connected between the first end of the auxiliary winding L AUX and the ground GND to input the divided voltage of the voltage divider sampling to the first controller. 104, whereby the first controller 104 uses the voltage divider to perform current zero-crossing (ZCD) detection of the secondary winding or overvoltage detection of the secondary side output voltage. And a first end of the main switch Q1 is connected to a second end of the main side winding L P , and a second end of the main switch Q1 is connected with a sensing resistor R S between the source and the ground GND. By multiplying the current value of the main winding L P by the resistance value of the sensing resistor R S , a voltage VS indicating the magnitude of the current flowing through the main side can be obtained. If the voltage VS is input to the first controller 104, the first controller By limiting this voltage VS to a preset limit voltage VLIMIT, the current on the primary side can be monitored and overcurrent protected.

Referring to FIG. 1, after the startup program is completed to switch the main switch Q1 between on and off for the first time, once the main switch Q1 is turned off, the first end of the secondary winding L S is positively polarized, and then The voltage drawn by the first end of the secondary winding L S can be used as the starting voltage ST to open the secondary controller 105 on the secondary side. The second controller 105 instantly monitors the output voltage V O of the secondary side and monitors the current I O flowing through the load 18 in a specific manner, for example, by using a series connection between the output node N 20 and the reference ground potential VSS of the secondary side. a voltage divider obtained by resistors R D1 and R D2 to obtain a divided voltage value, which is substantially generated at a node where the resistors R D1 and R D2 are interconnected and fed back as a feedback voltage V FB Two controllers 105. And placing the load 18 and a sense resistor R C in series between the output node N 20 and the reference ground potential VSS of the secondary side, the current I O flowing through the load 18 can be used to sense the voltage drop across the sense resistor R C V CS is divided by the resistance of the sense resistor R C , in other words, the sense voltage drop V CS can be used to characterize the magnitude of the load current value flowing through the load 18 and the sense resistor R C .

Referring to FIG. 6A, some components of the first controller 104 and the second controller 105 are shown to achieve the above-mentioned changes in the sense voltage drop V CS and the feedback voltage V FB to instantly control the conduction of the main switch Q1. Or the purpose of disconnection. The first controller 104 and the second controller 105 rely on the coupling element 106 for data interaction. The coupling element 106 includes two coupling capacitors C 21 and C 22 . The working mechanism of the first and second controllers 104, 105 will be described below. . It is to be noted that the first controller 104 and the second controller 105 are merely exemplary of the following structures for explaining the inventive spirit of the present invention, and the embodiments have various equivalent modifications, and any implementation based on the implementation For example, the solutions obtained without creative labor are within the scope of the present invention.

In the second controller 105, there is a first switch SW 41 and a second switch SW 42 each of which includes a first end and a second end and a control end, as an electronic switch, the level of the signal applied by the control end The logic state determines whether the first end and the second end are open or conductive. The two are connected in series between the bias circuit 105d and the reference ground potential VSS, for example, the first end of the first switch SW 41 is connected to the bias circuit 105d and the second end is connected to the first end of the second switch SW 42 The second end of the second switch SW 42 is connected to the reference ground potential VSS, and the first switch SW 41 and the second switch SW 42 are controlled by a control signal SQ generated by the Q output of the RS flip-flop 105a, for example, a control signal SQ is coupled to the control terminal of the first switch SW 41, the signal is coupled via a control signal SQ inverted by inverter 105e generated to the control terminal of the second switch SW 42 is, of course, also be a control signal SQ is also coupled through a buffer and then a first control terminal of the switch SW 41. That is, the first switch SW 41 turns on the second switch SW 42 is turned off should be the first or the second switching switch SW 41 SW 42 is turned off should be turned on.

For the second controller 105, a voltage divider value of the output voltage V O , that is, a feedback voltage V FB , is divided by the resistors R D1 and R D2 of the voltage divider, and the feedback voltage V FB is input to the second control. One of the first comparators A1 of the comparator 105 has an inverting input, and a first reference voltage V REF is input to the non-inverting input of the first comparator A1. Alternatively, as a method of replacing the feedback voltage V FB , the sensing resistor R C connected in series with the load 18 is drawn to the sensing voltage V CS characterizing the magnitude of the flow through the load 18, and the sensing voltage V CS is input to the second controller 105. The inverting input of the first comparator A1. In addition, the output of the first comparator A1 is connected to the set terminal S of the RS flip-flop 105a, and the signal S ON output by the one of the second controllers 105 is input to the reset terminal R of the RS flip-flop 105a. And a one-shot or one-click circuit 105b is connected between the Q output of the RS flip-flop 105a and the on-time generator 105c. In the second controller 105, the first switch SW 41 and the second switch SW 42 are located on a branch of the reference ground potential VSS, the node N 2 being the second end of the first switch SW 41 and the second switch SW 42 a common node at a first end of the interconnect, the node N 4 is connected to the VSS reference ground potential, and the node N 4 is a node of the second switch SW 42 at the second end.

For the first controller 104, it includes a second comparator A2, and further a second comparator having a positive input terminal connected to a node A2 is N 1, and has a ground terminal GND connected to a node N 3, A resistor R 41 connected between the node N 1 and the node N 3 is also provided. A second reference voltage V TH is input to the inverting input of the second comparator A2. Wherein the node N 1 of the first controller 104 and second controller 105 is connected to node N belongs to a coupling capacitor C 21 of element 106, the first controller 104 of the node N 3 between the 105 and the second controller 2 A capacitor C 22 belonging to the coupling element 106 is connected between the nodes N 4 . Although the twisted pair structure of the coupling element 106 and the Ethernet network are completely different, they have similar data transmission functions. For example, the node N 1 can be regarded as the receiving interface RX1+ of the first controller 104, and the node N 3 can be regarded as Corresponding to the receiving interface RX2- of the first controller 104, the node N 2 can be regarded as the transmitting interface TX1+ of the second controller 105, and the node N 4 can be regarded as the sending of the second controller 105. Interface TX2-.

The interaction between the first controller 104 and the second controller 105 to discuss the implementation of the first pulse signal S 1 of the main switch Q1 is now discussed from a system perspective, which needs to be explained with the aid of FIGS. 6A and 6B. . When the inverting terminal of the first comparator A1 in the second controller 105 separately inputs the feedback voltage V FB or separately inputs the sensing voltage V CS , when the feedback voltage V FB or the sensing voltage V CS starts to be higher than the positive phase end When a reference voltage V REF is low, that is, an event occurring at time T 1 in FIG. 6B, the output of the first comparator A1 is a logic high level, so the RS flip-flop 105a is set to output the output terminal Q. The control signal SQ jumps to a logic high level, so that the control signal SQ turns on the first switch SW 41 in FIG. 6A, but the signal inverted by the inverter signal 105 is inverted to the logic low level, so the signal is turned off. Two switches SW 42 . Since the first switch SW 41 SW 42 turns on the second switch is OFF, the reference potential may be lower than the ground potential VSS to the ground GND potential, between the second transfer signal from the controller 105 to the first controller 104, will Along the biasing circuit 105d, the first switch SW 41 , the node N 2 , the capacitor C 21 , the node N 1 , the resistor R 41 , the node N 3 , the capacitor C 22 , the node N 4 , the reference ground potential VSS A current path is formed on loop LOOP1, at which point the positive voltage source provided by bias circuit 105d begins to charge capacitor C 21 in coupling element 106 through first switch SW 41 and node N 2 that are turned on, then node N 2 That is, the change state of the charging voltage VTX1 at the transmission interface TX1+ is gradually increased as shown in FIG. 6B. And the change state of the charging voltage V RX1 at the node N 1 , that is, the receiving interface RX1 + is also shown in FIG. 6B. Since the voltage across the capacitor C 21 cannot be abruptly changed, the voltage V RX1 at the time T 1 has almost the maximum value, and As the voltage between the plates of the capacitor C 21 is gradually increased, the voltage V RX1 at the receiving interface RX1+ is gradually lowered. At this stage, since the charging voltage V RX1 at the node N 1 , that is, the receiving interface RX1+ is greater than the second reference voltage V TH , the output result of the second comparator A2, that is, the generated first pulse signal S 1 is a logic high level. Thus, the main switch Q1 is turned on by the first pulse signal S 1 coupled to the control terminal of the main switch Q1. It should be noted that since the first pulse signal S 1 has started to control the main switch Q1, in the start-up phase of the voltage converter, the output of the drive control circuit in the first controller 104 is used for control. an initial pulse signal of the primary switch Q1 stops generating, complete control is started by the main switch Q1 of the first pulse signal S 1, except the voltage converter can restart the power required again with the initial pulse signal to start the main switch Q1.

6B, a first pulse signal S T 1 time 1 caused this state continues until time T 2 to the time T 2, on-time generator 105c set on-time T ON ends, so that the on-time generator 105c generates A logic high level signal S ON is sent as a reset signal to the reset terminal S of the RS flip-flop 105a, so that the control signal SQ outputted from the Q output terminal of the RS flip-flop 105a is flipped to a logic low level, so that the control signal SQ is off. The first switch SW 41 in FIG. 6A is opened, but the signal inverted by the control signal SQ through the inverter 105e is at a logic high level, so that the second switch SW 42 is turned on. Since the second switch SW 42 is turned on when the first switch SW 41 is turned off, from the second controller 105 to the first controller 104, along the node N 2 , the second switch SW 42 , the node N 4 , the capacitor C 22 , node N 3 , resistor R 41 , node N 1 , capacitor C 21 return to node N 2 to form a closed loop LOOP2, and a portion of the charge stored by capacitor C 21 and capacitor C 22 is neutralized and neutralized by resistor R 41 Consumption. Therefore, starting from the time T 2, the capacitor C 21 to release a charge resulting in N 2 at a node that is transmitting the charging voltage VTX1 interface TX1 + at gradually reduced because the voltage of the capacitor C 21 can not mutations resulting in at time T 2 at too node N 1 That is, the voltage V RX1 at the receiving interface RX1+ is pulled down to a negative value that occurs briefly. As the capacitor C 21 and the capacitor C 22 discharge the charge, the voltage V RX1 at the receiving interface RX1+ is close to the static zero potential at the time T 3 , and the node The voltage VTX1 at the N 2 , that is, the transmission interface TX1+ is also close to the static zero potential at the time T 3 , at this stage, since the voltage V RX1 at the node N 1 , that is, the receiving interface RX1+ is smaller than, for example, the second reference voltage V close to zero potential. TH, resulting in the output of the second comparator A2 that is generated by the first pulse signal S 1 is at a logic low level, so that the first pulse signals S 1 to turn off the main switch Q1. As seen from FIG. 6B, the on-time T ON between the time T 1 and the time T 2 is the phase in which the main switch Q1 is turned on, and the off-time T OFF between the time T 2 and the time T 3 is the main switch Q1 is turned off. The stage, referring again to FIG. 1, has explained above that the second pulse signal S 2 is the first pulse signal S 1 or the inverted signal of the control signal SQ, so the second pulse signal S 2 is at the on time T ON and logic state and the off time T OFF signals S 1 opposite to the first pulse may be the second switch Q2 generates a sync pulse signal S 2 for controlling the secondary side 105 by the second control means.

During the period in which the main switch Q1 is turned on, the main-side current flows through the main-side winding L P for energy storage. At this time, since the synchronous switch Q2 is turned off, no current flows through the secondary-side winding L S , and the output capacitor C OUT supplies power to the load 18 . In the phase in which the main switch Q1 is turned off, the main-side current is reduced to zero, the main-side winding L P releases energy, and the energy of the main-side winding L P is transmitted to the secondary-side winding L S and the auxiliary winding L AUX , at which time the synchronous switch Q2 is turned on. A current flows through the secondary winding L S and the synchronous switch Q2, the secondary winding L S supplies a load current to the load 18 and charges the output capacitor C OUT , and the auxiliary winding L AUX also charges the capacitor C AUX serving as a power source. Generating on on-time controller 105c determines the on-time T ON delay mode measure, in conjunction with FIGS. 6A and 6B, the example may be triggered by a control signal SQ RS 105a outputted from the flip-flop rising Rising-edge at time T 1 of a single The steady state flip-flop 105b generates a narrow clock pulse CLK1 of the continuous nanosecond level. It should be noted that the narrow clock pulse CLK1 is only high level on the rising edge of the control signal SQ, and the other time is low level. The clock pulse CLK1 notifies the on-time generator 105c to start timing, and the on-time generator 105c retransmits the high-level signal S ON by the on-time generator 105c at the timing when the timing is just after the preset on-time T ON ends. The controller 105a, therefore, this control mode can be regarded as a control mode of constant on-time substantially. According to the inventive spirit of the present invention, the duration of the preset constant on-time T ON during each switching cycle is also It can be adjusted, for example, we can design a minimum constant on-time T ON-MIN or a maximum constant on-time T ON-MAX that meets the requirements.

Referring to Figure 6C, an alternative embodiment based on Figure 6A is shown. Considering that the switching frequency f of the main switch Q1 decreases as the input voltage V IN increases or as the input voltage V IN decreases, and the frequency f decreases as the on-time T ON increases or The on-time T ON decreases and increases. If the switching frequency f is too small, the core flux of the transformer T cannot be restored to the starting point of the hysteresis loop, causing the core to be oversaturated, for example, the input voltage V IN is increased. If the switching frequency f is too small, the transformer T will be saturated. At this time, once the core cannot withstand the voltage, it is easy to burn. In this embodiment we will overcome this problem. When the main switch Q1 is turned on but the synchronous switch Q2 is turned off, the secondary side winding L S has no current, but can be interconnected from the second end of the secondary winding L S as the name end and the first end of the synchronous switch Q2. retrieving a node voltage V SAM sample volume of this node, and the secondary winding L S of the second end of the period the voltage V SAM is approximately equal to the number of turns of the secondary side winding L S than on the primary side winding NS L P The parameter NP then multiplies the ratio NS/NP by the input voltage V IN , which means that the voltage V SAM is related to the magnitude of the input voltage V IN . Based on this correlation, the conduction time of perceived magnitude of the voltage generator 105c of V SAM, whereby as a basis to generate the appropriate on-time T ON to suppress the switching frequency f of the magnetic core is reduced to an abnormal state caused by the saturation. As shown in FIGS. 6C and 6D, the sense voltage drop V CS or the feedback voltage V FB is smaller than the first reference voltage V REF , which causes the first comparator A1 to output a high level to the set terminal S of the RS flip-flop 105a. The control signal SQ generated by the Q output of the RS flip-flop 105a is inverted from a low level to a high level, and the output of the control signal SQ to the monostable flip-flop 105b causes the monostable flip-flop 105b to be low-powered at the control signal SQ. The clock signal CLK1 is generated at the time when the rising edge of the flipping to the high level is turned flat. The on-time generator 105c includes a sample-and-hold (S/H) 105c-1 and a voltage-to-current converter 105c-2, and further includes a third switch SW51 and a capacitor C T , wherein the input of the sample holder 105c-1 The second end of the terminal connected to the secondary winding L S is like a terminal, the output of the sample holder 105c-1 is connected to the voltage input terminal of the voltage-current converter 105c-2, and the power supply voltage V DD is a voltage-current converter 105c- 2 The operating voltage is supplied. The current output terminal of the voltage-current converter 105c-2 and one end of the capacitor C T are connected to the node N T , and the other end of the capacitor C T is connected to the ground GND. A first end of the third switch SW51 is connected to node N T and a second end connected to the ground terminal GND so that the third switch SW51 and the capacitor C T is the parallel relationship, the control input terminal of the third switch SW51 105b monoflop The generated clock signal CLK1. On-time generator 105c further includes an end a third comparator A3, the positive-phase input terminal of the third comparator A3 is connected to the capacitor C T is charging i.e. node N T, in a third inverting input of comparator A3 is The terminal inputs a third reference voltage V P .

Referring to FIG. 6C, the operation mechanism of the on-time generator 105c to adjust the on-time T ON is to sample the second end of the secondary winding L S by the sample holder 105c-1 as the voltage V SAM of the name terminal, and the timing of the sampling is, for example, It is the time when the main switch Q1 is turned on and the synchronous switch Q2 is turned off. If the input voltage V IN is larger, the voltage value held by the sample holder 105c-1 is larger, and the current outputted by the voltage current converter 105c-2 is larger. . Vice versa, the smaller the input voltage V IN is, the smaller the voltage value held by the sample holder 105c-1 is, resulting in the smaller the current output by the voltage current converter 105c-2. Since the clock signal CLK1 for driving the third switch SW51 is at a high level only at the rising edge of the control signal SQ generated by the RS flip-flop 105a, the other time is a low level, so that the timing of the rising edge of the control signal SQ When the third switch SW51 is turned on, the charge stored at one end of the capacitor C T , that is, the node N T is released at the moment when the third switch SW51 is turned on, so the output of the third comparator A3 is At this time, a signal S ON which is output and is low is generated. In Fig. 6D, the timing of the rising edge of the control signal SQ is the timing at which the preset period T SET starts. After the rising edge of the control signal SQ ends, the clock signal CLK1 is turned back to the low level again. As long as the third switch SW51 is turned on and then turned off, the capacitor C T is again charged by the current output from the voltage-current converter 105c-2. . Once the continuous charging capacitance C T in the conduction period T ON, the voltage at the node N T starts in the off-period T OFF after the end of the on period T ON is greater than the third reference voltage V P. The final result is that the signal S ON generated at the output of the third comparator A3 is raised from the low level in the on period T ON to the high level in the off period T OFF , and the signal S ON is input again. The reset terminal R of the RS flip-flop 105a, so the high-level signal S ON resets the RS flip-flop 105a, causing the control signal SQ generated at the Q output thereof to fall from the high level in the on-period T ON to the off-period T Low level within OFF . Control signal SQ in the OFF period T OFF is a continuous low level until the end of the off period T OFF further continued low until the next sensing piezoelectric drop or V CS than the first feedback voltage V FB reference The voltage V REF is small, and the first comparator A1 asserts a high level again to set the RS flip-flop 105a to output a high level. And the output terminal of the third comparator A3 produces the signal S ON OFF period T OFF in the sustained high until after further continuation of the off-period T OFF is high, unless the SQ control signal until the next There is a rising edge, so that the clock signal CLK1 appears high level to turn on the third switch SW51, so that the node N T of the capacitor C T is transiently discharged, and the third comparator A3 generates the low level signal S ON again. .

Referring to FIG. 6C, the larger the input voltage V IN is, the larger the voltage value held by the sample holder 105c-1 is, and the larger the current value outputted by the voltage current converter 105c-2 is, thereby reducing the charging time, and soon. Let the voltage at the node N T at one end of the capacitor C T exceed the third reference voltage V P , which is equivalent to the length of the shortening period T ON during the entire switching period, and the control signal SQ is high level during the period T ON and is The on-time of the main switch Q1, so the on-time T ON is shortened when the input voltage V IN is larger, corresponding thereto, the control signal SQ is the low level and the off-time of the main switch Q1 in the period T OFF . In other words, although the increase of the input voltage V IN is intended to lower the switching frequency f, the effect of shortening the on-time T ON is to suppress the degree of reduction of the switching frequency f. Vice versa, once the input voltage V IN is smaller, the smaller the voltage value held by the sample-and-holder 105c-1 is, the smaller the current value outputted by the voltage-current converter 105c-2 is, and the charging time is delayed, and finally The slower speed causes the voltage at the node N T at one end of the capacitor C T to exceed the third reference voltage V P , which is equivalent to the length of time during which the period T ON is appropriately extended throughout the switching period, so the input voltage V IN is more Small, causing the on-time T ON of the main switch to be extended. In other words, although the input voltage V IN is lowered to increase the switching frequency f, the effect that the on-time T ON is extended is to suppress the increase in the switching frequency f. It will be apparent that this embodiment of the invention provides excellent protection of the relative steady state of the switching frequency f.

For example, in the discontinuous DCM mode, the switching frequency f = (2 × I O × L × V O ) ÷ {(V IN ) 2 × (T ON ) 2}, where L is the equivalent inductance value of the transformer T, according to the present invention The scheme provided above, obviously, whether the input voltage V IN decreases or increases, the variation value of the calculated value of (V IN ) 2 × (T ON ) 2 in the functional relationship is not large, and the switching frequency f can be suppressed. The amount of change/amplitude thus avoids damage to the transformer T entering saturation.

Referring to Figure 7A, the most significant difference compared to the embodiment of Figure 6A is that the component type of the coupling element 106 is altered while the other features are substantially the same. The coupling element 106 is a pulse transformer PT, wherein the circuitry of the second controller 105 and the manner in which the control signal SQ is generated have been explained above and will not be described again. In this embodiment, the pulse transformer PT serves as a transmission medium for data signal interaction between the first controller 104 and the second controller 105, and has a primary side or a primary winding L PT1 and a secondary side or a secondary side. Winding L PT2 , main side winding L PT1 is connected to second controller 105, and secondary side winding L PT2 is connected to first controller 104. The primary side winding L PT1 is provided with a first end for receiving the control signal SQ produced by the RS flip-flop 105a and a second end coupled to the reference ground potential VSS, and the first end of the secondary winding L PT2 . As the name end can generate the first pulse signal S 1 for driving the main switch Q1 and the second end is used to be coupled to the ground GND as a different name. Although the control signal SQ is directly input to the first end of the primary side winding L PT1 , and the output result of the first end of the secondary winding L PT2 is directly used as the first pulse signal S 1 , it is theoretically feasible, but to secure the signal Without error, the present invention provides the embodiment of Figure 7A. The control signal SQ can be transmitted to the input of a buffer A4, and the output of the buffer A4, that is, the node N5 and the first end of the main winding L PT1 is connected with a capacitor C 52 , the main winding L PT1 The two terminals are connected to a lower potential or a reference ground potential VSS at node N7. A capacitor C 51 is connected between the first end of the secondary winding L PT1 and a signal generating node N S for outputting the first pulse signal S 1 , and the second end of the secondary winding L PT2 is connected to a node N6 Ground GND. And optionally connecting the cathode of one diode D 51 to node N S and the anode to ground GND at node N6, and optionally also connecting a resistor R 51 between node N S and node N6 . The working mechanism of the pulse transformer PT is embodied in that the capacitor C 52 isolates the direct current, and when the control signal SQ is turned to a high level, the capacitor C 52 is charged, and the first end of the main side winding L PT1 is raised as the potential of the name end. Interface located in the main transmission side winding L PT1 at the first end node in FIG. 7B TX1 + voltage waveform VTX1 coarse primary winding L PT1 considered node at a second end TX2 - transmission interface, a control pulse transformer PT signal SQ Passed to the secondary winding L PT2 , the first end of the secondary winding L PT2 is also raised as the potential of the terminal, as shown in FIG. 7B, the rough waveform of the voltage V RX1 of the receiving interface RX1+ at the first end node of the secondary winding L PT2 The node at the second end of the secondary winding L PT2 is regarded as the receiving interface RX2-. In this process, the potential of the node N S is also synchronously raised due to the coupling of the capacitor C 51 . If the Schottky diode D 51 is used, the clamping effect of the diode D 51 can also make the potential of the node N S It rapidly increases to output a high-level first pulse signal S 1 at the node N S . Conversely, once the control signal SQ is turned low, the capacitor C 52 is discharged through the main side winding L PT1 , and the capacitor C 51 is also discharged through the secondary winding L PT1 and the resistor R 51 , so that the signal generation node N The potential of S drops rapidly, thereby generating a low-level first pulse signal S 1 at the signal generating node N S , and the first pulse signal S 1 changes synchronously as the logic state of the control signal SQ is inverted. The second pulse signal S 2 is an inverted signal of the first pulse signal S 1 , and the waveform diagram is as shown in FIG. 7B .

Referring to FIG. 7C, this embodiment is slightly different from FIG. 7A. In the embodiment of FIG. 7A, the inverting input terminal of the first comparator A1 in the second controller 105 is input with the feedback voltage V FB or the sensing voltage V. One of the CSs , but the output of the filter 105g and the output of the amplifier 105h in the embodiment of Fig. 7C are added by an adder 105i and then fed to the inverting input of the first comparator A1. Ripple actual waveform ripple voltage at the output node N 20 of the embodiment shown in FIG. 8 in the output node N 20 or FIG. 1 is later described in detail with upcoming AC component and a DC component, ripple The average voltage value of the voltage corresponds to the voltage level of the DC component, and the total ripple voltage minus the voltage value of the DC component is substantially equal to the voltage value of the AC component. Since the feedback voltage V FB is the divided voltage value taken at the output node N 20 , it is essentially a partial voltage of the actual ripple voltage. Further characterization of the sensing voltage V CS is the magnitude of the load current I O, showing a direct current component DC load current I O characteristics is much greater than with alternating current component with it, so that the sensing voltage V CS is cross A DC signal whose average voltage value is equal to the voltage value of its DC component. In Fig. 7C, the actual ripple voltage is supplied to a filter 105g for filtering out the DC component of the actual ripple voltage and retaining and outputting only the AC component. It can be considered that the filter 105g will feed back the voltage V FB . The total voltage value minus the voltage value of the DC component among them gives the voltage value of the AC component among them. In FIG. 7C, the voltage drop generated by the load current I O on the sense resistor R C , that is, the sense voltage V CS is supplied to an amplifier 105h, and the sense voltage V CS is amplified by the amplifier 105h and output. The filter 105g outputs a signal of the AC component obtained by filtering out the DC component of the feedback voltage V FB to the adder 105i, and the amplifier 105h outputs the signal with the AC component and the DC component amplified by the sensing voltage V CS to the adder. 105i, the adder 105i adds the signal output from the filter 105g and the signal output from the amplifier 105h to the inverting input terminal of the first comparator A1. The embodiment of Figure 7C is identical to Figure 7A except that the inverting input of the first comparator A1 is not the direct feedback voltage V FB or the sense voltage V CS . And the adder 105i adds the signal output from the filter 105g and the signal output from the amplifier 105h to the inverting input terminal of the first comparator A1 to replace the feedback voltage of the inverting input terminal of the first comparator A1. V FB or sense voltage V CS is also applicable to the embodiment of Figures 6A and 6C.

Referring to Figure 8, the greatest difference between this embodiment and Figure 1 is that the first end of the secondary winding L S is connected to the output node N 20 via a rectifying diode D REC, such as a different name end. And the synchronous switch Q2 in FIG. 1 can also be discarded. At this time, the second end of the secondary winding L S can be directly coupled to the reference ground potential VSS as the name terminal. The anode of the rectifying diode D REC is connected to the first end of the secondary winding L S and the cathode is connected to the output node N 20 , and the starting voltage ST can be drawn from the cathode of the rectifying diode D REC . If the synchronous switch Q2 is canceled, it is not necessary to generate the second pulse signal S 2 . Otherwise, the operational working mechanism of FIG. 8 is the same as that of FIG. 1 and will not be described here.

In the voltage converter, if the load 18 becomes light or no load, the load current I O will be significantly reduced, which also causes the switching frequency f of the main switch Q1 to decrease, and the light load of the load 18 mentioned here is light load. The situation or the empty load is relative to its overloaded Heavy load case. Moreover, the switching frequency f is closely related to whether the voltage converter enters the audio zone. If the switching frequency f is too low, parasitic oscillation will occur. For example, if the electric user hears the howling sound from the transformer, the switching frequency f may be reduced to about 20 Hz.

Referring to Fig. 9, in this embodiment, the audio converter adaptively determines the audio discomfort caused by the reduction of the switching frequency f. Regardless of the embodiment of FIG. 6A or FIG. 7A or FIG. 7C, one of the feedback voltage V FB or the sensing voltage V CS or the signal output by the adder 105i is regarded as the detection signal DE, so the detection signal DE can be used. To characterize the instantaneous magnitude of the output voltage V O and/or the load current I O provided to the load 18. The detection signal DE is input to the inverting input terminal of the first comparator A1, and the first reference voltage value V REF is input to the non-inverting input terminal of the first comparator A1, and when the detection signal DE is lower than the first reference voltage value At V REF , the high level of the output of the first comparator A1 sets the set terminal S of the RS flip-flop 105a, and the RS flip-flop 105a starts outputting the control signal SQ of the high level, and the high-power is generated when the on-time generator 105c is generated. When the flat signal S ON is supplied to the reset terminal R of the RS flip-flop 105a, the RS flip-flop 105a starts outputting the control signal SQ of the low level, which has been described in detail above and will not be described again. In the embodiment of Figure 9, only a portion of the components of the voltage converter are illustrated, while an optional but non-essential embodiment of the on-time generator 105c is also deliberately shown. In FIG. 9 and FIG. 10, once the detection signal DE is lower than the first reference voltage value V REF , the timing at which the control signal SQ transitions from the low level to the high level triggers the one shot 115b to be issued. Clock signal CLK. In the embodiment of FIG. 10, two adjacent time periods in which the detection signal DE is lower than the first reference voltage value V REF are taken as an example. For example, a detection signal DE occurs in a first time period TIME1 (for example, some A detection signal DE1) is lower than the first reference voltage value V REF , at which time the voltage converter modulates the output voltage V O and/or the load current I O by generating the control signal SQ1 to turn on the main switch Q1. Therefore, by the voltage modulation, the end period detection signal DE of the first period TIME1 just returns to a state larger than the first reference voltage value V REF , and then the detection signal DE occurs in a second period TIME 2 (for example, a certain detection) When the signal DE2) is lower than the first reference voltage value V REF again, the voltage converter needs to control the increase of the output voltage V O and/or the load current I O by the control of the control signal SQ2 to turn on the main switch Q1. The modulation causes the second period TIME2 end point detection signal DE to return to be greater than the first reference voltage value V REF , thus looping.

Referring to FIG. 10, during the first time period TIME1, the detection signal DE1 is lower than the first reference voltage value V REF . At the start time of the first time period TIME1, the high level comparison result of the first comparator A1 causes the RS flip-flop 105a to be set. The bit generates a high level control signal SQ1. At this moment, the control signal SQ1 is flipped from the previous low level to the rising edge of the high level, so that the monostable flip-flop 105b is clicked to emit a high-level narrow pulse. The clock signal CKL1, this process can be understood in conjunction with FIG. 6A and FIG. 7A or FIG. 7C. The clock signal CKL1 generated by the one-shot 115b triggers the on-time generator 105c to start the on-time TO N 1 , and the signal S ON1 from the third comparator A3 during the on-time T ON1 at which the main switch Q1 is turned on. Continues low. After the end of the on-time T ON1 , the third comparator A3 in the on-time generator 105c issues a high-level signal S ON1 as a reset signal, causing the RS flip-flop 105a to reset and inverting the control signal SQ1 to a low state. During the first time period TIME1, the main switch Q1 may have a plurality of switching periods instead of the number of illustrations, and a preset time period T SET -A is counted from the start time point of the first time period TIME1, after one or more switches The period until the end of the preset time period T SET -A, the detection voltage DE is larger than the first reference voltage V REF according to the expected setting, and the control signal SQ1 is at a low level, and the time is followed by the clock signal CLK1. The next high-level narrow clock signal has not appeared yet, so the capacitor C T has no transient discharge, and the signal S ON1 output from the third comparator A3 is maintained at a high level.

Referring to FIG. 10, after the end of the first time period TIME1, due to the voltage modulation effect of the voltage converter, the detection signal DE is returned to a state greater than the first reference voltage value V REF , and the comparison result of the first comparator A1 is Low level. After a period of time, the detection signal DE2 is again lower than the first reference voltage value V REF in a second period TIME2, and the high level comparison result of the first comparator A1 causes the RS to be triggered at the start time of the second period TIME2. The controller 105a sets a control signal SQ2 that generates a high level. At this moment, the control signal SQ2 is flipped from the previous low level to the rising edge of the high level, so that the one shot 115b is clicked and emits a high level. The narrow pulse is also the clock signal CKL2. The clock signal CKL2 generated by the one-shot 115b triggers the capacitor C T to be discharged lower than the third reference voltage V P . At this time, the on-time generator 105c starts the timing of the on-time T ON2 , and the main switch Q1 is turned on. S ON2 signal on-time T ON2 third comparator A3 emitted continuously at a low level. After the end of the on-time T ON2 , the capacitor C T is charged to exceed the third reference voltage V P , and the third comparator A3 in the on-time generator 105c issues a high-level signal S ON2 as a re-signal, allowing the RS flip-flop 105a Reset and turn control signal SQ2 to a low state. Also in the second time period TIME2, the main switch Q1 may have a plurality of switching periods instead of the number of illustrations, and one preset time period T SET -B is timed from the starting time point of the second time period TIME2, after one or more The switching period until the end of the preset time period T SET -B, the detection voltage DE is greater than the first reference voltage V REF as expected to meet the load demand, at which time the control signal SQ2 is low, and the time Moreover, since the next high-level narrow clock signal subsequent to the clock signal CLK2 has not appeared yet, the capacitor C T has no transient discharge, and the signal S ON2 output from the third comparator A3 is maintained at the high level.

Referring to FIG. 9, the feedback voltage V FB or the sense voltage V CS or the output signal of the adder 105i generated by the adjacent previous preset time period T SET -A and the subsequent preset time period T SET -B will be low. Taking the case of the first reference voltage V REF as an example, it is clarified how the present invention avoids the transformer T howling and directs the switching frequency f out of the audio zone when the switching frequency f is too low. Any one of the feedback voltage V FB or the sensing voltage V CS or the output signal of the adder 105i is regarded as the detection signal DE. In FIGS. 9 and 10, the clock signal CLK1 generated at the time of the control signal SQ1 in the previous preset period T SET -A has the frequency value F because the number of high-level narrow pulses of the clock signal CLK1 may be more than the number of times during the period Once, so there may be one or more cases of frequency value F. In Fig. 9, a clock generator 113 is provided which includes at least an oscillator 113a which generates an oscillation signal and outputs it to the frequency divider 113b, and a frequency divider 113b which changes the frequency of the oscillation signal to provide An upper frequency threshold FH and a lower frequency threshold FL are output to the frequency comparator 114 as a reference frequency, whereby the frequency comparator 114 can increase the frequency value F of the clock signal CLK1 triggered by the rising edge of the control signal SQ1. The frequency threshold FH is compared to the lower frequency threshold FL. The counter 115 has an addition calculator and a subtraction counter, and the initial count value of the counter 115 can be pre-assigned. When a certain frequency value F is greater than the upper frequency threshold FH, the limit counter 115 is decremented by 1 based on the initial value of the assigned count. When a certain frequency value F is lower than the lower frequency threshold FL, the limit counter 115 is incremented by 1 based on the initial value of the assigned count, and whether the addition or the subtraction is performed is determined by the comparison result of the frequency comparator 114. The comparison result is passed to the counter 115, by which the counter 115 executes the previously defined operation rule. In the preset time period T SET -A, according to the comparison of the magnitude of the corresponding frequency value F of each high-level narrow pulse clock signal CLK1 with the reference frequency, the counter 115 is sequentially incremented or decremented by one. Moreover, based on the number of types corresponding to the frequency value F (e.g., 5 different frequency values), the same number of counts (e.g., 5 counts) is executed by the counter 115, and the final counter 115 produces a total value. In addition, the counter 115 is further defined with a counting condition, that is, the counter 115 is defined with an upper critical count value and a lower critical count value, and once the total value exceeds the upper critical count value, the defined total value is equal to the upper critical count value, or when When the total value is lower than the lower critical count value, the defined total value is equal to the lower critical count value. Or when the total value is equal to one of the upper critical count value or the lower critical count value, the defined total value does not need to be changed.

For ease of understanding, it is assumed that in an exemplary but non-limiting embodiment, a plurality of high-level narrow pulse clock signals CLK1 corresponding to five different frequencies within a preset time period T SET -A may also be considered as a clock signal CLK1. The total number of frequency values F is five. In this case, the initial value of the count of the counter 115 is exemplified by the binary symbol BIT[00] embodied as a two-digit element, and the lower critical count value is defined as a two-ary binary symbol BIT[00] ], and the upper critical count value is defined as the two-ary binary symbol BIT [11]. When the total number of frequency values F of the clock signal CLK1 is five, each frequency value is compared with the frequency threshold value FH and the lower frequency threshold value FL according to the time node appearing, and is executed by the frequency comparator 114, before and after comparison. The obtained results are assumed to be: the first frequency value is lower than the lower frequency threshold FL, the second frequency value is higher than the upper frequency threshold FH, the third frequency value is lower than the lower frequency threshold FL, and the fourth frequency is The value is higher than the upper frequency threshold FH, and the fifth frequency value is lower than the lower frequency threshold FL. According to the counting rule defined above, the counter 115 counts the number of high-level narrow pulse clock signals CLK1, and the counter 115 counts The counting step performed five times before and after the initial value BIT[00] is embodied in that the comparison result of the frequency comparator 114 triggers the addition counter of the counter 115 to be valid and increases by 1, when the first frequency value is lower than the lower frequency threshold FL. When the second frequency value is higher than the upper frequency threshold FH, the comparison result of the frequency comparator 114 triggers the subtraction counter of the counter 115 to be valid and decremented, and the third frequency value is lower than the lower frequency threshold FL. The comparison result of the comparator 114 triggers the addition counter of the counter 115 to be valid and increases 1. When the fourth frequency value is higher than the upper frequency threshold FH, the comparison result of the frequency comparator 114 triggers the subtraction counter of the counter 115 to be valid and subtracts 1 and 5 When the frequency value is lower than the lower frequency threshold FL, the comparison result of the frequency comparator 114 triggers the addition counter of the counter 115 to be valid and increments by 1, so that the initial value of the count BIT [00] is obtained after the second and the last counts are counted five times in total. The total value is BIT[01]. In another example, it is assumed that the above-mentioned count initial value BIT[00] and lower critical count value BIT[00] and upper critical count value BIT[11] are unchanged, but the range of five frequency values has changed. The counting step performed by the counter 115 five times before and after counting the initial value BIT[00] is embodied in that the comparison result of the frequency comparator 114 triggers the subtraction counter of the counter 115 when the first frequency value is higher than the upper frequency threshold FH. Valid and decremented 1. The second frequency value is higher than the upper frequency threshold FH. The comparison result of the frequency comparator 114 triggers the subtraction counter of the counter 115 to be valid and decremented. 1. The third frequency value is higher than the upper frequency threshold FH. The comparison result of the comparator 114 triggers the subtraction counter of the counter 115 to be valid and decrements. The fourth frequency value is higher than the upper frequency threshold FH. The comparison result of the frequency comparator 114 triggers the subtraction counter of the counter 115 to be valid and subtracts 1 and 5 When the frequency value is higher than the upper frequency threshold FH, the comparison result of the frequency comparator 114 triggers the subtraction counter of the counter 115 to be valid and decremented by 1, in which case the total value is smaller than the lower critical count value BIT [00] So under the assigned threshold count BIT [00] ultimately deemed total value. In another reverse example, it is assumed that the count initial value BIT[00] and the lower critical count value BIT[00] and the upper critical count value BIT[11] are unchanged, but the range of the five frequency values is changed, the counter 115 The counting step performed five times before and after the counting initial value BIT[00] is embodied in that the comparison result of the frequency comparator 114 triggers the addition counter of the counter 115 to be effective when the first frequency value is lower than the lower frequency threshold FL. 1. When the second frequency value is lower than the lower frequency threshold FL, the comparison result of the frequency comparator 114 triggers the addition counter of the counter 115 to be valid and adds 1. When the third frequency value is lower than the lower frequency threshold FL, the frequency comparator 114 The comparison result triggers the addition counter of the counter 115 to be valid and increases 1. When the fourth frequency value is lower than the lower frequency threshold FL, the comparison result of the frequency comparator 114 triggers the addition counter of the counter 115 to be valid and adds 1 and the fifth frequency value. The comparison result of the frequency comparator 114 below the lower frequency threshold FL triggers the addition counter of the counter 115 to be valid and increments by 1, in which case the total value after five counts is greater than the upper threshold Value BIT [11], so the assigned threshold count BIT [11] ultimately deemed total value.

Referring to FIGS. 9 and 10, the counter 115 described above counts the frequency value F of the clock signal CLK1 in the last preset time period T SET -A, and the total value is finally transmitted and encoded/burned by the counter 115. Stored in a register 116. On the count of a predetermined frequency value SET -A period T F. The significance of the next adjacent one of the predetermined conduction time period T SET -A T ON2 relative to the predetermined period T SET -A the on-time T ON1 is adjusted, and the basis for implementing the adjustment is the total value corresponding to the frequency value F. Adjusting the on-time T ON2 manner Referring to Figure 9, generator 105c to the on-time of FIG. 9, includes a fixed current source 110 and the two optional additional current sources 111 and 112, further comprising a third switch SW51 and A capacitor C T , the supply voltage V DD provides an operating voltage for the fixed current source 110 and the two additional current sources 111, 112. Wherein the output current I 0 110 fixed current source directly to the node N T C T at the end and can continue the charging to the capacitor C T, C T relative to the other end of the capacitor connected to the ground terminal GND. But the connection between the node N T additional current sources 111 and the capacitor C T to an end of a fourth switch SW 61, a first terminal for receiving the fourth current source 111 outputs an additional switch SW 61 of the current I 1 and a second end connected to the node N T, only the control terminal of the fourth switch SW 61 receives a high level so that the fourth switch SW 61 is turned on, additional current source 111 will be output from the current I 1 from the N T C T is the capacitance at node Charging. Similarly current, is connected between the node N T additional current source 112 and another capacitor C T to the other end of the fifth switch SW 62, a first output terminal for receiving an additional current source 112 of the fifth switch SW 62 and the I 2 a second terminal connected to node N T, only the control terminal of the fifth switch SW 62 receives a high level such that the fifth switch SW 62 is turned on, additional current source 112 outputs a current I 2 at the node N T will Charge the capacitor C T . A first terminal connected to a third voltage to current converter switches 105c-2 SW51 to node N T and a second end connected to the ground terminal GND so that the third switch SW51 and the capacitor C T is the parallel relationship, the third switch SW51 The control terminal input monostable flip-flop 105b is a high-level clock signal CLK1 formed by the rising edge of the control signal SQ1 in the last preset time period T SET -A, and the third switch SW51 is transiently turned on, then the capacitor C T charge that is stored at node N T in the third switch SW51 is turned on this time freed at one end thereof, so that the output of the third comparator A3 at this time will generate a low level signal S ON1. After the rising edge of the control signal SQ1 high-level clock signal CLK1 pulse is narrow down to a low level, a fixed current source 110 to begin charging node capacitance C T N T, if the fourth switch SW 61 is turned the additional current sources 111 and a fixed current source 110 with charging capacitor C T to node N T, if the fifth switch SW 62 is turned the additional current source 112 and a fixed current source 110 charges the capacitor C T N T nodes together. CKL1 clock signal generated by a monostable flip-flop 105b trigger timing generator 105c starts timer T ON1 on-time, the signal S ON1 A3 emitted from the third comparator in the main switch Q1 is turned ON time duration T ON1 Is low. Once the capacitor C T continuously charged during the on-period T ON1, after the conduction period T ON1 voltage N T at the node capacitance C T starts than the third reference voltage V P so large that the output of the third comparator A3 is generated The signal S ON1 is flipped to a high level in the off period T OFF1 at the end of the on period T ON1 , and the signal S ON1 is again input to the reset terminal R of the RS flip-flop 105a, so the high level signal S ON1 is reset The RS flip-flop 105a causes the control signal SQ1 generated at the Q output terminal to fall from the high level in the ON period T ON1 to the low level in the OFF period T OFF1 , thereby turning off the main switch Q1. If the main switch Q1 detects that the voltage DE is still lower than the first reference voltage V REF after the first switching cycle, the main switch Q1 will start to execute the second switching cycle, and so on, until the preset time period T SET -A At the end, the detection voltage DE is intended to be larger than the first reference voltage V REF as expected. According to this switching mode, the action of the main switch Q1 being turned on during the on period T ON1 and being turned off in the off period T OFF1 can be looped multiple times in the entire preset period T SET -A.

The second controller 105 generates a high-level narrow pulse of the control signal SQ2 in the next preset time period T SET -B and the timing of the rising edge thereof according to the total value of the counter 115 in the last preset time period T SET -A CLK2. This working mechanism is embodied in that if the switching frequency f is too low in the last preset time period T SET -A, the transformer T enters the audio zone of the howling, so that the final total value of the counter 115 is greater than the preset due to the accumulated algorithm. An initial count value, which is stored in the register 116, and the binary symbol written by the register 116 is used as a control signal for controlling whether the electronic switch, that is, the fourth switch SW 61 and the fifth switch SW 62 are turned on, Once the switching frequency f is too low, the total value is greater than the initial count value. For example, the total value written by the register 116 is the bit BIT[01], or the upper critical count value BIT[11] regarded as the total value is written, and the ratio is initial. The value symbol BIT[00] is large.

According to the example described above, the total value BIT[01] is used as the control signal of the fourth switch SW 61 and the fifth switch SW 62 , and the higher bit 0 controls the fourth switch SW 61 to be turned off, and the lower bit 1 The fifth switch SW 62 is controlled to be turned on. Or the total value BIT[11] is used as the control signal of the fourth switch SW 61 and the fifth switch SW 62 , the higher bit 1 controls the fourth switch SW 61 to be turned on, and the lower bit 1 controls the fifth switch SW 62 Turn on. It should be noted that the on-time generator 105c in FIG. 9 merely shows a schematic diagram of the modeling, and some common-sense contents are not shown. For example, the control signal data of the register is known in some embodiments. It is necessary to first decode through the decoder and then use a set of decoded signals to effectively turn on or off the corresponding switch.

DE occurs when the detection voltage is lower than the first reference voltage V REF SET -B within a next predetermined period T, the rising edge of the high level narrow pulse control signal SQ2 within the preset period T SET -B trigger clock Once the signal CLK2 so that the third switch SW51 is turned on transients, the charge stored in the capacitor C T N T at node by the third switch SW51 freed, so the output of the third comparator A3 is low at this time is generated Flat signal S ON2 . After the rising edge of the control signal SQ2 clock signal CLK2 of a high level narrow pulses down to a low level, a fixed current source 110 to begin charging node capacitance C T N T, if the fourth switch SW 61 is turned the additional current sources 111 and also with fixed current source 110 to the charging node capacitance C T N T, if the fifth switch SW 62 is turned the additional current source 112 and a fixed current source 110 charges the capacitor C T N T nodes together. The total value BIT[01] of the register 116 controls the fourth switch SW 61 to be turned off and the fifth switch SW 62 to be turned on, so that the current I 2 output from the additional current source 112 and the current I 0 output from the fixed current source 110 are directly delivered to end node capacitance of N T C T C T is the capacitance of the charging, and clearly currents (I 0 + I 2) with respect to the pure faster charging current I 0, the next predetermined period T SET -B opposite The capacitor C T can be quickly filled up faster at the last preset time period T SET -A. By the same token, the total value BIT[11] of the register 116 controls the fourth switch SW 61 and the fifth switch SW 62 to be turned on, so the current I 1 output by the additional current source 111, the current I 2 output by the additional current source 112, and the fixed current I 0 110 output from the current source is directly supplied to the capacitor C T is N T at an end node of the capacitor C T charge, apparently sum of the currents (I 0 + I 1 + I 2) with respect to a simple current I 0 charging speed is more Fast, the capacitor C T can be quickly filled up faster in the following preset time period T SET -B relative to the last preset time period T SET -A. CKL2 clock signal generated by a monostable flip-flop 105b trigger timing generator 105c starts timer T ON2 on-time, the signal S ON2 A3 emitted from the third comparator in the main switch Q1 is turned ON time duration T ON2 Is low. Once the capacitor C T continuously charged during the on-period T ON2, after the conduction period T ON2 voltage N T at the node capacitance C T starts than the third reference voltage V P so large that the output of the third comparator A3 is generated The signal S ON2 is flipped to a high level within the off period T OFF2 at the end of the on period T ON2 , and the signal S ON2 is again input to the reset terminal R of the RS flip-flop 105a, so the high level signal S ON2 is reset The RS flip-flop 105a causes the control signal SQ2 generated at its Q output to fall from the high level in the on period T ON2 to the low level in the off period T OFF2 , thereby turning off the main switch Q1. If the main switch Q1 detects that the voltage DE is still lower than the first reference voltage V REF after the first switching cycle, the main switch Q1 will start to execute the second switching cycle, and so on, until the preset time period T SET -B At the end, the detection voltage DE is intended to be larger than the first reference voltage V REF as expected. According to this switching mode, the main switch Q1 is turned on during the ON period T ON2 and is turned OFF during the OFF period T OFF2 , and can be looped multiple times throughout the preset period T SET -B.

It goes without saying that an additional current source 111 and/or current source 112 are not introduced in the preset time period T SET -A, but an additional current source 111 and/or current source 112 are introduced in the preset time period T SET -B. Therefore, the conduction time period T ON2 in the preset time period T SET -B is larger because the charging current is larger, the charging time speed of the capacitance C T is faster than the conduction period T ON1 and the voltage at the node N T is faster than the third reference voltage. V P is large, and as a result, the subsequent conduction period T ON2 is smaller than the conduction period T ON1 . Considering that the switching frequency f of the main switch Q1 decreases as the conduction period T ON increases or increases as the conduction period T ON decreases, when the load 18 is lightly loaded or unloaded, the switch of the conduction period T ON1 phase When the frequency f is too small to cause the transformer T to enter the howling audio zone, since the subsequent conduction period T ON2 becomes smaller, the value of the switching frequency f is appropriately increased, and the transformer T is released from the howling audio zone.

The relative magnitude relationship between the substantially ON period T ON1 and the ON period T ON2 is highly correlated with the count initial value of the counter 115. In the exemplary but non-limiting embodiment, the fourth switch SW 61 or the fifth switch SW is the BIT [01] or BIT [10] during the preset time period T SET -A phase counter 115. 62 one of them will be turned on and the other will be turned off, then the current I 1 output by the additional current source 111 or the current I 2 output by the additional current source 112 will be together with the current I 0 of the fixed current source 110 during the on period T The ON1 phase charges the capacitor C T , and the total charging current value is (I 1 +I 0 ) or (I 2 +I 0 ), and the initial value of the count is BIT[01], for example, in the initial value of the BIT. On the basis of [01], the counting steps performed five times before and after the order of occurrence of different frequencies are: the first frequency value > the upper frequency threshold FH, the comparison result of the frequency comparator 114 triggers the subtraction counter of the counter 115 to be valid. And subtracting 1, the second frequency value < lower frequency threshold FL, the comparison result of the frequency comparator 114 triggers the addition counter of the counter 115 to be valid and adds 1, the third frequency value > the upper frequency threshold FH, the frequency comparator 114 The comparison result triggers the counter of the counter 115 to be valid and decremented by 1. When the fourth frequency value < lower frequency threshold FL is used, the comparison result of the frequency comparator 114 triggers the addition counter of the counter 115 to be valid, and the comparison result of the frequency comparator 114 is triggered when the fifth frequency value > the upper frequency threshold FH is added. The subtraction counter of the counter 115 is valid and decremented by 1, in which case the final total value is BIT[00], that is, the total charging current value of the capacitor C T charging total is I 0 during the conduction period T ON2 phase, so the capacitor C T charging the total time required for the conduction period T ON2 phase is greater than the capacitance C T conduction period T ON1 stage charging time corresponding to the conduction period T ON2 is to be greater than the conduction period T ON1, thereby causing the switching frequency f from a preset The larger value of the period T SET -A is adjusted to a smaller value of the preset period T SET -B.

In summary, in the previous preset time period T SET -A in FIG. 10, the control signal SQ1 of the secondary controller 105 on the secondary side is transmitted to the first controller 104 on the primary side through the coupling element 106, so that the first The first pulse signal S 1 generated by the controller 104 controls the main switch Q1 to have an on-time T ON1 in the switching period. In the latter preset time period T SET -B in FIG. 10, the control signal SQ2 of the secondary controller 105 on the secondary side is transmitted to the first controller 104 on the primary side through the coupling element 106, so that the first controller 104 generates The first pulse signal S 1 controls the main switch Q1 to have an on-time T ON2 in the switching period. When the preset period T SET -A counter 115 triggers the rising edge of the control signal SQ1, the number of frequency values F of the CLK1 is counted according to the counting rule, and the calculated final total value is greater than the initial count value, so that the latter preset period On-time T ON2 in T SET -B < On-time T ON1 . Vice versa, when the calculated total value is less than the initial count value, the on-time T ON2 > the on-time T ON1 in the latter preset time period T SET -B is made. When the calculated final total value is equal to the initial count value, the on-time T ON2 in the latter preset time period T SET -B is made to be the on-time T ON1 . The reason is that the total value is updated once every time the detection voltage DE is lower than the first reference voltage V REF , and the symbols in the total value directly determine the switching of the switches SW 61 and SW 62 . no. That is, when the next occurrence of the detection voltage DE is lower than the first reference voltage V REF , the total value calculated by the last detection voltage DE lower than the first reference voltage V REF determines the next detection voltage. The conduction time of the stage where DE is lower than the first reference voltage V REF . It should be noted that although the present invention is based on the two-symbol and two additional additional current sources 111, 112 as an example to explain the inventive spirit, in the actual topology, the initial value and the upper and lower count thresholds are counted. In fact, it is not limited by the number of two-bit symbols, and the number of additional current sources is not limited by the number of two branches.

In the above disclosure, the data transmission medium between the first and second controllers 104, 105, that is, the architecture of the pulse transformer PT employed by the coupling element 106 of the present invention is very important, in the corresponding diagram below. The structure of the pulse transformer PT will be described in detail in 11A to 13C.

Referring to Figure 11A, it is contemplated that all of the electronic components in the overall system of the voltage converter will be surface mounted or patched onto the PCB circuit board, and in this embodiment will be utilized as part of the physical structure of the pulse transformer PT. . It should be emphasized that the circuit board 200 in FIG. 11A is not a complete view of the PCB, and only shows the local area that needs to be used. An adjacent one of the first through holes 201 and one second through hole 202 are preliminarily formed on the circuit board 200 in a manner of drilling or etching or laser cutting, which penetrates the thickness of the circuit board 200. As an optional rather than an essential item, a strip-shaped slit 203 may also be formed in a region where the circuit board 200 is located between the first through hole 201 and the second through hole 202, and the slit 203 also penetrates the thickness of the circuit board 200. As an optional rather than an essential item, the first through hole 201 and the second through hole 202 are symmetrically arranged on the opposite sides of the slit 203, respectively, with the slit 203 as a center symmetry line. As an option, not an essential item, the first through hole 201 and the second through hole 202 are square. A spiral coil 202a is formed around the first through hole 201 on the surface of the circuit board 200, for example, as a main side winding of the pulse transformer PT, and the spiral coil 202a has a plurality of concentric square-shaped conductive rings, the series of concentric squares. The conductive ring surrounds the first through hole 201, and the conductive rings of each turn are disposed on the same plane on the circuit board 200. The center position of the spiral coil 202a substantially coincides with the center position of the first through hole 201. Similarly, another spiral coil 202b is formed around the second through hole 202 on the same surface of the circuit board 200, for example, as a secondary winding of the pulse transformer PT, and the spiral coil 202b has a plurality of concentric square-shaped conductive rings. The series of concentric square conductive rings surround the second through holes 202, and the conductive rings of the rings are disposed on the circuit board 200 at the same a plane. The center position of the spiral coil 202b and the center position of the second through hole 202 substantially coincide. The spiral coil 202a has a head end of the head end as a twist end and a head end having the opposite end end as a different name end. Similarly, the spiral coil 202b has a head end of the head end as a twist end and a head end having the opposite end end as a different name end. The topography or structure of the spiral coils 202a and 202b is various, for example, a spiral shaped back shallow groove is formed around the first through hole 201 on the upper surface or the lower surface of the circuit board 200, including from the inside to the outside. Concentric square trenches, when filled or embedded with conductive materials such as metal copper or the like in these concentric square trenches, a plurality of concentric square-shaped conductive rings can be formed as the spiral coil 202a. Similarly, a spiral shallow groove is formed around the second through hole 202 on the upper surface or the lower surface of the circuit board 200. When the conductive material is filled or embedded in the concentric square grooves, a plurality of concentric lines can be formed. A square shaped conductive ring acts as a helical coil 202b. In various other alternative embodiments, the helical coil 202a or 202b is directly mounted to the upper surface of the circuit board 200, such as by adhesion, deposition, sputtering, plating, etc., including a series of multi-turn concentric square metal coils. For example, they are plated with a metal material simultaneously with other metal wiring or wire diameter TRACE on the circuit board 200. Although the figure is exemplified by a square spiral coil 202a or 202b, in other embodiments not illustrated, the coils of the spiral coil 202a or 202b may be provided in a series of concentric rings or various polygonal shapes or the like. Although FIG. 11A only draws a single-layered helical coil 202a or 202b, in other alternative embodiments, for the helical coil 202a, a plurality of unillustrated helical coils may be disposed inside the circuit board 200. The spiral coils 202a of the top or bottom layer are aligned and aligned in a direction perpendicular to the circuit board 200, so that the spiral coils of different levels are arranged in parallel with each other, and these additional additions inside the circuit board 200 are performed. A spiral coil (not shown) is disposed around the first through hole 201 like the spiral coil 202a. Also for the spiral coil 202b, a plurality of layers of unillustrated helical coils may be disposed inside the circuit board 200 to coincide with the top or bottom spiral coils 202b in a direction perpendicular to the circuit board 200, so that different Hierarchical spiral coil These are disposed in a plane-parallel manner with each other, and at this time, these additional spiral coils (not shown) inside the circuit board 200 are arranged around the second through holes 202 like the spiral coils 202b. In a multi-layer helical coil structure, different levels of helical coils are spaced apart and laminated with an insulating layer belonging to the printed circuit board 200 to be electrically insulated, but any two spiral coils adjacent to each other must satisfy An interconnection condition: the second end (or first end) of the previous helical coil must pass through the interconnection built into the circuit board 200 at the first end (or the second end) of the adjacent next helical coil The line is electrically connected, and these multi-layer spiral coils are connected in series. For example, in a multi-layer helical coil, the first end (or the second end) of the first spiral coil of the top or bottom layer serves as an equivalent end of the same name (or a different name) of the plurality of helical coils, and the bottom layer or The second end (or first end) of one of the last helical coils of the top layer serves as the equivalent different end (or the end of the same name) of the plurality of helical coils.

Referring to Fig. 11A, the pulse transformer PT includes at least a U-shaped (or saddle-shaped) core skeleton 210 and a core skeleton 211 including a strip, and the core skeleton 210 includes side arm portions 210a extending in parallel in the same direction. And the side arm portion 210b further includes a middle portion 210c substantially perpendicular to the side arm portions 210a, 210b, the side arm portions 210a and 210b being respectively coupled to both sides of the middle portion portion 210c, substantially both the side arm portions 210a and 210b and the middle portion 210c is an integrated structure. When one side arm portion 210a of the U-shaped core bobbin 210 is inserted into the first through hole 201, the opposite side arm portion 210b of the U-shaped core bobbin 210 is correspondingly inserted into the second through hole 202, thereby The core bobbin 210 is mounted on the circuit board 200, and in order to form a closed magnetic circuit loop, it is also necessary to combine the core bobbin 211 with the core bobbin 210. In FIG. 11B, the core bobbin 210 is inserted from the front side of the circuit board 200, and the front end faces (or broken sections or cut faces) of the two side arm portions 210a, 210b of the core bobbin 210 are on the circuit board 200. The opposite side is closely attached to one surface of the core bobbin 211 to construct a magnetic circuit. It is worth noting that in order to avoid misunderstandings due to differences in terms or terms, the front end face END FACE of the side arm mentioned in this context is phase. For the side of the side arm SIDE FACE. A slit 204 is reserved between a side surface of one side arm portion 210a of the core bobbin 210 and a sidewall of the first through hole 201. Similarly, a side surface of the other side arm portion 210b of the core bobbin 210 and the second through hole 202 A gap 204 is also reserved between the side walls. In FIG. 11B, in view of the fact that the core bobbin 210 and the core bobbin 211 are polymerized together in a separable form, if the electronic device incorporating the pulse transformer PT is vibrated or dropped, the core skeleton may collapse. Preferably, some insulating glue is placed on the circuit board 200 to bond or hold the two on the circuit board 200 without sloshing. Note that the main function of the printed circuit board 200 herein is to install the above transformer T and the package wafer integrated with the first controller 104 and the package wafer integrated with the second controller 105, except for the PCB board. A corner area on 200 or a relatively rare area of a patch element is reserved for a position for perforation, and a first through hole 201 and a second through hole 202 are prepared to install a pulse transformer PT at the reserved position. . The main switch Q1 and the synchronous switch Q2 may be separately mounted on the PCB circuit board 200, or the main switch Q1 and the first controller 104 may be integrated in one package wafer and then mounted on the PCB circuit board 200, and/or The synchronous switch Q2 and the second controller 105 are integrated in one package wafer and then mounted on the PCB circuit board 200.

Referring to Fig. 12A, another structure of the pulse transformer PT still includes a U-shaped core bobbin 210 and a rectangular parallelepiped or square-shaped core bobbin 211, but has a first alternative to the helical coils 202a and 202b. Wafer 301 and a second wafer 302. The first wafer 301 of the flat square shape is disposed at a relatively near center position with a first central hole 314 penetrating the thickness of the first wafer 301, and the first wafer 301 further has at least two pins 312 and 313, the pin 312 And 313 are used for butt welding with pads on circuit board 200, such as by soldering with surface mount technology. The second wafer 302 of the flat square shape is provided with a second center hole 324 penetrating the thickness of the second wafer 302 near the center position, and the second wafer 302 further has at least two pins 322 and 323, pins 322 and 323 Used to interface with pads on circuit board 200 welding. At this time, adjacent first through holes 201 and second through holes 202 are still formed on the circuit board 200. When the first wafer 301 is mounted on the circuit board 200, its square first center hole 314 should be aligned with the square first through hole 201 of the circuit board 200 when the second wafer 302 is mounted on the circuit board 200. Its second central aperture 324, such as a square, should be aligned with the square second via 202 of the circuit board 200. Since the first center hole 314 and the first through hole 201 overlap, one side arm portion 210a of the U-shaped core bobbin 210 can easily be inserted through the both, and the other side arm portion 210b of the U-shaped core bobbin 210 Correspondingly, the second central hole 324 and the second through hole 202 overlapped at the same time. In Fig. 12B, the core bobbin 211 is combined with the core bobbin 210, and the core bobbin 210 is inserted from the front side of the circuit board 200, and the front end faces of the two side arm portions 210a, 210b of the core bobbin 210 are respectively The other side of the opposite side of the circuit board 200 is closely attached to one surface of the core bobbin 211 to construct a magnetic circuit. Referring to FIG. 12B, a slit 204 is reserved between a side surface of one side arm portion 210a of the core bobbin 210 and a sidewall of each of the first through hole 201 and the first center hole 314, and the other side arm of the core bobbin 210 A slit 204 is also reserved between the side surface of the portion 210b and the sidewalls of each of the second through hole 202 and the second center hole 324.

Referring to FIG. 12C-1, the relationship between the first wafer 301 and the second wafer 302 is modified on the basis of FIG. 12A. In the embodiment of FIG. 12A, the first wafer 301 and the second wafer 302 are each a separate wafer, and they are independent wafers. It is necessary to patch the board 200 separately, but in the possible embodiment of FIG. 12C-1, the first wafer 301 and the second wafer 302 are integrally connected as a whole, and the first wafer 301 and the second wafer 302 can be used. The sync patch is mounted on the circuit board 200. In the top view of FIG. 12C-2, the first wafer 301 and the second wafer 302 are arranged side by side, wherein one corner 311a of the first wafer 301 and one corner 321a of the second wafer 302 are close to each other, and both They are connected together by a connecting portion 331. The other corner portion 311b of the first wafer 301 and the other corner portion 321b of the second wafer 302 are close to each other, and the two are connected together by the connecting portion 332. The connecting portions 331, 332 may be moved to the gap between the first and second wafers in addition to the corners of the wafer. In other positions, as long as the interconnected first wafer 301 and the second wafer 302 are substantially coplanar, they can be mounted on the circuit board 200 simultaneously.

Referring to Figure 12D, a perspective view of the first wafer 301 and the second wafer 302 is shown based on Figure 12A. The first wafer 301 includes a spiral wiring 315 and the second wafer 302 includes a spiral wiring 325, and the topography with respect to the spiral wirings 315 and 325 is separately shown in FIG. 12E. Optionally, in FIG. 12E, one substrate 317 is used to carry a germanium substrate 316, and the substrate 316 may also be used alone. The substrate 317 and the substrate 316 are respectively provided with holes at the center of the substrate 316. A spiral wiring 315 is disposed around the hole in the center position thereof, and the center position of the spiral wiring 315 substantially coincides with the center position of each of the substrate 317 and the substrate 316, because the spiral wiring 315 is a conductor and passes through the substrate 316. The insulating layer of the surface is insulated from the substrate 316. Another substrate 326 disposed side by side with the substrate 316 is carried by a substrate 327 which can be used alone. The substrate 327 and the substrate 326 are each provided with a hole at a central position thereof, and are wound on the upper surface of the substrate 326. The hole in its center position is arranged with a spiral wiring 325 in which the center position of the spiral wiring 325 substantially coincides with the center position of each of the substrate 327 and the substrate 326, since the spiral wiring 325 is a conductor, it is required to pass through the upper surface of the substrate 326. The insulating dielectric layer is insulated from the substrate 326. Here, the substrates 317 and 327 have various options to ensure the implementation of the present invention. In addition to the insulating substrate, a typical metal lead frame or the like may be used instead. Although FIG. 12E only draws a single layer of spiral wiring 315 or 325, in other alternative embodiments, for the substrate 316, a plurality of unillustrated spiral wirings and spirals may be disposed thereon. The wirings 315 are aligned and aligned in a direction perpendicular to the substrate 316 such that the different levels of spiral wiring are disposed in a plane-parallel manner with each other, and at this time, these additional spiral wirings are provided on the substrate 316 (not It is illustrated that it is arranged around the first central hole 314 like the spiral wiring 315. Also for the substrate 326, a plurality of layers of unillustrated spiral wiring may be disposed thereon to coincide with the spiral wiring 325 in a direction perpendicular to the substrate 316, so that different levels of spiral wiring are interposed. Set in parallel with each other At this time, these additional added spiral wirings (not shown) above the substrate 326 are arranged around the second center hole 324 like the spiral wiring 315. In the architecture of a multi-layer spiral wiring, different levels of spiral wiring are spaced apart and an insulating dielectric layer (for example, ruthenium dioxide or the like) is disposed therebetween so as to be electrically insulated from each other, but adjacent to each other. The two spiral wires must satisfy an interconnection condition: the second end (or first end) of the last spiral wire must pass through the first end (or the second end) of the adjacent next spiral wire. The interconnection lines built into the insulating dielectric layer are electrically connected in such a manner that the multilayer spiral wirings are connected in series. For example, in a multi-layer spiral wiring, the first end (or the second end) of the first spiral wiring at the top or bottom layer serves as an equivalent end of the same name (or a different name) of the plurality of spiral wiring series structures, and is located The second end (or first end) of one end of the spiral wiring of the bottom layer or the top layer serves as an equivalent different name end (or the same name end) of the plurality of spiral wiring series structures.

Referring to FIGS. 12D and 12A, the first wafer 301 has a molding body 311, and the second wafer 302 has a molding body 321 . In the first wafer 301, the molding body 311 covers the substrate 316 and the spiral wiring 315 formed on the upper surface thereof, and if the substrate 317 is further provided, it is also covered by the molding body 311. One end of the spiral wiring 315 (like the name end) is connected to the adjacent substrate 317, the lead 312 of the substrate 316 by a wire 318 formed by wire bonding WIREBONDING, and the opposite end of the spiral wiring 315 (such as a different name end) The other leads 318 formed by wire bonding WIRE BONDING are connected to the leads 313 of the adjacent substrate 317 and the substrate 316, and the leads 318 also need to be covered by the molding body 311. The portion of the lead 312 for receiving the lead 318 is covered by the molding body 311, but a portion of the lead 312 extends beyond the molding body 311 for soldering to the pad on the circuit board 200, the same pin. The portion 313 for receiving the lead 318 is covered by the molding body 311, but a portion of the lead 313 extends beyond the molding body 311 for butt welding with the pads on the circuit board 200. Similarly, in the second wafer 302, the molding body 321 covers the substrate 326 and the spiral wiring 325 formed on the upper surface thereof, if the substrate 327 is further provided. It is also covered by a molded body 321 . One end of the spiral wiring 325 (like the name end) is connected to the adjacent substrate 327, the lead 322 of the substrate 326 by a wire 328 formed by wire bonding WIRE BONDING, and the opposite end of the spiral wiring 325 (such as a different name) The other leads 328 formed by wire bonding WIRE BONDING are connected to the adjacent substrate 327, the lead 323 of the substrate 326, and the lead 328 is also covered by the molding body 321 , for example, epoxy resin. Material preparation of the class. The portions of pins 322 and 323 for receiving leads 318 are covered by a molding 311, but each of pins 322 and 323 also has a portion extending beyond the molding 311 for interfacing with pads on circuit board 200. welding.

Referring to FIG. 12D and FIG. 12A, in the first wafer 301, a square first central hole 314 simultaneously penetrates the respective thicknesses of the molding body 311, the substrate 316, and the substrate 317 (if selected), and the first center hole 314 is basically The upper portion is located at the center of each of the molding body 311, the substrate 316, and the substrate 317, and the spiral wiring 315 serves as a main side winding of the pulse transformer PT, and a series of concentric square conductive rings surround the first center hole 314, and is spirally The center position of the wiring 315 and the center position of the first center hole 314 substantially coincide. Correspondingly, in the second wafer 302, a square second central hole 324 simultaneously passes through the respective thicknesses of the molding body 321, the substrate 326, and the substrate 327 (if selected), and the second center hole 324 is substantially located in the plastic package. The center position of each of the body 321, the substrate 326, and the substrate 327, wherein the spiral wiring 325 serves as a secondary winding of the pulse transformer PT, a series of concentric square conductive rings surround the second center hole 324, and the spiral wiring 325 The center position and the center position of the second center hole 324 substantially coincide. For the embodiment of FIG. 12C-1 and FIG. 12C-2, in the molding process MOLDING step, the molding body 311 of the first wafer 301 and the molding body 321 of the second wafer 302 are simultaneously integrally molded, one corner of the molding body 311. The portion 311a and the corner portion 321a of the molding body 321 are adjacent to each other, are close to each other in position, and are bridged by the connecting portion 331 (also a molding material) therebetween, and the other corner of the molding body 311 311b and a corner portion 321b of the molding body 321 are adjacent to each other in position, and by means of it The connection portion 332 (also the molding material) between them bridges the two. In the embodiment of FIG. 12B, a region between the first through hole 201 and the second through hole 202 on the circuit board 200 may be formed as a strip-shaped narrow slit 203 or may not be prepared. In the embodiment of FIGS. 12A to 12E, in the positional relationship, the middle portion 210c of the core bobbin 210 and the core bobbin 211 are both parallel to the plane in which the flat first wafer 301 and the second wafer 302 are located, and also in the circuit. The plates 200 are parallel, but the side arm portions 210a and the side arm portions 210b of the core frame 210 connected at both ends of the middle portion 210c are perpendicular to the plane in which the first wafer 301 and the second wafer 302 are located, and are also associated with the circuit board 200. vertical. When the first wafer 301 and the second wafer 302 are mounted on the circuit board 200, the substrate 316 and the substrate 317, the substrate 326 and the substrate 327, and the flat molded bodies 311, 321 for molding them are both the circuit board 200 Parallel.

Referring to Fig. 13A, another structure of the pulse transformer PT has a first wafer 401 and a second wafer 402. The first wafer 401 includes a U-shaped or saddle-shaped core skeleton 410, and the second wafer 402 includes a U. Shape or saddle-shaped core frame 420. In the first wafer 401, as shown in Fig. 13B, the core bobbin 410 includes parallel extending side arm portions 410a and side arm portions 410c further including a middle portion 410b substantially perpendicular to the side arm portions 410a, 410c, and the middle portion portion 410b is connected Between the side arm portions 410a, 410c. A first coil winding 415 is wound around the middle portion 410b, and one end of the first coil winding 415 (like the name end) is directly connected to the pin 412 by soldering or by various other connection methods, and the first coil winding 415 is opposite to the other. One end (such as a different name end) is directly electrically connected to the pin 413 by soldering or by various other connections, and the pins 412, 413 are adjacent to the core bobbin 410. The molding body 411 encapsulates the core bobbin 410 and the first coil winding 415, and the portion of the pin 412 for receiving the first coil winding 415 is covered by the molding body 411, but the pin 412 has a part. Extending beyond the molding body 411 for butt welding with the pads on the circuit board 200, the same portion of the pin 413 for receiving the first coil winding 415 is covered by the molding body 411, but the pin 413 is also A portion extends beyond the molding body 411 for butt welding with the pads on the circuit board 200. In the second wafer 402, as shown in FIG. 13B, the core skeleton 420 includes parallel The extended side arm portion 420a and side arm portion 420c further include a midsection portion 420b that is substantially perpendicular to the side arm portions 420a, 420c, and the middle portion portion 420b is coupled between the side arm portions 420a, 420c. A second coil winding 425 is wound around the middle portion 420b, and one end of the second coil winding 425 (for example, the same name end) is directly connected to the lead 422 by soldering or by various other connections, and the second coil winding 425 is opposite. The other end (such as a different name end) is directly electrically connected to the pin 423 by soldering or by various other connections, and the pins 422, 423 are adjacent to the core bobbin 420. The molding body 421 molds the core bobbin 420 and the second coil winding 425, and the portion of the pin 422 for receiving the second coil winding 425 is covered by the molding body 421, but the pin 422 has a part. Extending beyond the molding body 411 for docking soldering with the pads on the circuit board 200, the same portion of the pin 423 for receiving the second coil winding 425 is covered by the molding body 421, but the pin 423 is also A portion extends beyond the molding body 421 for butt welding with the pads on the circuit board 200. In the embodiment of FIGS. 13A to 13C, in the positional relationship, the middle portion 410b of the core bobbin 410, the side arm portions 410a, 410c are coplanar and parallel to the plane in which the flat first wafer 401 is located, and the core bobbin 420 is The midsection portion 420b and the side arm portions 420a, 420c are coplanar and parallel to the plane in which the flat second wafer 402 is located. And when the first wafer 401 and the second wafer 402 are mounted side by side on the circuit board 200, the core bobbin 410, the core bobbin 420, and the flat-shaped molding bodies 411, 421 corresponding to those used for molding them, and the circuit board 200 parallel.

Referring to Fig. 13A, for the core bobbin 410 and the core bobbin 420, the front end surface 410a-1 of the side arm portion 410a of the core bobbin 410 is required to be exposed from one side surface 411a of the molding body 411, and the front end surface 410a-1 is actually It is a cut surface or a broken cross section of the side arm portion 410a which is perpendicular to the longitudinal direction of the side arm portion 410a, and the front end surface 410c-1 of the side arm portion 410c of the core bobbin 410 is required to be from one side surface 411a of the molded body 411. The front end surface 410c-1 is actually a cut surface or a broken cross section which belongs to the side arm portion 410c and which is perpendicular to the longitudinal direction of the side arm portion 410c. And the front end surface 420a-1 of the side arm portion 420a of the core bobbin 420 is required to be from one side of the molding body 421 The front end surface 420a-1 is actually a cut surface or a broken cross section of the side arm portion 420a which is perpendicular to the longitudinal direction of the side arm portion 420a, and the side arm portion 420c of the core bobbin 420 is required to be exposed. The front end surface 420c-1 is exposed from one side surface 421a of the molding body 421, and the front end surface 420c-1 is actually a cutting surface or a broken section which belongs to the side arm portion 420c which is perpendicular to the longitudinal direction of the side arm portion 420c. It is also defined that the side surface 411a of the molding body 411 must face the side surface 421a of the molding body 421 when the pulse transformer PT is used, wherein the facing side faces of the regulating side surface 411a and the side surface 421a are disposed so that the front end surface 410a of the side arm portion 410a of the core core 410 is disposed. -1 can be aligned with the front end face 420a-1 of the side arm portion 420a of the core bobbin 420, and also allows the front end face 410c-1 of the side arm portion 410c of the core bobbin 410 to be coupled to the side arm of the core bobbin 420 The front end face 420c-1 of the portion 420c is aligned so as to be along the side arm portion 410a of the core bobbin 410 to the side arm portion 420a of the core bobbin 420, and along the side arm portion 420c from the core bobbin 420 to the magnetic The side arm portion 410c of the core bobbin 410 builds a closed core magnetic circuit between the two core bobbins 410 and 420.

Referring to FIG. 13B, a method of using the pulse transformer PT, when the first wafer 401 and the second wafer 402 are mounted on the circuit board 200, the first wafer 401 and the second wafer 402 are brought close to each other until the first wafer 401 The side surface 411a of the molded body 411 touches one side surface 421a of the molding body 421 of the second wafer 402, and the side surface 411a and the side surface 421a are bonded to each other without a gap. At this time, the front end surface 410a-1 of the side arm portion 410a of the core bobbin 410 and the front end surface 420a-1 of the side arm portion 420a of the core bobbin 420 are fitted together without a gap, and the side arm portion 410c of the core bobbin 410 The front end surface 410c-1 and the front end surface 420c-1 of the side arm portion 420c of the core bobbin 420 are attached to each other without a gap. Corresponding to the positional relationship, the side arm portion 410a of the core bobbin 410 and the side arm portion 420a of the core bobbin 420 are butted, and the side arm portion 410c of the core bobbin 410 and the side arm portion 420c of the core bobbin 420 are butted, thereby The core bobbin 410 and the core bobbin 420 may be spliced to form a desired toroidal core structure.

Referring to Fig. 13C, this embodiment is slightly different from Fig. 13B. Fig. 13B restricts that the side surface 411a of the molding body 411 completely and closely fits the side surface 421a of the molding body 421, but in Fig. 13C When the first wafer 401 and the second wafer 402 are mounted side by side on the circuit board 200, the first wafer 401 and the second wafer 402 are brought close to each other, but the side surface 411a of the molding body 411 and the side surface 421a of the molding body 421 are A gap 430 is left between, and it is still required that the side surface 411a of the molding body 411 of the first wafer 401 touches the side surface 421a of the molding body 421 of the second wafer 402 to face each other, and the side arm portion 410a of the core skeleton 410 The front end surface 410a-1 and the front end surface 420a-1 of the side arm portion 420a of the core bobbin 420 are face-to-face aligned with each other, and the front end surface 410c-1 of the side arm portion 410c of the core bobbin 410 and the side of the core bobbin 420 The front end faces 420c-1 of the arm portions 420c are aligned face to face with each other. Correspondingly, in the positional relationship, the side arm portion 410a of the core bobbin 410 and the side arm portion 420a of the core bobbin 420 are butted together with each other in a gap manner, and similarly, the side arm portion of the core bobbin 410 is similar. The 410c and the side arm portions 420c of the core bobbin 420 are butted to each other with a gap therebetween, so that the core bobbin 410 and the core bobbin 420 can be spliced to form a desired toroidal core structure, except that the side of the core bobbin 410 The arm portion 410a and the side arm portion 420a of the core bobbin 420 are broken and an air gap is formed at the disconnected position, and the side arm portion 410c of the core bobbin 410 and the side arm portion 420c of the core bobbin 420 are disconnected and An air gap is formed at the disconnected position, and an air gap between the front end surface 410a-1 and the front end surface 420a-1 and an air gap between the front end surface 410c-1 and the front end surface 420c-1 are used to prevent magnetic saturation. When an air gap is left in the magnetic core of the pulse transformer PT, since the magnetic permeability of the air is only a few thousandth of the magnetic permeability of the iron core, the magnetomotive force almost falls on the air gap, so that the air gap is left. The average magnetic permeability of the magnetic core will be greatly reduced, not only the residual magnetic flux density will be reduced, but also the maximum magnetic flux density can reach the saturation magnetic flux density, so that the magnetic flux increment is increased, and the transformer core is no longer prone to magnetic saturation. In this embodiment, an optional insulating material 450 is also filled in the gap 430 remaining between the side surface 411a of the molding body 411 and the side surface 421a of the molding body 421. The insulating material 450 can not only electrically isolate, but on the other hand It is also possible to effectively enhance the bonding strength of the first wafer 401 and the second wafer 402 on the circuit board 200.

The exemplary embodiments of the specific structures of the specific embodiments have been described above by way of illustration and the accompanying drawings. Various changes and modifications will no doubt become apparent to those skilled in the <RTIgt; Accordingly, the appended claims are to cover all such modifications and modifications The scope and content of any and all equivalents are intended to be within the scope and spirit of the invention.

101‧‧‧Rectifier

103‧‧‧ snubber circuit

104‧‧‧First controller

105‧‧‧Second controller

106‧‧‧Coupling components

12,14‧‧‧ Busbar

18‧‧‧load

T‧‧‧Transformer

L P ‧‧‧main side winding

L S ‧‧‧ secondary winding

N 10 ‧‧‧Input node

N 20 ‧‧‧Output node

V IN ‧‧‧ input voltage

GND‧‧‧ ground terminal

Q1‧‧‧Main switch

Q2‧‧‧Synchronous switch

C OUT ‧‧‧ output capacitor

L AUX ‧‧‧Auxiliary winding

C AUX ‧‧‧ capacitor

D 11 , D 12 , D 13 , D 14 , D 21, D 22 ‧‧‧ diode

V AC ‧‧‧Sinusoidal AC voltage

L 1 ‧‧‧Inductance

C 11 , C 12 ‧‧‧ capacitor

R 21 ‧‧‧ current limiting resistor

RX1, RX2‧‧‧ receiving interface

HV‧‧‧drain

V CC ‧‧‧ voltage

D AUX ‧‧‧ diode

S 1 ‧‧‧first pulse signal

S 2 ‧‧‧second pulse signal

R S ‧‧‧resistance resistor

Capacitance C Y ‧‧‧

TX1, TX2‧‧‧ send interface

ST‧‧‧Starting voltage

V FB ‧‧‧ feedback voltage

V CS ‧‧‧Sensor voltage

R D1 , R D2 ‧‧‧resistance

V O ‧‧‧Output voltage

I O ‧‧‧Load current

R C ‧‧‧Sensor resistance

VSS‧‧‧reference ground potential

Claims (23)

  1. A pulse transformer comprising a U-shaped first core bobbin with a set of side arms extending in parallel, and a strip-shaped second core bobbin disposed on a printed circuit board for mounting a pulse transformer a first and second through holes extending through the thickness of the printed circuit board, and inserting a set of side arm portions of the first core bobbin into the first through hole and the second through hole respectively from the first side of the printed circuit board And the front end faces of the set of side arm portions are directly pressed against one surface of the second core bobbin on the second side of the printed circuit board.
  2. The pulse transformer of claim 1, wherein the first side surface or the second side surface of the printed circuit board is provided with planarized first and second spiral coils, in the first spiral coil A series of concentric coils are disposed around the first through hole, and a series of concentric coils in the second helical coil are disposed around the second through hole.
  3. The pulse transformer of claim 1, wherein a region between the first and second through holes on the printed circuit board is provided with a strip-shaped slit penetrating the thickness of the printed circuit board, first, The two through holes are symmetrically distributed on both sides of the slit with the slit as a central symmetry line.
  4. The pulse transformer of claim 2, wherein the first and second helical coils are in the form of a square or circular spiral coil.
  5. The pulse transformer of claim 1, further comprising an insulating paste coated on the printed circuit board for adhering the first and second core bobbins to the printed circuit board.
  6. The pulse transformer of claim 2, wherein the first side surface or the second side surface of the plurality of first spiral coils and the printed circuit board are disposed inside the printed circuit board The first spiral coils of the face are aligned and coincident, and the plurality of first spiral coils disposed inside the printed circuit board are disposed around the first through hole; one end of any one of the upper first spiral coils and adjacent one next One ends of the first spiral coil are interconnected, whereby all of the first spiral coils are connected in series, and one end of the first first spiral coil among the plurality of first spiral coils connected in series is used as an equivalent end of the same name or One of the equivalent synonyms, one end of a first spiral coil at the end serves as the other of the equivalent end of the same name or the equivalent name.
  7. The pulse transformer of claim 2, wherein the plurality of second spiral coils are disposed inside the printed circuit board and aligned with the second spiral coil of the first side surface or the second side surface of the printed circuit board. Coincidentally, a plurality of second spiral coils disposed inside the printed circuit board are disposed around the second through hole; and one end of any one of the upper second spiral coils is interconnected with one end of the adjacent second spiral coil Thereby, all the second spiral coils are connected in series, and one end of the first second spiral coil among the plurality of second spiral coils connected in series is used as one of the equivalent end of the same name or the equivalent name end One end of a second spiral coil at the end serves as the other of the equivalent end of the same name or the equivalent name.
  8. The pulse transformer of claim 1, wherein the printed circuit board is further provided with a power transformer of a power stage, the primary side winding of the main transformer receives the input voltage and provides an output voltage for the load on the secondary side winding, and The primary side winding of the main transformer is connected in series with a main switch; a wafer with the first controller is mounted on the printed circuit board for generating a first pulse signal to drive the main switch to switch between on and off; A wafer with a second controller is mounted on the printed circuit board and a characterization output The voltage magnitude and/or the detected voltage indicative of the magnitude of the load current is compared with a first reference voltage, and the logic state of a control signal generated by the comparison is determined by the comparison result; wherein the pulse transformer transmits the logic state of the control signal to the first A controller causes the first controller to determine a logic state of the first pulse signal according to a logic state of the control signal, thereby determining whether the main switch is turned on or off.
  9. A pulse transformer comprising a U-shaped first core bobbin with a set of side arms extending in parallel, and a strip-shaped second core bobbin disposed on a printed circuit board for mounting a pulse transformer a first and second through holes extending through the thickness of the printed circuit board; and a first wafer having a first center hole and a second wafer having a second center hole, the first and second wafers being mounted on On the printed circuit board, the first central hole and the first through hole are coincidently aligned and the second central hole and the second through hole are aligned and coincident; a set of side arms of the first core bobbin is from the first side of the printed circuit board One of the portions is simultaneously inserted into the first center hole, the first through hole and the other is simultaneously inserted into the second center hole and the second through hole, and the front end faces of the set of side arm portions are second in the printed circuit board The sides are each directly pressed against one surface of the second core bobbin.
  10. The pulse transformer of claim 9, wherein the first wafer comprises: a first substrate, and a first spiral wiring is disposed on one surface of the first substrate: disposed near the first substrate Two pins, two ends of the first spiral wiring are respectively connected to the two pins through leads; a first plastic body covering the first substrate, the first spiral cloth, and the lead wires a portion of the foot for receiving the lead is covered by the first molding, but another portion of the lead extends beyond the first molding for soldering to the pad on the printed circuit board; the first central opening extends through the first plastic And the first substrate, and a series of concentric spiral wirings in the first spiral wiring are arranged around the first central hole.
  11. The pulse transformer according to claim 10, wherein the first substrate is provided with a plurality of first spiral wires and vertically aligned with each other, and the first spiral wires adjacent to each other are disposed between An insulating dielectric layer, a series of concentric spiral wirings in any one of the first spiral wirings are arranged around the first central hole; any one of the one of the upper first spiral wirings and one end adjacent to the next first spiral wiring Interconnecting, whereby all of the first spiral wires are connected in series, and one end of the first first spiral wire in the plurality of first spiral wires connected in series is used as an equivalent end of the same name or equivalent name One of the ends of a first spiral wiring at the end serves as the other of the equivalent end of the same name or the equivalent name.
  12. The pulse transformer of claim 9, wherein the second wafer comprises: a second substrate, and a second spiral wiring is disposed on one surface of the second substrate: disposed adjacent to the second substrate Two pins, two ends of the second spiral wiring are respectively connected to the two pins through leads; a second plastic body covering the second substrate, the second spiral cloth, and the lead wires A portion of the foot for receiving the lead is covered by the second molding, but another portion of the lead extends beyond the second molding for soldering to the pad on the printed circuit board; the second central opening extends through the second plastic Body and second substrate, and in the second spiral wiring A series of concentric spiral wires are arranged around the second central hole.
  13. The pulse transformer according to claim 12, wherein the second substrate is provided with a plurality of second spiral wires and is vertically aligned with each other, and the second spiral wires adjacent to each other are disposed between a plurality of concentric spiral wires in any one of the second spiral wires are arranged around the second center hole; any one of the one of the upper second spiral wires and one end of the adjacent second spiral wire Interconnecting, whereby all of the second spiral wires are connected in series, and one end of the first second spiral wire in the plurality of second spiral wires connected in series is used as an equivalent end of the same name or equivalent name One of the ends of a second spiral wiring at the end serves as the other of the equivalent end of the same name or the equivalent name.
  14. The pulse transformer of claim 9, wherein the insulating glue coated on the printed circuit board is used to adhere the first and second core skeletons to the printed circuit board.
  15. The pulse transformer of claim 9, wherein the first wafer and the second wafer are connected to each other by one or more connecting portions to make them a coplanar integrated structure, so that the first wafer and the first wafer The two wafers are simultaneously mounted to the printed circuit board.
  16. The pulse transformer of claim 9, wherein the printed circuit board is further provided with a power transformer of a power stage, the primary side winding of the main transformer receives the input voltage and provides an output voltage for the load on the secondary side winding, and The primary side winding of the main transformer is connected in series with a main switch; a wafer with the first controller is mounted on the printed circuit board for generating a first pulse signal to drive the main switch to switch between on and off; A wafer with a second controller is mounted on the printed circuit board and compares a detected voltage indicative of the magnitude of the output voltage and/or the magnitude of the load current with a first reference voltage, the result of which is determined by the comparison a logic state of the control signal; wherein the pulse transformer transmits the logic state of the control signal to the first controller, so that the first controller determines the logic state of the first pulse signal according to the logic state of the control signal, thereby determining the main switch Turn on or off.
  17. A pulse transformer comprising first and second wafers, the first wafer having a U-shaped first core skeleton and a first molding body having a first magnetic core skeleton molded, the second wafer having a U-shaped first a second core skeleton and a second molding body having a second core skeleton; the first and second core skeletons each have a set of side arm portions extending in parallel, and a set of sides of the first core bobbin The front end faces of the arms are exposed from one side edge surface of the first molding body, and the front end faces of the set of side arm portions of the second core frame are exposed from one side edge surface of the second molding body, so that The side edge surface of the side arm portion of the first molding body exposing the first core bobbin faces the side edge surface of the side arm portion of the second molding body exposing the second core bobbin, and any of the first core bobbin is disposed The front end face of one side arm portion is aligned with the front end face of one of the second core bobbins.
  18. The pulse transformer of claim 17, wherein a middle portion is connected between a set of side arm portions of the first core bobbin, and the first coil has a first coil winding wound around the first core bobbin On the middle portion, and the two ends of the first coil winding are respectively connected to the two pins of the first wafer, and the pin is used to receive a part of the first coil winding and is covered by the first plastic body, but Another part of the foot extends beyond the first plastic body for printing The pads on the board are butt welded.
  19. The pulse transformer of claim 17, wherein a middle portion of the second core bobbin has a middle portion connected thereto, and the second wafer has a second coil winding wound around the second core bobbin On the middle portion, and the two ends of the second coil winding are respectively connected to the two pins of the second wafer, and the pin is used to receive a part of the second coil winding and is covered by the second plastic body, but Another portion of the foot extends beyond the second molded body for butt welding with the pads on the printed circuit board.
  20. The pulse transformer of claim 17, wherein when the first and second wafers are mounted side by side on the printed circuit board, the first plastic body and the second plastic body are spaced apart from each other, and the side of the first core frame is The front end surface of the arm portion and the front end surface of the side arm portion in the second core bobbin are aligned one-to-one in a spaced apart manner.
  21. The pulse transformer of claim 17, wherein when the first and second wafers are mounted side by side on the printed circuit board, the first plastic body and the second plastic body are closely attached to each other to make the first plastic body The side edge surface of the side arm portion exposing the first core bobbin and the side edge surface of the side arm portion exposing the second core bobbin of the second molding body are seamlessly fitted, and the side arm portion of the first core bobbin The front end faces and the front end faces of the side arm portions in the second core bobbin are aligned one-to-one in a manner of being low-pressure mutually.
  22. The pulse transformer of claim 20, wherein the first plastic body and the second plastic body are spaced apart and filled with an insulating material in a gap between the first core body and a front end surface of the side arm portion of the first core frame The front end faces of the side arm portions in the second core bobbin are aligned one-to-one with the insulating material spaced apart.
  23. The pulse transformer of claim 17, wherein the printed circuit A power stage main transformer is also mounted on the board, the primary side winding of the main transformer receives the input voltage and provides an output voltage for the load on the secondary side winding, and the primary side winding of the main transformer is connected in series with a main switch; The controller's wafer is mounted on a printed circuit board for generating a first pulse signal to drive the main switch to switch between on and off; a wafer with a second controller is mounted on the printed circuit board for a characterization The output voltage magnitude and/or the detected voltage indicative of the magnitude of the load current is compared with a first reference voltage, and the logic state of a control signal generated by the comparison result is determined by the comparison result; wherein the pulse transformer transmits the logic state of the control signal to The first controller causes the first controller to determine the logic state of the first pulse signal according to the logic state of the control signal, thereby determining whether the main switch is turned on or off.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI617113B (en) * 2016-02-05 2018-03-01 廣東歐珀移動通信有限公司 System and method for charging terminal and power adapter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI617113B (en) * 2016-02-05 2018-03-01 廣東歐珀移動通信有限公司 System and method for charging terminal and power adapter

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