CN106531817A - Semiconductor element and manufacturing method thereof - Google Patents
Semiconductor element and manufacturing method thereof Download PDFInfo
- Publication number
- CN106531817A CN106531817A CN201510566785.3A CN201510566785A CN106531817A CN 106531817 A CN106531817 A CN 106531817A CN 201510566785 A CN201510566785 A CN 201510566785A CN 106531817 A CN106531817 A CN 106531817A
- Authority
- CN
- China
- Prior art keywords
- layer
- type doping
- semiconductor
- base material
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 197
- 238000004519 manufacturing process Methods 0.000 title abstract description 5
- 229910021645 metal ion Inorganic materials 0.000 claims abstract description 35
- 239000000463 material Substances 0.000 claims description 67
- 238000002360 preparation method Methods 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 21
- 238000005240 physical vapour deposition Methods 0.000 claims description 18
- 238000005516 engineering process Methods 0.000 claims description 17
- 238000009792 diffusion process Methods 0.000 claims description 12
- 238000009413 insulation Methods 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 6
- 238000007733 ion plating Methods 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 230000003746 surface roughness Effects 0.000 claims description 4
- -1 Si oxide Inorganic materials 0.000 claims description 3
- 238000010521 absorption reaction Methods 0.000 claims description 3
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 3
- 229910003437 indium oxide Inorganic materials 0.000 claims description 3
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 239000011787 zinc oxide Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims 1
- 238000009713 electroplating Methods 0.000 abstract description 6
- 239000002585 base Substances 0.000 description 43
- 239000004020 conductor Substances 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000012797 qualification Methods 0.000 description 4
- 230000005611 electricity Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000009466 transformation Effects 0.000 description 3
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 2
- 229910001431 copper ion Inorganic materials 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000003513 alkali Substances 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008033 biological extinction Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000002674 ointment Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000009498 subcoating Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Life Sciences & Earth Sciences (AREA)
- Sustainable Development (AREA)
- Sustainable Energy (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a manufacturing method of a semiconductor element. The manufacturing method of the semiconductor element comprises the following steps: providing a semiconductor stacking layer and an electroplating electrode in a solution; applying a voltage difference for the opposite side of the semiconductor stacking layer and the electroplating electrode; and providing a light beam to the semiconductor stacking layer, so that a first electrode is formed on an incident surface of the semiconductor stacking layer, wherein the voltage difference enables the electroplating electrode to provide at least one metal ion into the solution and form a metal ion solution, the incident surface of the semiconductor stacking layer is opposite to the opposite side of the semiconductor stacking layer, and the semiconductor stacking layer is suitable for absorbing the light beam and generating an electron to the incident surface, so that the metal ion in the metal ion solution and the electron form the first electrode on the incident surface of the semiconductor stacking layer. Based on the manufacturing method, the semiconductor element is also provided.
Description
Technical field
The invention relates to a kind of electronic component and preparation method thereof, and in particular to one kind half
Conductor element and preparation method thereof.
Background technology
In existing solar battery technology, by heteroj unction technologies (Heterojunction
Technology, HJT) formed with hetero-junctions (Heterojunction with Intrinsic
Thin-Layer, HIT) heterojunction solar battery mainly by with it is different can bands semiconductor
Material is combined into.Heterojunction solar battery not only has higher photoelectric transformation efficiency and preferably
Temperature characterisitic, by it is different can the hetero-junctions of combination of bands can also reduce in solar cell freely
The loss of carrier.Therefore, heterojunction solar battery is had become in solar battery technology now
One of technology of main development.
In existing heterojunction solar battery, N-type silicon wafer (Silicon) heterojunction solar electricity
Pond has front emitter-base bandgap grading (front emitter) structure, that is, N-type silicon Jing heterojunction solar batteries exist
Receiving electronics (electron) produced after light beam via irradiation face can be toward solar cell relative to photograph
The non-irradiation face movement in light face.When above-mentioned heterojunction solar battery will make electricity using electroplating technology
Pole needs an additional contact electrode when irradiation face, is forced by contacting electrode and gives electronics to different
The irradiation face of matter joint solar cell, use in an electroplating solution with metal ion to complete reduction anti-
Should.However, above-mentioned contact electrode needs electrically to connect with heterojunction solar battery in the way of clamping
Connect, the chip on heterojunction solar battery is easily damaged during clamping, breakage, and then is dropped
Low qualification rate.On the other hand, contact electrode to be formed in the irradiation face of heterojunction solar battery
The region for having strong electric near even Electric Field Distribution, therefore contact electrode can be initially formed electroplated electrode,
Remaining area forms weaker electric field also with the coating of electroplated electrode, and then forms uneven electricity
Pole.In order to solve the above problems, existing method for manufacturing solar battery first can be existed with the mode of vacuum
On semiconductor chip, the metal level in one whole face of growth finally uses alkali again as Seed Layer (seed layer)
Property solution removes metal seed layer to expose transmission region.However, extra Seed Layer is except increasing
The complexity of technique, while can also make overall acceptability rate decline and cost is significantly increased.
The content of the invention
The present invention provides a kind of preparation method of semiconductor element, and which can efficiently form good
Electrode.
The present invention provides a kind of semiconductor element, and which has uniform and good electrode.
The preparation method of the semiconductor element of embodiments of the invention includes providing semiconductor stack layer
And one opposite face of the electroplated electrode in a solution, to semiconductor stack layer and electroplated electrode apply one
Voltage difference and one light beam of offer make first electrode be formed at semiconductor stack layer to semiconductor stack layer
Incidence surface on, voltage official post electroplated electrode provide an at least metal ion is into solution and forms a gold medal
Category solion, the incidence surface of semiconductor stack layer are relative with the opposite face of semiconductor stack layer, and half
Conductor stack is suitable to absorb above-mentioned light beam and produces an electronics to incidence surface, in making metal ion solution
Metal ion with electronically form first electrode on the incidence surface of semiconductor stack layer.
In one embodiment of this invention, above-mentioned offer semiconductor stack layer and electroplated electrode are in solution
In step include providing one first type doping base material, form one first type doping semiconductor layer and one the
Two type doping semiconductor layers and one first conductive layer of formation and one second conductive layer.First type doping half
Conductor layer is located on the front of the first type doping base material, and Second-Type doping semiconductor layer is mixed positioned at the first type
Miscellaneous base material relative on positive reverse side.First conductive layer be located at the first type doping semiconductor layer and on
The incidence surface stated is located at the first conductive layer.Second conductive layer is positioned at Second-Type doping semiconductor layer and above-mentioned
Opposite face be located at the second conductive layer.
In one embodiment of this invention, above-mentioned formation the first type doping semiconductor layer and Second-Type doping
Also include forming one first intrinsic layer before the step of semiconductor layer and form one second intrinsic layer.First
Intrinsic layer is located on the front of the first type doping base material, and the second intrinsic layer is located at the first type doping base material
On reverse side.A hetero-junctions, and the second intrinsic layer are formed between first intrinsic layer and the first type doping base material
And first type doping base material between form another hetero-junctions.
In one embodiment of this invention, the first conductive layer of above-mentioned formation is led in the first type doped semiconductor
Electric layer and formed the second conductive layer the step of Second-Type doping semiconductor layer include forming multiple anti-reflective
Micro-structural is penetrated in the first conductive layer and the second conductive layer.
The semiconductor element of embodiments of the invention includes one first type doping base material, the doping of one first type
Semiconductor layer, a Second-Type doping semiconductor layer, one first conductive layer, one second conductive layer, one
One electrode and a second electrode.First type doping semiconductor layer is just being configured at the first type doping base material
Face, Second-Type doping semiconductor layer be configured at the first type doping base material relative to positive reverse side.The
One conductive layer is configured on the first type doping semiconductor layer, and the first type semiconductor layer is conductive positioned at first
Between layer and the first type doping base material.Second conductive layer is configured on Second-Type doping semiconductor layer, and
Second type semiconductor layer is located between the second conductive layer and the first type doping base material.First electrode is configured at
The one of first conductive layer is back to positive incidence surface, and first electrode expose portion incidence surface.Second is electric
Pole be configured at the one of the second conductive layer back to reverse side opposite face, and second electrode expose portion opposite face.
In one embodiment of this invention, the first above-mentioned type doping semiconductor layer is partly led for n-type doping
Body layer, the first type doping base material are n-type doping base material, and Second-Type doping semiconductor layer is that p-type is adulterated
Semiconductor layer.
In one embodiment of this invention, above-mentioned semiconductor element is also configured on incidence surface including one
Insulation screen, and insulation screen exposed portion is divided into surface.
In one embodiment of this invention, the forming method of the first above-mentioned intrinsic layer and the second intrinsic layer
Including plasma auxiliary chemical vapor deposition, physical vapour deposition (PVD), aumospheric pressure cvd, from
Sub- coating technique and thermal diffusion furnace technology.
In one embodiment of this invention, the first above-mentioned type doping semiconductor layer and Second-Type doping half
The forming method of conductor layer includes plasma auxiliary chemical vapor deposition (Plasma Enhanced
Chemical Vapor Deposition, PECVD), physical vapour deposition (PVD) (Physical Vapor
Deposition, PVD), aumospheric pressure cvd (Atmospheric Pressure Chemical
Vapor Deposition, APCVD) and thermal diffusion furnace technology (Thermal diffusion furnace).
In one embodiment of this invention, the forming method of the first above-mentioned conductive layer and the second conductive layer
Including plasma auxiliary chemical vapor deposition (Plasma Enhanced Chemical Vapor
Deposition, PECVD), physical vapour deposition (PVD) (Physical Vapor Deposition, PVD), often
Pressure chemical vapor deposition (Atmospheric Pressure Chemical Vapor Deposition,
APCVD), ion-plating technique (Reactive Plasma Deposition, RPD) and thermal diffusion furnace
Technology (Thermal diffusion furnace).
In one embodiment of this invention, the first above-mentioned conductive layer and the second conductive layer have multiple anti-
Reflection micro-structure.
In one embodiment of this invention, the surface roughness Ra of above-mentioned incidence surface and opposite face is little
In 5 nanometers.
In one embodiment of this invention, the wavelength of above-mentioned light beam is different from the suction of metal ion solution
Receive the wavelength of wave band.
In one embodiment of this invention, the first above-mentioned type doping semiconductor layer and Second-Type doping half
The material of conductor layer includes monocrystalline silicon, polysilicon, non-crystalline silicon, carborundum, Si oxide, silicon nitridation
Thing or its combination.
In one embodiment of this invention, the material of the first above-mentioned conductive layer and the second conductive layer includes
Indium oxide, zinc oxide, metal oxide, silicon nitride or its combination.
In one embodiment of this invention, above-mentioned semiconductor element is also configured at the first type including one and mixes
The first intrinsic layer between miscellaneous base material and the first type doping semiconductor layer and it is configured at the doping of the first type
The second intrinsic layer between base material and Second-Type doping semiconductor layer.First intrinsic layer and the doping of the first type
A hetero-junctions is formed between base material, forms another heterogeneous between the second intrinsic layer and the first type doping base material
Knot.
Based on above-mentioned, the preparation method of the semiconductor element of embodiments of the invention is partly being led by light beam
The electronics produced in body stack layer to be formed the electrode of semiconductor element in a metal ion solution, because
Can have uniform and good electrode, and the formation of electrode on the surface of this semiconductor element for being formed
During be not required to additionally paste, grip electrode on the surface of semiconductor stack layer, therefore can be lifted partly
The making qualification rate of conductor element.The framework of the semiconductor element of embodiments of the invention in process may be used
Light beam is allowed sufficiently into incidence surface producing electronics, therefore can form more uniform electrode and carry
For good electric connection quality.Consequently, it is possible to the semiconductor element of embodiments of the invention just can be with
More luminous energy are converted to into electric energy.
It is that the features described above and advantage of the present invention can be become apparent, special embodiment below, and match somebody with somebody
Accompanying drawing appended by closing is described in detail below.
Description of the drawings
Fig. 1 is according to the schematic diagram for making semiconductor element in the first embodiment of the present invention.
Fig. 2 to Fig. 5 is according to the schematic diagram for making semiconductor element in the second embodiment of the present invention.
【Symbol description】
L、L1、L2：Light beam
V：Voltage difference
100、100A：Semiconductor element
110、110A：Semiconductor stack layer
111：Electronics
112、112A：First type doping semiconductor layer
113、113A：Incidence surface
114、114A：First type doping base material
115、115A：Opposite face
116、116A：Second-Type doping semiconductor layer
117、117A：Insulation shielding
118、118A：First electrode
119、119A：Second electrode
121、121A：First conductive layer
123、123A：Front
125、125A：Reverse side
126、126A：Second conductive layer
131A、132A：Intrinsic layer
133A、134A：Hetero-junctions
200：Electroplated electrode
201：Metal ion
300：Solution
400：Metal ion solution
Specific embodiment
Fig. 1 is according to the schematic diagram for making semiconductor element in the first embodiment of the present invention.Refer to
Fig. 1, in the first embodiment of the present invention, the preparation method of semiconductor element 100 includes offer one
Semiconductor stack layer 110 and an electroplated electrode 200 are in a solution 300 and to semiconductor stack layer
110 apply voltage difference V with electroplated electrode 200.Voltage difference V makes electroplated electrode 200 provide at least
One metal ion 201 is in solution 300 and forms a metal ion solution 400.Namely this enforcement
The semiconductor element preparation method of example is by providing voltage difference V to electroplated electrode 200 and semiconductor stack
Layer 110 is making electroplated electrode 200 dissociate metal ion 201 into solution 300, and then makes solution
300 form the metal ion solution 400 for being mixed with metal ion 201.In the present embodiment, voltage difference V
Battery can be passed through or external power supply is provided, the invention is not restricted to this.
100 preparation method of semiconductor element of the present embodiment is the opposite face to semiconductor stack layer 110
115 and 200 applied voltage of electroplated electrode difference V, a light beam L is then provided to semiconductor stack layer 110.
Semiconductor stack layer 110 is suitable to absorb light beam L and produce electronics 111, and semiconductor stack layer 110
Incidence surface 113 relative to opposite face 115, therefore the electronics 111 produced by above-mentioned absorption light beam L
Incidence surface 113 be can reach, and then metal ion 201 and electronics 111 in metal ion solution 400 made
Formation first electrode 118 is on incidence surface 113.That is, the first electrode 118 in the present embodiment
It is that the metal ion 201 gone out by produced by voltage difference V is produced in semiconductor stack layer 110 with light beam L
Electronics 111 formed, and then produce semiconductor element 100.Due to being formed in the present embodiment
The electronics 111 of first electrode 118 be by produced by semiconductor stack layer 110 absorbs light beam L, via
The electronics 111 caused by light beam L can equably arrive at incidence surface 113, therefore first electrode 118
Can be formed uniformly on incidence surface 113.On the other hand, because the semiconductor element of the present embodiment
Extra conductive electrode is not had in preparation method and touches incidence surface 113, therefore can be greatly reduced
Incidence surface 113 damage because touching, clamping or breakage probability, and then lifted make semiconductor element
100 qualification rate.In other words, the preparation method of the semiconductor element 100 of the present embodiment be via
It is light-initiated to electroplate to form uniform first electrode 118 in incidence surface 113.
Specifically, in the present embodiment, there is provided semiconductor stack layer 110 and electroplated electrode 200
Step in solution 300 includes providing one first type doping base material 114, forms the doping of one first type
Semiconductor layer 112 and a Second-Type doping semiconductor layer 116 and formed one first conductive layer 121 and
One second conductive layer 126.First type doping semiconductor layer 112 is located at the first type doping base material 114
On front 123, Second-Type doping semiconductor layer 116 be located at the first type adulterate base material 114 relative to
On the reverse side 125 in front 123.First conductive layer 121 be located at the first type doping semiconductor layer 112 and
Incidence surface 113 is located at the first conductive layer 121.Second conductive layer 126 is located at Second-Type doped semiconductor
Layer 116 and above-mentioned opposite face 115 be located at the second conductive layer 126.In the present embodiment, the first type
Doping base material 114 is, for example, n-type doping base material, and the first type doping semiconductor layer 112 is, for example, N
Type doping semiconductor layer, Second-Type doping semiconductor layer 116 are, for example, p-type doping semiconductor layer, and
Semiconductor stack layer 110 for example has a kind of back reflection pole (rear emitter) structure.Work as the present embodiment
Semiconductor stack layer 110 can produce in receiving light beam L electronics 111 forward (namely toward enter light
113) face is projected, and then metal ion 201 is gone back in incidence surface 113 in making metal ion solution 400
Original simultaneously forms first electrode 118.
In the present embodiment, due to there is voltage difference V to provide the opposite face in semiconductor stack layer 110
115, therefore can move toward incidence surface 113 after electronics 111 is produced in semiconductor stack layer 110.In detail
For thin, in the present embodiment, semiconductor stack layer 110 has and is formed at the second of opposite face 115
Electrode 119, and second electrode 119 is electrically connected to electroplated electrode 200, and voltage difference V is via
Two electrode 119 provides opposite face 115.In the present embodiment, there is provided voltage difference V is to second electrode
119 method is provided e.g. by brush contact with second electrode 119, but the present invention is not limited
In this.On the other hand, in other embodiments of the invention, the opposite face of semiconductor stack layer 110
115 can also directly be electrically connected to electroplated electrode 200, the invention is not restricted to this.
On the other hand, in the first embodiment of the present invention, semiconductor stack layer 110 also includes insulation
Shielding 117, insulation shielding 117 is configured on incidence surface 113 and expose portion incidence surface 113.Half
Conductor stack 110 can be limited metal ion 201 and can be connect by the position of insulation shielding 117
The region of tactile incidence surface 113, that is, insulation shielding 117 can define 118 shapes of first electrode
Into position.
In the present embodiment, the wavelength of light beam L is different from the absorption bands of metal ion solution 400
Wavelength.Specifically, in the present embodiment, when the metal ion 201 dissociated by electroplated electrode 200
For example, copper ion when, metal ion solution that copper ion 201 is formed 400 is not because absorb blueness
Light beam, therefore light beam L can include that e.g. wavelength is 460 nanometers of blue light beam L, and then make
Light beam L efficient can be transferred to semiconductor stack layer 110.That is, the enforcement of the present invention
The selection of the light beam L of example can be determined according to the extinction characteristic of metal ion solution 400, and then is made
Light beam L can efficiently be delivered to semiconductor stack layer 110.
In the first embodiment of the present invention, the first type doping semiconductor layer 112 and Second-Type doping half
The forming method of conductor layer 116 include plasma auxiliary chemical vapor deposition, physical vapour deposition (PVD),
Aumospheric pressure cvd and thermal diffusion furnace technology (Thermal diffusion furnace), but the present invention
Not limited to this.The forming method of the first conductive layer 121 and the second conductive layer 126 includes that plasma is auxiliary
Help chemical vapor deposition, physical vapour deposition (PVD), aumospheric pressure cvd, ion-plating technique and heat
Diffusion furnace technology, but the invention is not restricted to this.
In the present embodiment, semiconductor element 100 includes that the first type doping base material 114, the first type are mixed
Miscellaneous semiconductor layer 112, Second-Type doping semiconductor layer 116, the first conductive layer 121, the second conductive layer
126th, first electrode 118 and second electrode 119.First type doping semiconductor layer 112 is configured at
The front 123 of one type doping base material 114, Second-Type doping semiconductor layer 116 are configured at the first type and mix
The reverse side 125 relative to front 123 of miscellaneous base material 114.First conductive layer 121 is configured at the first type
On doping semiconductor layer 112, and the first type doping semiconductor layer 112 be located at the first conductive layer 121 and
Between first type doping base material 114.Second conductive layer 126 is configured at Second-Type doping semiconductor layer 116
On, and the second type semiconductor layer 116 be located at the second conductive layer 126 and the first type doping base material 114 it
Between.First electrode 118 be configured at the one of the first conductive layer 121 back to front 123 incidence surface 113,
And 118 expose portion incidence surface 113 of first electrode.Second electrode 119 is configured at the second conductive layer 126
One back to reverse side 125 opposite face 115, and 119 expose portion opposite face 115 of second electrode.
Due to the first type doping base material 114 e.g. n-type doping base material, the first type doping semiconductor layer 112
E.g. n-type doping semiconductor layer, Second-Type doping semiconductor layer 116 are, for example, that p-type doping is partly led
Body layer, therefore semiconductor element 100 is, for example, a kind of good N-type semiconductor element 100, wherein
The characteristic of the back of the body emitter structure that first electrode 118 has by N-type semiconductor element 100 can be by
Above-mentioned light-initiated plating being formed, with the uniformity well, while it is qualified to lift making
Rate.That is, the framework of the semiconductor element 100 of the present embodiment can allow light beam L in process
Sufficiently enter incidence surface 113 to produce electronics 111, therefore more uniform electrode can be formed and carried
For being electrically connected with quality well, and then lifted the photoelectric transformation efficiency of semiconductor element 100.
Furthermore, it is understood that in the present embodiment, the first type doping semiconductor layer 112 and Second-Type adulterate
The material of semiconductor layer 116 include monocrystalline silicon, polysilicon, non-crystalline silicon, carborundum, Si oxide,
Silicon nitride or its combination, but the invention is not restricted to this.In the present embodiment, the first conductive layer 121
And second conductive layer 126 material include indium oxide, zinc oxide, metal oxide, silicon nitridation
Thing or its combination, but the invention is not restricted to this.
Fig. 2 to Fig. 5 is according to the schematic diagram for making semiconductor element in the second embodiment of the present invention.
Fig. 2 is refer to, in the second embodiment of the present invention, the preparation method of semiconductor element first provides
One type doping base material 114A, and first is formed on the front 123A that the first type adulterates base material 114A
Intrinsic layer 131A, the reverse side 125A second intrinsic layer 132A of formation of the base material 114A that adulterates in the first type.
First intrinsic layer 131A and the first type adulterate and form a hetero-junctions 133A between base material 114A, and the
Hetero-junctions 134A is formed between two intrinsic layer 132A and the first type doping base material 114A.That is,
The present embodiment is forming the first type doping semiconductor layer 112A and Second-Type doping semiconductor layer 116A
The first intrinsic layer 131A and the second intrinsic layer 132A has been initially formed before, and then has made the first type doping base
The front 123A and reverse side 125A of material 114A forms hetero-junctions.In the present embodiment, first
The forming method for levying layer 131A and the second intrinsic layer 132A includes that plasma-enhanced CVD sinks
Product, physical vapour deposition (PVD), aumospheric pressure cvd, ion-plating technique and thermal diffusion furnace technology,
But the invention is not restricted to this.
Fig. 3 is refer to, the present embodiment is forming the first type doping semiconductor layer 112A and Second-Type
After doping semiconductor layer 116A, the first conductive layer 121A is subsequently formed in the first type doped semiconductor
Layer 112A, and the second conductive layer 126A is formed in Second-Type doping semiconductor layer 116A.This enforcement
Example also forms multiple anti-reflection microstructures, that is, this reality while the first conductive layer 121A is formed
Apply.
Specifically, in the present embodiment, the surface roughness Ra of incidence surface 113A is less than 5 nanometers, enters
And increase the efficiency that e.g. light beam L1 penetrates incidence surface 113A.In other embodiments, antireflection
Micro-structural can more be formed at opposite face 115A, the invention is not restricted to this.
On the other hand, due to the front of the first type doping base material 114A of the second embodiment of the present invention
123A and reverse side 125A to form hetero-junctions, therefore can more lift semiconductor stack layer 110A
The efficiency of electronics is produced after receiving light beam L1, there is provided a good photoelectric transformation efficiency.
Refer to Fig. 4, the present embodiment formed first electrode layer 121A and the second electrode lay 126A it
Second electrode 119A is formed afterwards in opposite face 115A, and forms insulation shielding 117A in incidence surface
113A.By above-mentioned light-initiated electroplating technology, the voltage difference for putting on second electrode 119A can be with
The electronics that semiconductor stack layer 110A is produced because absorbing e.g. light beam L2 is made to reach incidence surface
113A.Therefore, semiconductor stack layer 110A can be reduced by the metal ion in environment and shape
Into first electrode 118A in incidence surface 113A.Then refer again to Fig. 5, the present embodiment is again via removing
Insulation shielding 117A is producing semiconductor element 100A.
In the present embodiment, semiconductor element 100A includes being configured at the first type doping base material 114A
And first the first intrinsic layer 131A between type doping semiconductor layer 112A and be configured at the first type
The second intrinsic layer 132A between doping base material 114A and Second-Type doping semiconductor layer 116A.The
One intrinsic layer 131A and the first type adulterate and form a hetero-junctions 133A between base material 114A, second
Levy and hetero-junctions 134A is formed between layer 132A and the first type doping base material 114A, can be lifted and partly be led
Electron generation efficiencies of the volume elements part 100A when light beam L2 is received.On the other hand, in the present embodiment
In, incidence surface 113A is electric by second more than opposite face 115A by the exposed area of first electrode 118A
The exposed areas of pole 119A.Therefore first electrode 118A can pass through N-type semiconductor element 100A
The characteristic of the back of the body emitter structure being had is being formed on incidence surface 113A well, but the present invention is not
It is limited to this.In other embodiments, incidence surface can also be electric with second by the exposed area of first electrode
Pole exposed opposite face area it is identical, the invention is not restricted to this.
In sum, the preparation method of the semiconductor element of embodiments of the invention is by providing voltage
The environment that difference is located between semiconductor stack layer and electroplated electrode and in semiconductor stack layer forms gold
Category solion, and then allow the electronics that light beam is produced in semiconductor stack layer can be in semiconductor stack
Reducing metal ions in incidence surface and the metal ion solution of layer simultaneously form electrode.Therefore semiconductor element
The formation of the electrode of part is not affected by the allocation position of additional conductive electrode, and electrode can be with adequate relief
Into on incidence surface, while the surface of semiconductor element can be avoided to paste or touching other conductive elements
Cause to damage during part, and then lift the making qualification rate of semiconductor element.The half of embodiments of the invention
The framework of conductor element can allow light beam in process sufficiently into incidence surface producing electronics, and then
Uniform electrode is formed by light-initiated plating, therefore there can be good electric connection quality.
Consequently, it is possible to more luminous energy just can be converted to electric energy by the semiconductor element of embodiments of the invention.
Although the present invention is disclosed above with embodiment, so which is not limited to the present invention, Ren Hesuo
Those of ordinary skill in category technical field, without departing from the spirit and scope of the present invention, when can make portion
The change for dividing and modification, therefore protection scope of the present invention ought be defined depending on the defined person of appended claims.
Claims (18)
1. a kind of preparation method of semiconductor element, it is characterised in that include：
Semiconductor stack layer and an electroplated electrode are provided in a solution, wherein the semiconductor stack
Layer has an incidence surface and an opposite face relative with the incidence surface；
One voltage difference is applied with the electroplated electrode to the opposite face；And
A light beam is provided to the semiconductor stack layer, wherein voltage official post electroplated electrode is provided at least
One metal ion is into the solution and forms a metal ion solution, and the semiconductor stack layer is suitable to absorb
The light beam simultaneously produces an at least electronics to the incidence surface, makes the metal ion in the metal ion solution
A first electrode is electronically formed on the incidence surface of the semiconductor stack layer with this.
2. the preparation method of semiconductor element according to claim 1, the wherein semiconductor stack
Layer also include an insulation screen, be configured on the incidence surface, the insulation screen expose portion this enter
Light face.
3. the preparation method of semiconductor element according to claim 1, wherein provides the semiconductor
The step of stack layer and the electroplated electrode in the solution includes：
One first type doping base material is provided；
One first type doping semiconductor layer is formed on a front of the first type doping base material and is formed
One Second-Type doping semiconductor layer is in first type doping base material one relative on the positive reverse side；
And
One first conductive layer is formed in the one first type doping semiconductor layer and one second conductive layer is formed
In the Second-Type doping semiconductor layer, the wherein incidence surface is located at first conductive layer, the opposite face position
In second conductive layer.
4. the preparation method of semiconductor element according to claim 3, wherein forms first type
Also include before the step of doping semiconductor layer and the Second-Type doping semiconductor layer：
One first intrinsic layer is formed on the front of the first type doping base material and one second is formed
Layer is levied on the reverse side of the first type doping base material, first intrinsic layer and first type doping base is made
A hetero-junctions is formed between material, and makes formation between second intrinsic layer and the first type doping base material another
One hetero-junctions.
5. the preparation method of semiconductor element according to claim 4, wherein first intrinsic layer
And the forming method of second intrinsic layer includes that plasma auxiliary chemical vapor deposition, physical vapor are sunk
Product, aumospheric pressure cvd, ion-plating technique and thermal diffusion furnace technology.
6. the preparation method of semiconductor element according to claim 3, wherein first type are adulterated
The forming method of semiconductor layer and the Second-Type doping semiconductor layer includes plasma auxiliary chemical gas
Mutually deposition, physical vapour deposition (PVD), aumospheric pressure cvd and thermal diffusion furnace technology.
7. the preparation method of semiconductor element according to claim 3, wherein first conductive layer
And the forming method of second conductive layer includes that plasma auxiliary chemical vapor deposition, physical vapor are sunk
Product, aumospheric pressure cvd, ion-plating technique and thermal diffusion furnace technology.
8. the preparation method of semiconductor element according to claim 3, wherein forms this and first leads
Electric layer is in the first type doped semiconductor conductive layer and forms second conductive layer in Second-Type doping
The step of semiconductor layer, includes：
Multiple anti-reflection microstructures are formed in first conductive layer and second conductive layer.
9. the preparation method of semiconductor element according to claim 1, the wherein incidence surface and should
The surface roughness Ra of opposite face is less than 5 nanometers.
10. the preparation method of semiconductor element according to claim 1, wherein provides this and partly leads
The step of body stack layer and the electroplated electrode in the solution includes：
The electroplated electrode is electrically connected to into a second electrode of the semiconductor stack layer, the second electrode
It is formed at the opposite face.
The preparation method of 11. semiconductor elements according to claim 1, the wherein ripple of the light beam
The wavelength of the long absorption bands different from the metal ion solution.
12. a kind of semiconductor elements, it is characterised in that include：
One first type doping base material；
One first type doping semiconductor layer, is configured at a front of first type doping base material；
One Second-Type doping semiconductor layer, is configured at a reverse side of first type doping base material, wherein should
Reverse side is relative to the front；
One first conductive layer, is configured on the first type doping semiconductor layer, and the first type semiconductor
Layer is located between first conductive layer and the first type doping base material；
One second conductive layer, is configured on the Second-Type doping semiconductor layer, and the Second-Type semiconductor
Layer is located between second conductive layer and the first type doping base material；
One first electrode, is configured at the one of first conductive layer back to the positive incidence surface, and this first
The electrode expose portion incidence surface；And
One second electrode, be configured at the one of second conductive layer back to the reverse side opposite face, this second
The electrode expose portion opposite face.
13. semiconductor elements according to claim 12, wherein the first type doping semiconductor layer
For n-type doping semiconductor layer, first type doping base material is n-type doping base material, and the Second-Type is mixed
Miscellaneous semiconductor layer is p-type doping semiconductor layer.
14. semiconductor elements according to claim 12, wherein first conductive layer and this second
Conductive layer has multiple anti-reflection microstructures.
15. semiconductor elements according to claim 12, the wherein incidence surface and the opposite face
Surface roughness Ra is less than 5 nanometers.
16. semiconductor elements according to claim 12, wherein the first type doping semiconductor layer
And the material of the Second-Type doping semiconductor layer include monocrystalline silicon, polysilicon, non-crystalline silicon, carborundum,
Si oxide, silicon nitride or its combination.
17. semiconductor elements according to claim 12, wherein first conductive layer and this second
The material of conductive layer includes indium oxide, zinc oxide, metal oxide, silicon nitride or its combination.
18. semiconductor elements according to claim 12, it is characterised in that also including a configuration
Adulterate in first type and the first intrinsic layer between base material and the first type doping semiconductor layer and match somebody with somebody
The second intrinsic layer that first type adulterates between base material and the Second-Type doping semiconductor layer is placed in, wherein
A hetero-junctions is formed between first intrinsic layer and first type doping base material, second intrinsic layer and should
Another hetero-junctions is formed between first type doping base material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510566785.3A CN106531817A (en) | 2015-09-08 | 2015-09-08 | Semiconductor element and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510566785.3A CN106531817A (en) | 2015-09-08 | 2015-09-08 | Semiconductor element and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106531817A true CN106531817A (en) | 2017-03-22 |
Family
ID=58345390
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510566785.3A Pending CN106531817A (en) | 2015-09-08 | 2015-09-08 | Semiconductor element and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106531817A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107833929A (en) * | 2017-10-13 | 2018-03-23 | 浙江昱辉阳光能源江苏有限公司 | The silicon heterogenous battery and manufacture method of a kind of one texture-etching side |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101257059A (en) * | 2007-11-30 | 2008-09-03 | 无锡尚德太阳能电力有限公司 | Method for electrochemical depositing solar cell metallic electrode |
| CN102021636A (en) * | 2009-09-17 | 2011-04-20 | 肖特太阳能控股公司 | Method and device for galvanising substrates |
| CN102660761A (en) * | 2012-05-11 | 2012-09-12 | 无锡尚德太阳能电力有限公司 | Solar cell film plating equipment and film plating method |
| CN102686784A (en) * | 2009-10-23 | 2012-09-19 | 弗劳恩霍弗应用技术研究院 | Method for the light-induced, galvanic pulsed deposition for forming a seed layer for a metal contact of a solar cell and for the subsequent reinforcement of said seed layer or said metal contact and arrangement for carrying out the method |
| CN103107212A (en) * | 2013-02-01 | 2013-05-15 | 中国科学院上海微系统与信息技术研究所 | Heterojunction solar battery with electroplate electrodes and preparation method |
| CN104178787A (en) * | 2013-05-26 | 2014-12-03 | 无锡尚德太阳能电力有限公司 | Solar battery coating equipment and coating method |
-
2015
- 2015-09-08 CN CN201510566785.3A patent/CN106531817A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101257059A (en) * | 2007-11-30 | 2008-09-03 | 无锡尚德太阳能电力有限公司 | Method for electrochemical depositing solar cell metallic electrode |
| CN102021636A (en) * | 2009-09-17 | 2011-04-20 | 肖特太阳能控股公司 | Method and device for galvanising substrates |
| CN102686784A (en) * | 2009-10-23 | 2012-09-19 | 弗劳恩霍弗应用技术研究院 | Method for the light-induced, galvanic pulsed deposition for forming a seed layer for a metal contact of a solar cell and for the subsequent reinforcement of said seed layer or said metal contact and arrangement for carrying out the method |
| CN102660761A (en) * | 2012-05-11 | 2012-09-12 | 无锡尚德太阳能电力有限公司 | Solar cell film plating equipment and film plating method |
| CN103107212A (en) * | 2013-02-01 | 2013-05-15 | 中国科学院上海微系统与信息技术研究所 | Heterojunction solar battery with electroplate electrodes and preparation method |
| CN104178787A (en) * | 2013-05-26 | 2014-12-03 | 无锡尚德太阳能电力有限公司 | Solar battery coating equipment and coating method |
Non-Patent Citations (1)
| Title |
|---|
| 沈文忠: "《太阳能光伏技术与应用》", 31 October 2013 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107833929A (en) * | 2017-10-13 | 2018-03-23 | 浙江昱辉阳光能源江苏有限公司 | The silicon heterogenous battery and manufacture method of a kind of one texture-etching side |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP7212786B2 (en) | Crystalline silicon solar cell and manufacturing method thereof | |
| WO2006137322A1 (en) | Solar cell element and solar cell element manufacturing method | |
| CN113594304A (en) | Preparation method of solar cell, solar cell and photovoltaic module | |
| EP4044259A1 (en) | Efficient heterojunction battery structure and preparation method therefor | |
| CN108963013A (en) | Solar battery and its manufacturing method | |
| CN103035753B (en) | Photoelectric conversion device | |
| WO2023036121A1 (en) | Battery back passivation structure, manufacturing method therefor, and solar cell | |
| TW201312779A (en) | Method for producing a solar cell and solar cell | |
| CN109148613A (en) | A kind of preparation method of the two-sided PERC solar cell of anti-PID | |
| CN115566093A (en) | Efficient selective doped battery and preparation method thereof | |
| CN111952408A (en) | Back junction solar cell with passivated metal contact and preparation method thereof | |
| US8735201B2 (en) | Film-forming method for forming passivation film and manufacturing method for solar cell element | |
| Jeong et al. | Preparation of born-doped a-SiC: H thin films by ICP-CVD method and to the application of large-area heterojunction solar cells | |
| JP6863853B2 (en) | Solar cell elements and solar cell modules | |
| CN109616556A (en) | A kind of annealing of silicon chip back side and the integrated method of front plated film and a kind of preparation method of cell piece | |
| CN106531817A (en) | Semiconductor element and manufacturing method thereof | |
| CN109041583B (en) | Solar cell element and solar cell module | |
| CN105742375B (en) | A kind of back contacts crystal silicon battery and preparation method thereof | |
| CN114597285B (en) | Solar cell manufacturing method, solar cell and photovoltaic module | |
| KR20100004193A (en) | Method for manufacturing wafer type solar cell | |
| KR20120043421A (en) | Solar cell and method of manufacturing the same | |
| JP2016187027A (en) | Crystal silicon solar cell and method of manufacturing the same, and solar cell module | |
| TWI614907B (en) | Semiconductor device and manufacturing method thereof | |
| CN102800760A (en) | Manufacture method of solar cell with multi-layer silicon nitride antireflection films | |
| CN115172479B (en) | Solar cell, preparation method thereof and photovoltaic module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20170322 |
|
| WD01 | Invention patent application deemed withdrawn after publication |