CN106531809A - Deep trench power MOS device structure and method for producing same - Google Patents
Deep trench power MOS device structure and method for producing same Download PDFInfo
- Publication number
- CN106531809A CN106531809A CN201611005996.0A CN201611005996A CN106531809A CN 106531809 A CN106531809 A CN 106531809A CN 201611005996 A CN201611005996 A CN 201611005996A CN 106531809 A CN106531809 A CN 106531809A
- Authority
- CN
- China
- Prior art keywords
- type
- layer
- groove
- termination environment
- lightly doped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title abstract description 5
- 239000004065 semiconductor Substances 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 25
- 230000008569 process Effects 0.000 claims abstract description 11
- 238000005468 ion implantation Methods 0.000 claims abstract description 6
- 230000001413 cellular effect Effects 0.000 claims description 73
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 38
- 229920005591 polysilicon Polymers 0.000 claims description 35
- 238000002360 preparation method Methods 0.000 claims description 24
- 238000005516 engineering process Methods 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 22
- 238000002347 injection Methods 0.000 claims description 17
- 239000007924 injection Substances 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 6
- 229910044991 metal oxide Inorganic materials 0.000 claims description 6
- 150000004706 metal oxides Chemical class 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 238000010276 construction Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 238000000137 annealing Methods 0.000 abstract description 7
- 238000002955 isolation Methods 0.000 abstract description 2
- 238000011109 contamination Methods 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 description 16
- 238000012545 processing Methods 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 229910015900 BF3 Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000008280 blood Substances 0.000 description 2
- 210000004369 blood Anatomy 0.000 description 2
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 238000000844 transformation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention relates to the technical field of semiconductor manufacturing and more particularly to a deep trench power MOS device structure and a method for producing the same. After body ion implantation and a annealing process, a covered P-type ion implantation process is added. A P-type lightly doped region is formed on the upper parts of N-type protection rings and the upper parts of P-type lightly doped epitaxial layers between adjacent N-type protection rings to resist N-type ion contamination in the process so that the isolation at the device periphery may maintain normal operation because of there is not a direct large leakage path, thereby improving the performance of the device.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of deep-groove power MOS component structure and its system
Preparation Method.
Background technology
With the continuous development of semiconductor technology, power mos transistor device is with the high and low loss of its input impedance, switch
Speed is fast, without second breakdown, safety operation area width, dynamic property is good, easily couple with front pole and realize high current, high conversion efficiency
The advantages of, gradually substituting bipolar device becomes the main flow of current power device development.
At present, in conventional deep-groove power MOS component technique preparation process, in dust free room, can there is free N-type
Ion.There is the board of each unit processing procedure in the source of N-type ion, the gear sky piece that production cycle is used, different in board maintenance process
Often process, the charging of the environment and raw material of factory service；N-type dissociated ion can cause the drift of device electric during processing procedure
Move. particularly for p-type metal-oxide-semiconductor, after the processing procedure after body area (body) ion implanting and annealing is finished, to finite concentration ratio
The free N-type ion of example can form very light N-type interface in device surface, be easily caused the termination environment China and foreign countries enclosure of MOS device
From structural failure, and then cause the leakage current of device bigger than normal and pressure low, this is that those skilled in the art are not expected sees
's.
The content of the invention
For above-mentioned problem, the invention discloses a kind of deep-groove power MOS component structure, including：
P-type heavy doping substrate, is divided into cellular region and termination environment above the p-type heavy doping substrate；
P-type lightly doped epitaxial layer, is arranged at the p-type heavy doping substrate；
N-type doping layer, is arranged on the p-type lightly doped epitaxial layer of the cellular region；
P-type source region layer, is arranged on the n-type doping layer；
Some cellular region grooves, sequentially pass through the p-type source region layer and the n-type doping layer, and it are light to be arranged at the p-type
In doped epitaxial layer；
Some termination environment grooves, are arranged in the p-type lightly doped epitaxial layer of the termination environment；
Some N-type protection rings, are arranged in the p-type lightly doped epitaxial layer of the termination environment, and the adjacent N-type protection ring
Between the top of p-type lightly doped epitaxial layer be formed with p-type lightly doped district.
Above-mentioned deep-groove power MOS component structure, wherein, the deep-groove power MOS component structure also includes：
Insulating medium layer, is arranged at bottom and its side wall of some cellular region grooves and some termination environment grooves
On surface, and by the upper surface of the p-type source region layer, the N-type protection ring exposed upper surface and the p-type lightly doped district
Exposed upper surface is covered；
Polysilicon layer, is arranged in some cellular region grooves and some termination environment grooves, and the polysilicon
Upper surface of the upper surface of layer less than the p-type source region layer.
Above-mentioned deep-groove power MOS component structure, wherein, the upper surface of the polysilicon layer and the p-type source region layer
Upper surface between difference in height be 10～50 angstroms.
Above-mentioned deep-groove power MOS component structure, wherein, the insulating medium layer is oxide layer.
Above-mentioned deep-groove power MOS component structure, wherein, in the n-type doping layer between the adjacent cellular region groove
It is each formed with NXing Ti areas contact zone.
Above-mentioned deep-groove power MOS component structure, wherein, the deep-groove power MOS component structure also includes being located at
Some cellular region contact holes of the cellular region and some termination environment contact holes positioned at the termination environment：
Some cellular region contact holes are arranged at institute through the insulating medium layer on the p-type source region layer
In ShuNXing Ti areas contact zone, and some termination environment contact holes are through the dielectric on the termination environment groove
Layer is arranged in the polysilicon layer in the termination environment groove.
Above-mentioned deep-groove power MOS component structure, wherein, the deep-groove power MOS component structure also includes：
Metal, full of some cellular region contact holes and some termination environment contact holes.
The invention also discloses a kind of preparation method of deep-groove power MOS component structure, comprises the steps：
A semiconductor structure for including cellular region and termination environment is provided, the semiconductor structure includes p-type heavy doping substrate
With the p-type lightly doped epitaxial layer positioned at the p-type heavy doping substrate；
Trench etch process is carried out to the semiconductor structure, with the shape in the p-type lightly doped epitaxial layer of the cellular region
Into some cellular region grooves, some termination environment grooves are formed in the p-type lightly doped epitaxial layer of the termination environment；
Some N-type protection rings are formed in the p-type lightly doped epitaxial layer of the termination environment；
Polysilicon layer is formed in some cellular region grooves and termination environment groove；
Carry out body area injection technology and mixed with the p-type lightly doped epitaxial layer top formation NXing Ti areas in the cellular region
Miscellaneous area；
Carry out p-type ion implantation technology to form the in the top of NXing Ti areas doped region to the semiconductor structure
One p-type lightly doped district, the top of the p-type lightly doped epitaxial layer between the adjacent N-type protection ring form the second p-type and are lightly doped
Area；
The preparation technology for continuing follow-up deep-groove power MOS component structure.
The preparation method of above-mentioned deep-groove power MOS component structure, wherein, the trench etch process includes：
The hard mask with groove figure is formed on the p-type lightly doped epitaxial layer；
P-type lightly doped epitaxial layer described in the hard mask as mask etching is forming the cellular region groove and the end
Petiolarea groove.
The preparation method of above-mentioned deep-groove power MOS component structure, wherein, the hard mask is oxide, nitride
And the laminated construction that oxide is formed.
The preparation method of above-mentioned deep-groove power MOS component structure, wherein, be set forth in some cellular region grooves and
The step of polysilicon layer is formed in the groove of termination environment includes：
Prepare bottom and its side that gate dielectric layer covers some cellular region grooves and some termination environment grooves
On wall surface, and the upper surface of the p-type lightly doped epitaxial layer is covered；
Deposit polycrystalline silicon layer is to be full of some cellular region grooves and termination environment groove, and covers the gate dielectric layer
Exposed upper surface；
Return and carve the polysilicon layer, so that the upper surface of the polysilicon layer is less than the p-type lightly doped epitaxial layer
Upper surface；
The preparation method of above-mentioned deep-groove power MOS component structure, wherein, the upper surface of the polysilicon layer with it is described
Difference in height between the upper surface of p-type lightly doped epitaxial layer is 10～50 angstroms.
The preparation method of above-mentioned deep-groove power MOS component structure, wherein, it is described to continue follow-up power MOS (Metal Oxide Semiconductor) device
Preparation technology comprise the steps：
P-type source region, the p-type are formed at the top of the NXing Ti areas doped region between the adjacent cellular region groove
Source region covers the first p-type lightly doped district；
Insulating medium layer is formed on the semiconductor structure；
The insulating medium layer, the p-type source region are sequentially etched according to order from top to bottom to adulterate to the NXing Ti areas
Stop in area to form cellular region contact hole, and the insulating medium layer on the termination environment groove is etched to the terminal
Stop forming termination environment contact hole in polysilicon layer in area's groove.
Hole injection technology is carried out to NXing Ti areas doped region by the cellular region contact hole, and by the terminal
Area's contact hole carries out hole injection technology to the polysilicon layer in the termination environment groove, with the cellular region contact hole and terminal
The bottom periphery of area's contact hole forms NXing Ti areas contact zone；
In the contact hole, deposited metal is forming the power MOS (Metal Oxide Semiconductor) device.
Foregoing invention has the advantage that or beneficial effect：
The invention discloses a kind of deep-groove power MOS component structure and preparation method thereof, by finishing body area ion
Injection and processing procedure after annealing, increase by one cover type (blanket) p-type ion implantation technology, in N-type protection ring top and adjacent
P-type lightly doped district is formed at the top of the p-type lightly doped epitaxial layer between N-type protection ring, dirty with the N-type ion in resisting process
Dye, makes the isolation of device periphery be maintained normal work due to not direct big leakage path, so as to improve device
Performance.
Description of the drawings
By reading the detailed description made to non-limiting example with reference to the following drawings, the present invention and its feature, outward
Shape and advantage will become more apparent.In whole accompanying drawings, identical mark indicates identical part.Not can according to than
Example draws accompanying drawing, it is preferred that emphasis is illustrate the purport of the present invention.
Fig. 1 is the schematic diagram of deep-groove power MOS component structure in the embodiment of the present invention；
Fig. 2 is the method flow diagram of deep-groove power MOS component structure in the embodiment of the present invention；
Fig. 3～17 are that the flowage structure of the preparation method of deep-groove power MOS component structure in the embodiment of the present invention is illustrated
Figure.
Specific embodiment
The present invention is further illustrated with specific embodiment below in conjunction with the accompanying drawings, but not as the limit of the present invention
It is fixed.
Embodiment one：
As shown in figure 1, the present embodiment is related to the invention discloses a kind of deep-groove power MOS component structure, specifically, is somebody's turn to do
Deep-groove power MOS component structure includes that top is divided into the p-type heavy doping substrate 100 of cellular region and termination environment, is arranged at p-type weight
P-type lightly doped epitaxial layer 101 (such as P- silicon layers) on doped substrate 100, is arranged at the p-type lightly doped epitaxial layer of cellular region
N-type doping layer 102, the p-type source region layer 103 being arranged on n-type doping layer 102 on 101, sequentially pass through p-type source region layer
103 and n-type doping layer 102, and be arranged at some cellular region grooves 104 in the p-type lightly doped epitaxial layer 101 of cellular region, set
The some termination environment grooves 105 being placed in the p-type lightly doped epitaxial layer 101 of termination environment and the p-type for being arranged at termination environment are gently mixed
Some N-type protection rings 106 in miscellaneous epitaxial layer 101, the p-type lightly doped epitaxial layer 101 between adjacent N-type protection ring 106 it is upper
Portion is formed with p-type lightly doped district 107；Further, aforementioned p-type heavy doping substrate 100 is included as drain region with
The p-type heavy doping substrate (such as P++ silicon chips) 101 of one doping content and positioned at this have the first doping content p-type heavy doping
The p-type heavy doping substrate with the second doping content (such as extension P+ silicon layer) 1002 above substrate 1001, and the first doping
Concentration is more than the second doping content.
In a preferred embodiment of the invention, above-mentioned deep-groove power MOS component structure is also some including being arranged at
Polysilicon layer 109 in cellular region groove 104 and some termination environment grooves 105, it is arranged at cellular region groove 104 and polysilicon layer
With by polysilicon layer 109 and cellular region groove 104 between 109 and between some termination environment grooves 105 and polysilicon layer 109
Wall surface, polysilicon layer 109 and 105 inner wall surface of termination environment groove are isolated, and by the upper surface of p-type source region layer 103, N
Covered the exposed upper surface of the upper surface of type protection ring 106, the upper surface of polysilicon layer 109 and p-type lightly doped district 107
The insulating medium layer 108 of lid, the upper surface of above-mentioned polysilicon layer 109 are less than the upper surface of p-type source region layer 103, and above-mentioned polycrystalline
Difference in height between the upper surface of silicon layer 109 and the upper surface of p-type source region layer 103 be 10～50 angstroms (such as 10 angstroms, 20 angstroms, 25
Angstrom or 50 angstroms etc.)；Further, above-mentioned insulating medium layer 108 is oxide layer.
In a preferred embodiment of the invention, in the n-type doping layer 102 between above-mentioned adjacent cellular region groove 104
It is each formed with NXing Ti areas contact zone 110.
In a preferred embodiment of the invention, above-mentioned deep-groove power MOS component structure is also included positioned at cellular region
Some cellular region contact holes 111 and some termination environment contact holes 112 positioned at termination environment：Some cellular region contact holes 111 are passed through
Wear the insulating medium layer 108 on p-type source region layer 103 to be arranged in NXing Ti areas contact zone 110, and some termination environments connect
Contact hole 112 is arranged at the polysilicon in termination environment groove 105 through the insulating medium layer 108 on termination environment groove 105
In layer 109.
In a preferred embodiment of the invention, if above-mentioned deep-groove power MOS component structure is also included full of above-mentioned
Dry cellular region contact hole 111 and some termination environment contact holes 112, and cover the metal level of the upper surface of insulating medium layer 108
113。
Embodiment two：
As shown in Fig. 2 the present embodiment is related to a kind of preparation method of deep-groove power MOS component structure, specifically, the party
Method comprises the steps：
Step S1, there is provided one has the semiconductor structure of cellular region and termination environment, and the semiconductor structure includes p-type heavy doping
Substrate 200 and the p-type lightly doped epitaxial layer on p-type heavy doping substrate 200 201 (such as P- silicon layers)；Preferably, the P
Type heavy doping substrate 200 includes the p-type heavy doping substrate 200 (N++ silicon layers) with the first doping content and be located at should be with the
2002 (the N+ silicon of p-type heavy doping substrate with the second doping content on the p-type heavy doping substrate 2001 of one doping content
Layer), and the first doping content is more than the second doping content, structure as shown in Figure 3.
Specifically, the forming method of the semiconductor structure includes：The extension P+ silicon above the P++ silicon chips as drain region
Layer and P- silicon layers, and wherein p-type Doped ions can be the one kind in boron (B), boron fluoride (BF2) or combination.
Step S2, carries out trench etch process to semiconductor structure, with the p-type lightly doped epitaxial layer 201 of cellular region
Some cellular region grooves 2031 are formed, some termination environment grooves 2032 are formed in the p-type lightly doped epitaxial layer 201 of termination environment,
Structure as shown in Figures 4 and 5.
In embodiments of the present invention, step S2 specifically includes following steps：
Step S21, (to could also say that and be sequentially depositing oxygen on (p-type lightly doped epitaxial layer 201) in above-mentioned semiconductor structure
Compound layer (OX), nitride layer (SIN) and oxide skin(coating) (OX), to form hard mask 202, i.e., the hard mask 202 is by aoxidizing
The laminated construction that thing, nitride and oxide are formed.
Step S22, carries out photoetching and etching to hard mask 202, to form the hard mask 202 with groove figure, such as Fig. 4
Shown structure.
Step S23, with above-mentioned hard mask 202 as mask etching p-type lightly doped epitaxial layer 201, to be formed positioned at cellular region
P-type lightly doped epitaxial layer 201 in some cellular region grooves 2031 and in the p-type lightly doped epitaxial layer 201 of termination environment
Some termination environment grooves 2032, structure as shown in Figure 5.
Step S3, forms some N-type protection rings 204 in the p-type lightly doped epitaxial layer 201 of termination environment；Should due to being formed
The technique of some N-type protection rings 204 is well known to those skilled in the art, and here is not just repeated, knot as shown in Figure 6
Structure.
Step S4, the formation polysilicon layer 207 ' in some cellular region grooves 2031 and termination environment groove 2032, such as Fig. 7～
Structure shown in 10.
In embodiments of the present invention, step S4 specifically includes following steps：
Step S41, after removing above-mentioned hard mask 202, prepares sacrificial oxide layer 205 and covers above-mentioned some cellular region grooves
2031 and bottom and its sidewall surfaces of termination environment groove 2032, structure as shown in Figure 7.
Step S42, and after above-mentioned sacrificial oxide layer 202 is removed, prepare gate dielectric layer 206 and cover some cellular region ditches
On the bottom and its sidewall surfaces of groove 2031 and termination environment groove 2032, and the upper surface of p-type lightly doped epitaxial layer 201 is given
Cover, it is preferred that the material of gate dielectric layer 206 be oxide, structure as shown in Figure 8.
Step S43, deposit polycrystalline silicon 207 is to be full of some 2031 and termination environment groove 2032, and covers gate dielectric layer
206 exposed upper surfaces, structure as shown in Figure 9.
Step S44, returns and carves polysilicon 207, so that the upper surface of the polysilicon layer 207 ' for being formed is lightly doped outward less than p-type
Prolong the upper surface of layer 201；Preferably, between the upper surface of the upper surface of polysilicon layer 207 ' and p-type lightly doped epitaxial layer 201
Difference in height be 10～50 angstroms (such as 10 angstroms, 20 angstroms, 25 angstroms or 50 angstroms etc.), structure as shown in Figure 10.
Step S5, carries out body area injection technology with 201 top of p-type lightly doped epitaxial layer in cellular region and forms NXing Ti areas
Doped region 208, specifically, the ion injected in above-mentioned body area injection technology can be phosphorus (P), and the body area injection technology includes body
The step of area's photoetching, doping injection and high annealing.Now, after the processing procedure for finishing body area (body) ion implanting and annealing,
Device surface in termination environment can form very light N-type interface 209 (N-- areas), structure as shown in figure 11.
Step S6, the semiconductor structure to completing step S5 carry out p-type ion implantation technology (blanket IMP) with N
First p-type lightly doped district 2101 is formed at the top of Xing Ti areas doped region 208, and the p-type between adjacent N-type protection ring 204 is gently mixed
Second p-type lightly doped district 2102 is formed at the top of miscellaneous epitaxial layer 201；Structure as shown in figure 12.
Step S7, the preparation technology for continuing follow-up deep-groove power MOS component structure, the knot as shown in Figure 13～17
Structure.
In a preferred embodiment of the invention, the preparation technology for continuing follow-up power MOS (Metal Oxide Semiconductor) device includes following step
Suddenly：
Step S71, carries out source region photoetching and P+ ion implantings (using XP light shields), and injection ion can be B, BF, BF2P
One kind or combination, carry out annealing process afterwards, with the NXing Ti areas doped region 208 between adjacent cellular region groove 2031
P-type source region (P+ type source region) 211 is formed at top, and the p-type source region 211 covers the first p-type lightly doped district 2101, i.e. the first P of original
Type lightly doped district 2101 is ion implanted formed p-type source region 211 part or all, structure as shown in fig. 13 that.
Step S72, forms insulating medium layer 212, the insulating medium layer on the semiconductor structure formed by step S71
212 are full of cellular region groove 2031 and termination environment groove 2032, and the upper surface of covering gate dielectric layer 206, as shown in figure 14
Structure.
Step S73, is sequentially etched insulating medium layer 212, p-type source region 211 according to order from top to bottom and mixes to NXing Ti areas
Stop in miscellaneous area 208 to form cellular region contact hole 2131, and etch the insulating medium layer on termination environment groove 2032
The middle stopping of polysilicon layer 207 ' in 212 to termination environment groove 2032 is to form termination environment contact hole 2132, as shown in figure 15
Structure.
Step S74, carries out hole injection technology by cellular region contact hole 2131 to NXing Ti areas doped region 208, and by eventually
Petiolarea contact hole 2132 carries out hole injection technology to the polysilicon layer 207 ' in termination environment groove 2032, with cellular region contact hole
2131 and the bottom periphery of termination environment contact hole 2132 form NXing Ti areas contact zone 214, Ji Ti areas contact area and other nothings
Need the region of source region injection to carry out N++ ion implantings, make these regional transformations be N-type, injection ion can be P, and in ion
High annealing is carried out after injection, to form NXing Ti areas contact area, structure as shown in figure 16.
Step S75, continues at deposited metal 215 in above-mentioned cellular region contact hole 2131 and termination environment contact hole 2132, and
Photoetching is carried out to metal 215, that etching forms metal is in electrical contact, wherein cell region is that full wafer source body contacting metal leans on deep trench
The insulating medium layer 212 on surface is electrically isolated, structure as shown in figure 17
It is seen that, the present embodiment is the method reality corresponding with the embodiment of above-mentioned deep-groove power MOS component structure
Apply example, the present embodiment can be worked in coordination enforcement with the embodiment of above-mentioned deep-groove power MOS component structure.Above-mentioned deep-groove power
The relevant technical details mentioned in the embodiment of MOS device structure are still effective in the present embodiment, in order to reduce repetition, here
Repeat no more.Correspondingly, the relevant technical details mentioned in present embodiment are also applicable in above-mentioned deep-groove power MOS component
In the embodiment of structure.
It should be appreciated by those skilled in the art that those skilled in the art are can be with reference to prior art and above-described embodiment
Change case is realized, be will not be described here.Such change case has no effect on the flesh and blood of the present invention, will not be described here.
Above presently preferred embodiments of the present invention is described.It is to be appreciated that the invention is not limited in above-mentioned
Particular implementation, wherein the equipment and structure that do not describe in detail to the greatest extent are construed as giving reality with the common mode in this area
Apply；Any those of ordinary skill in the art, under without departing from technical solution of the present invention ambit, all using the disclosure above
Methods and techniques content make many possible variations and modification to technical solution of the present invention, or be revised as equivalent variations etc.
Effect embodiment, this has no effect on the flesh and blood of the present invention.Therefore, every content without departing from technical solution of the present invention, foundation
The technical spirit of the present invention still falls within the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification
In the range of technical scheme protection.
Claims (13)
1. a kind of deep-groove power MOS component structure, it is characterised in that include：
P-type heavy doping substrate, is divided into cellular region and termination environment above the p-type heavy doping substrate；
P-type lightly doped epitaxial layer, is arranged at the p-type heavy doping substrate；
N-type doping layer, is arranged on the p-type lightly doped epitaxial layer of the cellular region；
P-type source region layer, is arranged on the n-type doping layer；
Some cellular region grooves, sequentially pass through the p-type source region layer and the n-type doping layer, and are arranged at the p-type and be lightly doped
In epitaxial layer；
Some termination environment grooves, are arranged in the p-type lightly doped epitaxial layer of the termination environment；
Some N-type protection rings, are arranged in the p-type lightly doped epitaxial layer of the termination environment, and between the adjacent N-type protection ring
The top of p-type lightly doped epitaxial layer be formed with p-type lightly doped district.
2. deep-groove power MOS component structure as claimed in claim 1, it is characterised in that the deep-groove power MOS component
Structure also includes：
Insulating medium layer, is arranged at bottom and its sidewall surfaces of some cellular region grooves and some termination environment grooves
On, and will be the upper surface of the p-type source region layer, the N-type protection ring exposed upper surface and the p-type lightly doped district exposed
Upper surface covered；
Polysilicon layer, is arranged in some cellular region grooves and some termination environment grooves, and the polysilicon layer
Upper surface of the upper surface less than the p-type source region layer.
3. deep-groove power MOS component structure as claimed in claim 2, it is characterised in that the upper surface of the polysilicon layer
And the difference in height between the upper surface of the p-type source region layer is 10～50 angstroms.
4. deep-groove power MOS component structure as claimed in claim 2, it is characterised in that the insulating medium layer is oxidation
Layer.
5. deep-groove power MOS component structure as claimed in claim 2, it is characterised in that the adjacent cellular region groove it
Between n-type doping layer in be each formed with NXing Ti areas contact zone.
6. deep-groove power MOS component structure as claimed in claim 5, it is characterised in that the deep-groove power MOS component
Structure also includes some cellular region contact holes positioned at the cellular region and some termination environment contact holes positioned at the termination environment：
Some cellular region contact holes are arranged at the N through the insulating medium layer on the p-type source region layer
In Xing Ti areas contact zone, and some termination environment contact holes are set through the insulating medium layer on the termination environment groove
In the polysilicon layer being placed in the termination environment groove.
7. deep-groove power MOS component structure as claimed in claim 6, it is characterised in that the deep-groove power MOS component
Structure also includes：
Metal, full of some cellular region contact holes and some termination environment contact holes.
8. a kind of preparation method of deep-groove power MOS component structure, it is characterised in that comprise the steps：
A semiconductor structure for including cellular region and termination environment is provided, the semiconductor structure includes p-type heavy doping substrate and position
In the p-type lightly doped epitaxial layer of the p-type heavy doping substrate；
Trench etch process is carried out to the semiconductor structure, if to be formed in the p-type lightly doped epitaxial layer of the cellular region
Dry cellular region groove, forms some termination environment grooves in the p-type lightly doped epitaxial layer of the termination environment；
Some N-type protection rings are formed in the p-type lightly doped epitaxial layer of the termination environment；
Polysilicon layer is formed in some cellular region grooves and termination environment groove；
Carry out body area injection technology and NXing Ti areas doped region is formed with the p-type lightly doped epitaxial layer top in the cellular region；
Carry out p-type ion implantation technology to form the first p-type in the top of NXing Ti areas doped region to the semiconductor structure
Lightly doped district, the top of the p-type lightly doped epitaxial layer between the top of the N-type protection ring and the adjacent N-type protection ring
Form the second p-type lightly doped district；
The preparation technology for continuing follow-up deep-groove power MOS component structure.
9. the preparation method of deep-groove power MOS component structure as claimed in claim 8, it is characterised in that the groove is carved
Etching technique includes：
The hard mask with groove figure is formed on the p-type lightly doped epitaxial layer；
P-type lightly doped epitaxial layer described in the hard mask as mask etching is forming the cellular region groove and the termination environment
Groove.
10. the preparation method of low on-resistance power MOS (Metal Oxide Semiconductor) device with groove structure as claimed in claim 9, it is characterised in that institute
State the laminated construction that hard mask is that oxide, nitride and oxide are formed.
The preparation method of 11. deep-groove power MOS component structures as claimed in claim 8, it is characterised in that be set forth in described
The step of polysilicon layer is formed in some cellular region grooves and termination environment groove includes：
Prepare bottom and its side wall table that gate dielectric layer covers some cellular region grooves and some termination environment grooves
On face, and the upper surface of the p-type lightly doped epitaxial layer is covered；
Deposit polycrystalline silicon layer is to be full of some cellular region grooves and termination environment groove, and it is exposed to cover the gate dielectric layer
Upper surface；
Return and carve the polysilicon layer, so that upper table of the upper surface of the polysilicon layer less than the p-type lightly doped epitaxial layer
Face.
The preparation method of 12. deep-groove power MOS component structures as claimed in claim 11, it is characterised in that the polycrystalline
Difference in height between the upper surface of the upper surface of silicon layer and the p-type lightly doped epitaxial layer is 10～50 angstroms.
The preparation method of 13. deep-groove power MOS component structures as claimed in claim 8, it is characterised in that after the continuation
The preparation technology of continuous power MOS (Metal Oxide Semiconductor) device comprises the steps：
P-type source region, the p-type source region are formed at the top of the NXing Ti areas doped region between the adjacent cellular region groove
Cover the first p-type lightly doped district；
Insulating medium layer is formed on the semiconductor structure；
The insulating medium layer, the p-type source region are sequentially etched into NXing Ti areas doped region according to order from top to bottom
Stop forming cellular region contact hole, and the insulating medium layer on the termination environment groove is etched to the termination environment ditch
Stop forming termination environment contact hole in polysilicon layer in groove.
Hole injection technology is carried out to NXing Ti areas doped region by the cellular region contact hole, and is connect by the termination environment
Contact hole carries out hole injection technology to the polysilicon layer in the termination environment groove, to connect in the cellular region contact hole and termination environment
The bottom periphery of contact hole forms NXing Ti areas contact zone；
In the contact hole, deposited metal is forming the power MOS (Metal Oxide Semiconductor) device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611005996.0A CN106531809B (en) | 2016-11-15 | 2016-11-15 | deep trench power MOS device structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611005996.0A CN106531809B (en) | 2016-11-15 | 2016-11-15 | deep trench power MOS device structure and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106531809A true CN106531809A (en) | 2017-03-22 |
| CN106531809B CN106531809B (en) | 2019-12-17 |
Family
ID=58353349
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611005996.0A Active CN106531809B (en) | 2016-11-15 | 2016-11-15 | deep trench power MOS device structure and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106531809B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100219461A1 (en) * | 2008-08-06 | 2010-09-02 | Mark Rinehimer | Structure With PN Clamp Regions Under Trenches |
| CN102403346A (en) * | 2010-09-08 | 2012-04-04 | 株式会社电装 | Semiconductor device and method of manufacturing the same |
| CN103972289A (en) * | 2013-01-31 | 2014-08-06 | 瑞萨电子株式会社 | Semiconductor Device And Method Of Manufacturing Semiconductor Device |
-
2016
- 2016-11-15 CN CN201611005996.0A patent/CN106531809B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100219461A1 (en) * | 2008-08-06 | 2010-09-02 | Mark Rinehimer | Structure With PN Clamp Regions Under Trenches |
| CN102403346A (en) * | 2010-09-08 | 2012-04-04 | 株式会社电装 | Semiconductor device and method of manufacturing the same |
| CN103972289A (en) * | 2013-01-31 | 2014-08-06 | 瑞萨电子株式会社 | Semiconductor Device And Method Of Manufacturing Semiconductor Device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106531809B (en) | 2019-12-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7981783B2 (en) | Semiconductor device and method for fabricating the same | |
| US10505033B2 (en) | Electronic device of vertical MOS type with termination trenches having variable depth | |
| US8575691B2 (en) | Lateral-diffusion metal-oxide semiconductor device | |
| US6303961B1 (en) | Complementary semiconductor devices | |
| US20220045210A1 (en) | Method for fabricating shield gate mosfet | |
| CN108962989B (en) | Groove type MOS device and manufacturing method thereof | |
| CN104992977A (en) | Nldmos device and manufacturing method thereof | |
| CN106449753A (en) | Low on-state resistance groove power MOS (Metal Oxide Semiconductor) device structure and fabrication method thereof | |
| CN103151268A (en) | Vertical double-diffused field-effect tube and manufacturing process thereof | |
| CN106033744B (en) | Method for manufacturing semiconductor device | |
| CN103456673A (en) | STI (shallow trench isolation) preparation method and CMOS (complementary metal oxide semiconductor) manufacturing method | |
| CN108807502B (en) | Manufacturing method of NLDMOS device and LDMOS power device | |
| CN105206675A (en) | Nldmos device and manufacturing method thereof | |
| CN106531809A (en) | Deep trench power MOS device structure and method for producing same | |
| CN112018038B (en) | Preparation method of semiconductor device | |
| CN103839981B (en) | A kind of semiconductor device and manufacture method thereof | |
| KR20110079021A (en) | Semiconductor device method for manufacturing the same | |
| CN112309853A (en) | Preparation method of shielded gate trench structure | |
| CN103779416A (en) | Low VF power MOSFET device and manufacturing method thereof | |
| CN108511529B (en) | Manufacturing method of NLDMOS device and LDMOS power device | |
| CN111092113B (en) | Terminal area structure of metal oxide semiconductor field effect transistor and manufacturing method thereof | |
| CN103383926A (en) | Increased transistor performance by implementing an additional cleaning process in a stress liner approach | |
| CN219873541U (en) | SGT MOSFET device structure | |
| CN106449758A (en) | Trench power MOS device structure and preparation method thereof | |
| US11417761B1 (en) | Transistor structure and method for fabricating the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 401331 No. 25 Xiyong Avenue, Xiyong Town, Shapingba District, Chongqing Applicant after: Huarun Microelectronics (Chongqing) Co., Ltd. Address before: 401331 No. 25 Xiyong Avenue, Xiyong Town, Shapingba District, Chongqing Applicant before: China Aviation (Chongqing) Microelectronics Co., Ltd. |
|
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: 401331 No. 25 Xiyong Avenue, Shapingba District, Chongqing Applicant after: Huarun Microelectronics (Chongqing) Co., Ltd. Address before: 401331 No. 25 Xiyong Avenue, Xiyong Town, Shapingba District, Chongqing Applicant before: Huarun Microelectronics (Chongqing) Co., Ltd. |
|
| CB02 | Change of applicant information | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |