CN103972289A - Semiconductor Device And Method Of Manufacturing Semiconductor Device - Google Patents

Semiconductor Device And Method Of Manufacturing Semiconductor Device Download PDF

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Publication number
CN103972289A
CN103972289A CN201410015627.4A CN201410015627A CN103972289A CN 103972289 A CN103972289 A CN 103972289A CN 201410015627 A CN201410015627 A CN 201410015627A CN 103972289 A CN103972289 A CN 103972289A
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recess
dielectric film
groove
insulating film
thickness
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CN103972289B (en
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徳田悟
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Renesas Electronics Corp
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Renesas Electronics Corp
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor

Abstract

A first lower insulating film (LIL1) is formed on the bottom surface and a lower portion of the side surface of a first concave portion (gate trench) and is thicker than a gate insulating film (GIF). An upper end of LIL1 is connected to a lower end of the GIF. A second lower insulating film is formed on the bottom surface and a lower portion of the side surface of a second concave portion (termination trench). An upper insulating film (UIF) is formed at an upper portion of the side surface of the second concave portion and a lower end is connected to an upper end of LIL2. The depth of the second concave portion is >=90% and !<=110% of the depth of the first concave portion. The thickness of LIL2 is >=95% and !<=105% of the thickness of LIL1. The UIF is thicker than the GIF.

Description

The method of semiconductor device and manufacture semiconductor device
The application, based on Japanese patent application No.2013-017588, is incorporated in this as a reference by the content of this application by reference.
Technical field
The present invention relates to the method for semiconductor device and manufacture semiconductor device, especially the present invention relates to be applied to the technology of the semiconductor device for example, with vertical-type transistor (, thering is trench gate structure).
Background technology
As the semiconductor device of a type, have and there is the transistorized semiconductor device of vertical-type.Vertical-type transistor is for for example controlling the element of large electric current.As vertical-type transistor, there is the transistor with trench gate structure.Trench-gate transistor is so a kind of structure, wherein in Semiconductor substrate, forms recess, on the side surface of this recess, forms gate insulating film, and in this recess, embed gate electrode subsequently.
In recent years, there is following various structures, wherein, in the time seeing in the plane graph on every kind of structure, provide in trench-gate outside and stop groove (reference example as, unexamined Japanese Patent Application Publication No.2002-299618, unexamined Japanese Patent Application Publication (translation of PCT application) No.2007-528598, unexamined Japanese Patent Application Publication No.2012-19188 and unexamined Japanese Patent Application Publication (translation of PCT application) No.2010-541289).
Structure described in unexamined Japanese Patent Application Publication No.2002-299618 is that a kind of channel shaped that wherein stops becomes the structure more shallow than trench-gate.
In unexamined Japanese Patent Application Publication (translation of PCT application) No.2007-528598, describe in the membrane structure of dielectric film that stops forming on the side surface of groove different with the membrane structure of gate insulating film.Particularly, deposit supplementary insulation film on the dielectric film of the layer identical with the gate insulating film of bottom surface with the bottom of the side surface in trench-gate and on the side surface of termination groove and basal surface.In addition, stop groove side surface top on the side of trench electrode, do not form this supplementary insulation film.
Structure described in unexamined Japanese Patent Application Publication No.2012-19188 is a kind of such structure, and the dielectric film wherein stopping on the basal surface of groove is manufactured thinlyyer than the dielectric film on the basal surface of trench-gate.
Structure described in unexamined Japanese Patent Application Publication (translation of PCT application) No.2010-541289 is a kind of such structure, and the dielectric film wherein stopping on trench bottom surfaces and side surface is manufactured thicklyer than the dielectric film on the basal surface of trench-gate and side surface (comprising gate insulating film).
Summary of the invention
As a desired characteristic in transistor, there is low on-resistance.As the result of the research of being undertaken by the present inventor, find to become the intercalation electrode that stops groove in the case of providing, in applying drain voltage, electric field strength increases at the oxidation film of grid place that stops groove, and therefore, gate insulating film suffers dielectric breakdown sometimes.As a kind of means that prevent this situation, can use the thickening of gate insulating film, still, thickening can cause the increase of conducting resistance.
To become clear from other task and novel feature of the description of this specification and accompanying drawing.
In one embodiment, form gate insulating film on the top of the first recess side surface.This first recess forms in basalis (base layer) and its lower end is arranged in low concentration impurity layer.On the basal surface of the first recess and the bottom of side surface, form the first bottom dielectric film, and it is than gate insulator thickness.In addition, the upper end of the first bottom dielectric film is connected to the lower end of gate insulating film.Gate electrode is embedded in the first recess.Source layer is the first conduction type, be formed on than in the shallow basalis of described basalis, and position is close to the first recess in the time seeing in plane graph.The second bottom dielectric film is formed on the basal surface of the second recess and the bottom of side surface.Top place at the second recess side surface forms upper portion insulating film, and its lower end is connected to the upper end of the second bottom dielectric film.While seeing in plane graph, the second recess is around the first recess.Intercalation electrode is embedded in the second recess.The degree of depth of the second recess be more than or equal to the first recess depths 90% and be less than or equal to 110% of the first recess depths.In addition, the thickness of the second bottom dielectric film be greater than or equal to the first bottom insulator film thickness 95% and be less than or equal to 105% of the first bottom insulator film thickness.Upper portion insulating film is than gate insulator thickness.
According to an above-mentioned embodiment, can be suppressed at the increase of electric field strength in the gate insulating film that stops groove while applying drain voltage, and therefore can improve reliability.
Brief description of the drawings
Description below in conjunction with accompanying drawing to some preferred embodiment, above-mentioned purpose of the present invention and other object, advantage and feature will become more obvious, wherein:
Figure 1A and 1B are according to the plane graph of the semiconductor device of the first embodiment;
Fig. 2 A and 2B are the plane graphs of the amplification of the main cross section of semiconductor device;
Fig. 3 is the plane graph of the amplification of the main cross section of semiconductor device;
Fig. 4 A and 4B are the viewgraph of cross-section of semiconductor device;
Fig. 5 A to 5C is the viewgraph of cross-section that the method for manufacturing semiconductor device is shown;
Fig. 6 A to 6C is the viewgraph of cross-section that the method for manufacturing semiconductor device is shown;
Fig. 7 A to 7C is the viewgraph of cross-section that the method for manufacturing semiconductor device is shown;
Fig. 8 A to 8C is the viewgraph of cross-section that the method for manufacturing semiconductor device is shown;
Fig. 9 A to 9C is the viewgraph of cross-section that the method for manufacturing semiconductor device is shown;
Figure 10 A to 10C is the viewgraph of cross-section that the method for manufacturing semiconductor device is shown;
Figure 11 is the viewgraph of cross-section illustrating according to the configuration of the semiconductor device of the second embodiment;
Figure 12 A to 12C illustrates to manufacture according to the viewgraph of cross-section of a kind of method of the semiconductor device of the second embodiment; And
Figure 13 A and 13B are the figure of the effect for describing the first embodiment.
Specific embodiment
Referring now to illustrative embodiment, the present invention is described.Those skilled in the art will recognize that, utilize instruction of the present invention can realize many alternate embodiments, and the invention is not restricted to the embodiment illustrating for task of explanation.
Hereinafter, will utilize accompanying drawing to describe embodiment.In addition, in all figure, identical reference marker instruction for identical Constitution Elements, and will not repeat its description.
(the first embodiment)
Describe according to the semiconductor device of the first embodiment with reference to Figure 1A to 4B.Figure 1A and 1B are according to the plane graph of the semiconductor device of this embodiment.Fig. 2 A, 2B and 3 are amplification views of the main cross section of this semiconductor device.Fig. 4 A and 4B are the viewgraph of cross-section of this semiconductor device.
In Figure 1A to 4B, reference number C E represents unit area, DE represents that grid draws region, EE represents outer regions, TRg represents gate trench, TRd represents to draw groove, TRe represents to stop groove, CTs, CTd and CTg represent contact hole, Ms represents source wiring, Mg represents grid wiring, PG represents connector, BR represents barrier metal film, OPs and OPg represent opening portion, SUB represents substrate, SB represents substrate body, EP represents epitaxial loayer, GE represents gate electrode, PR represents p-type region, NR represents N-shaped region, GI represents gate insulating film, CD represents electric conductor, FIL1 represents the first bottom dielectric film, FIL2 represents the second bottom dielectric film, FIH represents upper portion insulating film, BE represents back electrode, and VE represents intercalation electrode.
There is drain electrode layer (substrate body SB), low concentration impurity layer (epitaxial loayer EP), basalis (p-type region PR), gate insulating film GI, gate electrode GE, the first bottom dielectric film FIL1, the second bottom dielectric film FIL2, source layer (N-shaped region NR), upper portion insulating film FIH and intercalation electrode VE according to the semiconductor device of this embodiment.Drain electrode layer (substrate body SB) is the first conduction type (in the following description, being called N-shaped).Low concentration impurity layer (epitaxial loayer EP) is N-shaped, is formed on drain electrode layer (substrate body SB) upper, and has than the low impurity concentration of drain electrode layer (substrate body SB).Basalis (p-type region PR) is the second conduction type (in the following description, being called p-type), and is positioned on low concentration impurity layer (epitaxial loayer EP).Gate insulating film GI is formed on the top place of the side surface of the first recess (gate trench TRg).The first recess (gate trench TRg) is formed in basalis (p-type region PR), and its lower end is arranged in low concentration impurity layer (epitaxial loayer EP).The first bottom dielectric film FIL1 is formed on the basal surface of the first recess (gate trench TRg) and the bottom of side surface, and thicker than gate insulating film GI.In addition, the upper end of the first bottom dielectric film FIL1 is connected to the lower end of gate insulating film GI.Gate electrode GE is embedded in the first recess (gate trench TRg).Source layer (N-shaped region NR) is N-shaped, is formed in basalis (p-type region PR), more shallow than basalis (p-type region PR), and position is close to the first recess (gate trench TRg) in the time seeing in plane graph.The second bottom dielectric film FIL2 is formed on the basal surface of the second recess (stopping groove TRe) and the bottom of side surface.Upper portion insulating film FIH is formed on the top place of the side surface of the second recess (stopping groove TRe), and its lower end is connected to the upper end of the second bottom dielectric film FIL2.In the time seeing in plane graph, the second recess (stopping groove TRe) is around the first recess (gate trench TRg).Intercalation electrode VE is embedded in the second recess (stopping groove TRe).
The degree of depth of the second recess (stop groove TRe) be more than or equal to the first recess (gate trench TRg) the degree of depth 90%, and be less than or equal to the first recess (gate trench TRg) the degree of depth 110%.In addition, the thickness of the second bottom dielectric film FIL2 is more than or equal to 95% of the first bottom dielectric film FIL1 thickness, and is less than or equal to 105% of the first bottom dielectric film FIL1 thickness.FIH is thicker than gate insulating film GI for upper portion insulating film.
Hereinafter will be specifically described.
First, with reference to Figure 1A, the general introduction to semiconductor device distributing is described.Figure 1A is plane graph and the region that utilizes dash area to show wherein to form grid wiring Mg and the source wiring Ms of semiconductor device.Source wiring Ms is arranged on the central part office of semiconductor device.Grid wiring Mg along the edge annular of semiconductor device form, thereby around source wiring Ms.Each in source wiring Ms and grid wiring Mg uses the passivating film (not shown) of being made up of such as nitride film, polyimide film etc. to cover.The opening portion OPs and the OPg(aperture position that in the presumptive area of passivating film, are provided for respectively jointing metal line etc. are shown by dashed lines).
Next, carry out with reference to the plane graph of Figure 1B the layout that description unit region CE, grid draw region DE and stop groove TRe.In the drawings, it is shown by dashed lines that unit area CE and grid are drawn region DE, illustrated by chain-dotted line and stop groove TRe.Unit area CE is arranged on the central part office of semiconductor device.Multiple cell transistors are arranged in the CE of unit area.Each cell transistor has the gate electrode with groove structure.Form source wiring Ms, thus capping unit region CE.Grid is drawn region DE and is arranged on two bights (for example, the both sides of minor face in a side) of touching with same edge joint in four bights of unit area CE and locates.It is the region for the gate electrode GE of cell transistor being drawn out to unit area CE outside that grid is drawn region DE.Gate electrode GE draws at two horizontal directions of figure, and does not draw at longitudinal direction.
,, in the time seeing in horizontal direction, grid is drawn region DE and is inserted in unit area CE and stops between groove TRe.But in the time seeing in longitudinal direction, unit area CE and termination groove TRe are adjacent one another are.
In the time seeing in plane graph, grid wiring Mg forms circlewise, with around unit area CE(source wiring Ms), to draw a part of region DE overlapping with the termination groove extending at longitudinal direction and grid simultaneously.Stop groove TRe and be formed as circlewise that to draw region DE spaced apart with unit area CE and grid, thereby draw region DE around unit area CE and grid.On the termination groove TRe extending at longitudinal direction in the drawings, form grid wiring Mg, so that overlapping with termination groove TRe.
Next, the layout of groove and diffusion layer is described with reference to Fig. 2 A and 2B.Fig. 2 A and 2B are the amplification views of part A in Figure 1B.Although do not illustrate in the drawings,, the part B in Figure 1B is arranged to line and the part A line symmetry based on vertical direction is extended in the drawings.In addition, in Fig. 2 A, the region that wherein forms groove is illustrated by diagonal.
In the CE of unit area, the bar shaped gate trench TRg extending at horizontal direction (directions X) in a large number in the drawings Y-direction is arranged side by side with the pitch (distance L 1 between adjacent trenches) equating.All ends of these a large amount of gate trench TRg are all connected to the gate trench TRg extending at longitudinal direction (Y-direction).Cell transistor is the Vertical Metal Oxide Semiconductor (MOS) with trench gate structure, and gate trench TRg is the groove for embedding electric conductor CD, and electric conductor CD serves as the transistorized gate electrode GE of dispensing unit.
Draw in the DE of region at grid, that extends at horizontal direction (directions X in figure) in a large number draws groove TRd(the 3rd recess) Y-direction is arranged to equate in the drawings pitch (distance L 1 between adjacent trenches) is parallel to each other.This draws in a large number all sides in groove TRd mono-side and is all connected to the gate trench TRg extending at longitudinal direction (Y-direction in figure), and all opposite sides be all connected to extend at longitudinal direction (Y-direction in figure) draw groove TRc.
Draw groove TRd and gate trench TRg continuously and form., draw groove TRd and be connected to gate trench TRg.Drawing groove TRd is the groove for embedding electric conductor CD, and wherein electric conductor CD is drawn out to gate electrode GE the outside of unit area CE.
Stop groove TRe and be arranged in the outer regions EE of semiconductor device, and be arranged to outmost gate trench TRgo, be arranged in outermost one side draw groove TRdo and extend at longitudinal direction draw all L2 spaced apart of groove TRc.Provide and stop groove TRe with by making the insulation thickness on its sidewall discharge electric field strength and prevent dielectric breakdown or the generation of leakage.Distance L 2 equals or is narrower than the placement interval L1 of gate trench TRg.
Gate electrode GE(fills up the electric conductor CD of gate trench TRg inside) and extraction electrode TE(fill up the electric conductor CD that draws groove TRd inside) each other continuously and form.Intercalation electrode VE(fills up and stops the electric conductor CD of groove TRe inside) below describe by being embedded in contact hole CTg() in connector PG and grid wiring Mg be connected to gate electrode GE.In addition the electric conductor CD that, fills up groove TRg, TRd, TRc and TRe inside is the polysilicon for example adulterating.
The gate trench TRg extending at horizontal direction, the gate trench TRg extending at longitudinal direction and the width of drawing groove TRd extending at horizontal direction are all formed as identical width W 1.The groove TRc that draws extending at longitudinal direction has the width W 2 wider than width W 1, to guarantee to be used to form the space (W1<W2) of contact (described below).In addition, stop groove TR3 and also there is the width W 2 wider than width W 1, to guarantee to form the space (W1<W2) of contact (described below).The degree of depth of groove TRg, TRd, TRc and TRe (from the surface of substrate to the distance of the basal surface of groove) is all the almost identical degree of depth.But, in these degree of depth, there is sometimes certain variable quantity.Even in this case, in most of the cases, the degree of depth that stops groove TRe be also more than or equal to the gate trench TRg degree of depth 90% and be less than or equal to 110% of the gate trench TRg degree of depth.
In the superficial layer of unit area CE, form and wherein introduce n +the N-shaped region NR of type dopant.
Draw and in the superficial layer of region DE, form the p-type region PR that wherein introduces p type dopant at grid.Territory, p type island region PR is formed in the superficial layer of outer regions EE.Territory, p type island region PR is formed in the region stopping between groove TRe and the gate trench TRgo of the most close termination groove TRe.But, also in the presumptive area that stops groove TRe outside, form territory, p type island region PR.
Next, the layout of contact hole is described with reference to Fig. 3.Fig. 3 is plane graph and shows the part that wherein forms contact hole by diagonal.The connector of being made up of for example tungsten is buried in contact hole, and electrically contacts and be positioned at the semiconductor layer below insulating interlayer and be positioned at the grid wiring/source wiring on this insulating interlayer.
In the CE of unit area, contact hole CTs horizontal direction extend and gate trench TRg adjacent one another are between along gate trench TRg arrange.In addition, between the termination groove TRe extending at outmost gate trench TRgo with at horizontal direction, form contact hole CTso along gate trench TRg.Draw in the DE of region at grid, contact hole CTd is arranged at horizontal direction and extends and adjacent one another are drawing between groove TRd.In addition, contact hole CTdo is formed between the outmost termination groove Tre that draws groove TRdo and extend at horizontal direction.Contact hole CTd and CTdo are all arranged to be biased to unit area CE mono-side (, away from grid wiring Mg a side).By this way, can fully guarantee the distance between grid wiring Mg and source wiring Ms.
Contact hole CTg(the first contact) be arranged at longitudinal direction extend drawing on groove TRc.Contact hole CTe(the second contact) be arranged on the termination groove TRe extending at longitudinal direction.
Next, the cross-sectional structure of semiconductor device is described with reference to Fig. 4 A and 4B.Fig. 4 A and 4B are respectively the cross-sectional views of obtaining along line X-X and the Y-Y of Fig. 3.The cross-sectional structure that, Fig. 4 A shows grid and draws region DE and outer regions EE.Fig. 4 B shows the cross-sectional structure of unit area CE and outer regions EE.
Go out as shown in Figure 4 B, substrate S UB has by n +the upper n of the substrate body SB that type silicon is made and substrate body SB -the epitaxial loayer EP of type.Substrate body SB is body silicon substrate.Epitaxial loayer EP is epitaxially grown silicon layer on substrate body SB.
Gate trench TRg is set in the CE of unit area.The upper portion side wall of gate trench TRg is coated with gate insulating film GI(film thickness: t1).The lower sides of gate trench TRg is coated with first bottom dielectric film FIL1(film thickness: the t2 thicker than gate insulating film GI) (t1<t2).The electric conductor CD being made up of the polysilicon that adulterating is buried in gate trench TRg.Electric conductor CD serves as gate electrode GE.The lower end of gate insulating film GI is connected to the upper end of the first bottom dielectric film FIL1.
In the region adjacent with gate trench TRg of substrate S UB, form respectively PRHenXing region, the p-type region NR that each all has desired depth.P-type region PR serves as basal region, and N-shaped region NR serves as source region.But, in the p-type region PR between outermost peripheral gates groove TRgo and termination groove TRe, do not form N-shaped region NR.
Contact hole CTs passes insulating interlayer IL2, dielectric film IL1 and N-shaped region NR at thickness direction, and penetrates into the centre of p-type region PR.Contact hole CTso passes insulating interlayer IL2 and dielectric film IL1 at thickness direction, and is formed into the centre of p-type region PR.The connector PG being made up of tungsten is embedded in contact hole CTs and CTso by barrier metal BR.Connector PG is electrically connected to source wiring Ms PRHenXing region, p-type region NR.
Stopping groove TRe is arranged in outer regions EE.The depth d 2 that stops groove TRe is identical with the depth d 1 of gate trench TRg or slightly dark (d1 ≈ d2) almost.Described at Fig. 2 A and 2B, the width W 2 that stops groove TRe is greater than the width W 1(W1<W2 of gate trench TRg).The upper portion side wall that stops groove TRe is coated with upper portion insulating film FIH, and lower sides is coated with the second bottom dielectric film FIL2.In this embodiment, the thickness t 4 of upper portion insulating film FIH almost with the thickness t 3 identical (t3=t4) of the second bottom dielectric film FIL2.In addition, here, the thickness t 2 of the first bottom dielectric film FIL1 of the lower sides of the thickness t 3 of the second bottom dielectric film FIL2 and cover gate groove TRg is identical thickness (t3=t2).But, t3 also can for be more than or equal to t2 95% and be less than or equal to 105% of t2.
So outmost gate trench TRgo and the distance L 2 stopping between groove TRe are equal to or less than the distance L 1(L2≤L1 between gate trench TRg and TRgo adjacent one another are).
Go out as shown in Figure 4 A, draw groove TRd and be arranged on grid and draw in the DE of region.The degree of depth of drawing groove TRd is the degree of depth identical with the depth d 1 of gate trench TRg.As mentioned above, be similar to and stop groove TRe, the width W 2 of drawing groove TRd is greater than the width W 1(W1<W2 of gate trench TRg).The upper portion side wall of drawing groove TRd is coated with gate insulating film GI(film thickness: t1).The lower sides of drawing groove TRd is coated with dielectric film FIL3(film thickness: t2), wherein dielectric film FIL3 has and the first bottom dielectric film FIL1(film thickness: t2 on the lower sides of gate trench TRg) identical thickness.The electric conductor CD being made up of the polysilicon that adulterating is buried in and draws in groove TRd.This electric conductor CD is the extraction electrode TE of electrical connection grid electrode GE and grid wiring Mg.
In addition, also in the adjacent region with drawing groove TRd of substrate S UB, form p-type region PR.
Contact hole CTd is set drawing on groove TRd, and is stopping, on groove TRe, contact hole CTe is set.Contact hole CTd and CTe pass insulating interlayer IL2.As mentioned above, the connector PG being made up of tungsten is embedded in contact hole CTd and CTe through barrier metal BR.Connector PG is electrically connected to grid wiring Mg being buried in the extraction electrode TE drawing in groove TRd and being buried in the intercalation electrode VE stopping in groove TRe.
On the surface of substrate, form dielectric film IL1 and insulating interlayer IL2.In addition, on insulating interlayer IL2, form grid wiring Mg.In addition, on the rear surface of substrate S UB, form back electrode BE.Back electrode BE serves as drain electrode.
In addition, in shown example, the border in gate trench TRg sidewall between gate insulating film GI and the first bottom dielectric film FIL1 is arranged in epitaxial loayer EP in the figure.In addition, the boundary in termination groove TRe sidewall between the second bottom dielectric film FIL2 and upper portion insulating film FIH forms step, and this border is arranged in epitaxial loayer EP.But, also have a kind of situation to be, wherein between the second bottom dielectric film FIL2 and upper portion insulating film FIH, there is no border.
According to above-described semiconductor device, the upper portion insulating film that is positioned at termination groove TRe side wall upper part place is thicker than the gate insulating film GI that is positioned at gate trench TRg side wall upper part.So, even if large voltage is applied to back electrode BE and near therefore stop the sidewall of groove TRe electric field strength increases, also can suppress to stop the generation of dielectric breakdown in groove TRe.Therefore, the reliability of semiconductor device is improved.
In addition, by the thickness that stops the second bottom dielectric film FIL2 of groove TRe and the first bottom dielectric film FIL1 of gate trench TRg is equal to each other, and the degree of depth that stops groove TRe and gate trench TRg is equal to each other, can stop forming below groove with gate trench TRg below the similar Electric Field Distribution of Electric Field Distribution.Also, can below all termination groove TRe and longitudinal gate trench TRg arranging, form more uniform Electric Field Distribution, and therefore can suppress the generation of the abnormal conditions that withstand voltage is low.
Here, by research by making to stop the degree of depth of groove TRe and gate trench TRg the obtained effect that is equal to each other.The depletion layer and the avalanche current path that are applied to the state between source electrode and drain electrode in high voltage have been shown in Figure 13 A and 13B.Figure 13 A shows the result in the case of the depth as shallow of the depth ratio gate trench TRg of termination groove TRe.Figure 13 B shows the result in the case of the degree of depth of termination groove TRe is identical with the degree of depth of gate trench TRg.
In Figure 13 A, stopping groove TRe(is rightmost groove in the figure) depth ratio gate trench TRg(be the groove except termination groove in the figure) depth as shallow.Therefore, the Electric Field Distribution between gate trench TRg and gate trench TRg and gate trench TRg and the Electric Field Distribution stopping between groove TRe differ from one another, and therefore between gate trench TRg and termination groove TRe, the abnormal conditions that withstand voltage is low occur.,, even improve withstand voltage by the sidewall of the dielectric film covering termination groove TRe with thick, still, because Electric Field Distribution is inhomogeneous, therefore between gate trench TRg and termination groove TRe, also can puncture.
On the other hand, in Figure 13 B, stopping groove TRe(is rightmost groove in the figure) the degree of depth be the groove except termination groove in the figure with gate trench TRg() the degree of depth identical.Therefore, Electric Field Distribution between gate trench TRg and gate trench TRg and gate trench TRg and the Electric Field Distribution stopping between groove TRe become substantially even, and therefore between gate trench TRg and termination groove TRe, do not have the abnormal conditions that withstand voltage is low.
In the Vertical Metal Oxide Semiconductor field-effect transistor (MOSFET) having at above-mentioned semiconductor device, if apply predetermined voltage between gate electrode GE and source wiring Ms, make gate electrode GE there is high potential, in the p-type region PR towards gate electrode GE, form raceway groove.So electric current flows between drain electrode and source electrode by this raceway groove.
Next, with reference to figure 5A to 10C, the method for manufacturing above-mentioned semiconductor device is described.Fig. 5 A to 10C is all corresponding near viewgraph of cross-section Fig. 3 line Y-Y.In addition, near viewgraph of cross-section Fig. 3 line X-X will not illustrate and describe.But, in the time forming each structure of gate trench TRg and inside thereof, form simultaneously and draw groove TRdo and inner each structure thereof.In addition, after forming contact hole CTs(, describe) process in, contact hole CTd draws on groove TRd in formation, and contact hole CTe is formed on and stops on groove TRe.
First, as shown in Figure 5A, preparing substrate SUB, wherein at n +the upper n that forms of type Semiconductor substrate main body SB -type epitaxial loayer EP.Next, on the surface of substrate S UB, form hard mask MK1, together with ground floor LY1 is laminated to second layer LY2 in hard mask MK1.Ground floor LY1 is for example silicon oxide film, and second layer LY2 is made up of for example silicon nitride film.Hard mask MK1 should form in the region of groove therein has opening.Next, by utilizing hard mask MK1 as anisotropically etching n of mask -type epitaxial loayer EP forms upper groove Tgh and upper groove Teh simultaneously.Due to by the formation of lower channel of describing subsequently, upper groove Tgh and upper groove Teh become respectively gate trench TRg and stop groove TRe.Here, the width W 2 of upper groove Teh is wider than the width W of upper groove Tgh 1.In addition, the distance of the depth d 4(of upper groove Teh from substrate surface to trench bottom surfaces) almost identical with the depth d 3 of upper groove Tgh.But because groove width is wide, therefore the degree of depth becomes slightly dark (d4 >=d3).In addition, the distance L 2 between upper groove Teh and upper groove Tgh almost with upper groove Tgh and Tgh between distance L 1 identical or slightly narrow (L2≤L1).
In addition,, in order to make embeddability better, preferably on the side surface of upper groove Tgh and Teh, provide the inclination angle of about 85 °.For example comprise that by utilization the reacting gas CBrF3 of carbon carries out etching this inclination angle is provided.In such method, carbon is synthesis of organic substance matter (being commonly called as: accumulate (depot)) in plasma, and it adheres to the side surface of groove and serves as etching mask.By this way, carry out along with etched, on side surface, form inclination angle.So if the carbon content in reacting gas is large, inclination angle becomes large.
In addition the method that, inclination angle is set is not limited to this.Can provide inclination angle by for example a kind of so method, wherein, after forming groove opening, carry out isotropic etching, thereby make to retreat (retreat) near the peripheral boundary part of groove opening of etching mask, and subsequently by utilizing chemical drying method etching (CDE) to carry out etching.
Next, go out as shown in Figure 5 B, by using chemical vapor deposition (CVD) method, on the whole surface of substrate, comprise the inner surface of upper groove Tgh and Teh, for example form diaphragm PL(, nitride film (SiN)).In addition,, in figure in this drawing or below, second layer LY2 is shown as a part of diaphragm PL.
Next, go out as shown in Figure 5 C the diaphragm PL on the diaphragm PL on the basal surface of use anisotropic etching removal upper groove Tgh and the basal surface of upper groove Teh.
Next, shown in Fig. 6 A, by utilizing diaphragm PL as further etching n anisotropically of mask -type epitaxial loayer EP forms lower channel Tgl and lower channel Tel simultaneously.With which, form gate trench TRg simultaneously and stop groove TRe., the depth d 1 of gate trench TRg becomes almost identical with the depth d 2 that the stops groove TRe degree of depth.But because width is wide, therefore the degree of depth becomes slightly dark (d1≤d2).In addition,, in order to make embeddability better, the inclination angle of about 85 ° is also set on the side surface of lower channel Tgl and Tel.The method that inclination angle is set is identical with method recited above.
Next, shown in Fig. 6 B, utilize diaphragm PL as mask, carry out by the oxidation of local oxidation of silicon (LOCOS).By this way, on the inwall of lower channel Tgl and Tel, form thick insulating film SI.
Next,, shown in Fig. 6 C, by using CVD method, on the substrate surface that comprises the inner surface of gate trench TRg and the inner surface of termination groove TRe, form CVD dielectric film CVI.
Next, go out as shown in Figure 7A, on substrate, form resist mask MK2.Resist mask MK2 has opening in the region that stops groove TRe.
Next, shown in Fig. 7 B, utilize resist mask MK2 as mask, carry out wet etching.By this way, remove the CVD dielectric film CVI on the inner surface that stops groove TRe.
Next,, shown in Fig. 7 C, remove resist mask MK2.
Next, go out as shown in Figure 8 A, using CVD dielectric film CVI as mask, remove the diaphragm PL on the inner surface that stops groove TRe by hot phosphoric acid.Due to compared with resist mask, CVD dielectric film CVI has outstanding acid resistance, and therefore CVD dielectric film CVI is suitable as the mask of this process.
Next,, shown in Fig. 8 B, CVD dielectric film CVI and dielectric film SI are passed wet etching and remove.By this way, lower channel Tgl and Tel extend at horizontal direction.Can, by changing the film thickness of dielectric film SI, extension yardstick be arranged to any yardstick.In addition, in lower channel Tgl and Tel, in each and upper groove Tgh and Teh, the boundary between each forms step ST.
Next, shown in Fig. 8 C, utilize diaphragm PL as mask, carry out LOCOS oxidation.By this way, form the first bottom dielectric film FIL1 at the bottom place of the inwall of gate trench TRg, and form the second bottom dielectric film FIL2 and upper portion insulating film FIH on the inwall that stops groove TRe.Here, the thickness t 4 of the thickness t 3 of the second bottom dielectric film FIL2 of the thickness t 2 of the first bottom dielectric film FIL1 of gate trench TRg, termination groove TRe and the upper portion insulating film FIH of termination groove TRe, is all identical thickness (t2=t3=t4).,, in this process, almost do not form the border between the second bottom dielectric film FIL2 and upper portion insulating film FIH.In addition, thickness t 4 can be more than or equal to thickness t 3 95% and be less than or equal to 105% of thickness t 3.
Next,, shown in Fig. 9 A, by utilizing hot phosphoric acid to carry out etching, remove diaphragm PL.
Next,, shown in Fig. 9 B, by using thermal oxidation process, in the upper inside wall of gate trench TRg, form gate insulating film GI.Now, the first bottom dielectric film FIL1, the second bottom dielectric film FIL2 and upper portion insulating film FIH are also through oxidated and therefore become slightly thick.
Next, go out as shown in Figure 9 C, after the electric conductor CD that deposit is for example made up of the polysilicon that adulterating on the whole surface of substrate, execution is eat-back.By this way, in gate trench TRg, form gate electrode GE, and form intercalation electrode VE in termination groove TRe.In addition,, although do not illustrate in figure, also in groove TRdo, form extraction electrode TE drawing.
Next, go out as shown in FIG. 10A, by utilizing the ion implantation technology of corrosion-resisting pattern, p-type impurity and N-shaped impurity are incorporated into respectively in predetermined region to the predetermined degree of depth.By this way, form PRHenXing region, p-type region NR.
Next, go out as shown in Figure 10 B, on substrate, form insulating interlayer IR.
Next,, shown in Figure 10 C, form contact hole CTs.Contact hole CTs is through insulating interlayer IR, ground floor LY1(dielectric film IL1) and N-shaped region NR, and half way (halfway) degree of depth of arrival p-type region PR.Afterwards, form the barrier metal BR for example being made by titanium/titanium nitride on whole surface after, in contact hole CTs, form the connector PG for example being made by tungsten.
Next, by using injection method or method of evaporating to form conducting film, and then optionally remove this conducting film.By this way, on the surface of substrate, form source wiring Ms and grid wiring Mg.Afterwards, form passivating film (not shown) on these wirings after, in passivating film (not shown), be formed for the opening portion OPs and the OPg that engage.Finally, on the rear surface of substrate, form back electrode BE, thereby complete the semiconductor device shown in Figure 1A to 4B.
According to above-mentioned manufacture method for semiconductor, because gate trench TRg and termination groove TRe form simultaneously, therefore the two can form with the almost identical degree of depth.In addition, because the second bottom dielectric film FIL2 on the first bottom dielectric film FIL1 of gate trench TRg and the inwall of termination groove TRe forms simultaneously, therefore the two can form with almost identical thickness.
In addition, in the above description, vertical-type transistor is n channel transistor.But vertical-type transistor can be also p channel MOS.
(the second embodiment)
Figure 11 is the viewgraph of cross-section illustrating according to the configuration of the semiconductor device of the second embodiment.Except the thickness t 4 of upper portion insulating film FIH is thicker and than the thickness t 3 thin (t1<t4<t3) of the second bottom dielectric film FIL2 than the thickness t of gate insulating film GI 1, have and the configuration identical according to the semiconductor device of the first embodiment according to the semiconductor device of this embodiment.
In order to improve the resistance to dielectric breakdown of dielectric film, the thickness of the dielectric film (upper portion insulating film FIH and the second bottom dielectric film FIL2) of the inwall of covering termination groove TRe is more thick better.But, do not increase outmost gate trench TRgo if the thickness of dielectric film is more and more thicker and stop the distance L 2 between groove TRe, process allowance (process margin) LM that forms contact hole CTso reduces.
On the contrary, in this embodiment, with regard to the dielectric breakdown characteristic of dielectric film, the thickness t 3 of the second bottom dielectric film FIL2 can be made enough thick.In addition, the thickness that the thickness t 4 of upper portion insulating film FIH can be arranged to realize withstand voltage and guarantee process allowance LM.
Hereinafter, with reference to Figure 12 A to 12C, the example of manufacturing the method for semiconductor device according to the second embodiment is described.
According to the method for the manufacture semiconductor device of this embodiment have with at the manufacturing process identical according to Fig. 8 A describing in the manufacture method of the first embodiment, and its description will not repeat.Figure 12 A is corresponding to Fig. 8 A.
Shown in Figure 12 A, utilize CVD dielectric film CVI as mask, remove the diaphragm PL on the inner surface that stops groove TRe by hot phosphoric acid.
Next, go out as shown in Figure 12B, utilize diaphragm PL as mask, carry out LOCOS oxidation.By this way, in the upper portion side wall that stops groove TRe, form upper portion insulating film FIH.Now, due to the protected film PL of upper portion side wall of gate trench TRg and the coverage of the laminated film of CVD dielectric film, therefore oxidation is not proceeded.In addition, because the first bottom dielectric film FIL1 of gate trench TRg is thick with the second bottom dielectric film FIL2 that stops groove TRe, therefore, than the thickness of upper portion insulating film FIH, the recruitment of thickness is little.
Next,, shown in Figure 12 C, be removed CVD dielectric film by wet etching.Now, the thickness of the bottom dielectric film FIL of gate trench TRg and termination groove TRe is also by partially-etched.Afterwards, remove diaphragm PL by hot phosphoric acid.
By control LOCOS oxidizing condition in the process of Figure 12 B, in the step of Figure 12 C, can make thickness, the thickness of the second bottom dielectric film FIL2 of termination groove TRe and the thickness of the upper portion insulating film FIH of termination groove TRe of the first bottom dielectric film FIL1 of gate trench TRg is respectively predetermined thickness t 2, t3 and t4.But, aspect the resistance to dielectric breakdown of dielectric film, make the thickness t 4 of the upper portion insulating film FIH that stops groove TRe thicker than the thickness t of gate insulating film GI 1.
Because subsequent technique process is followed the manufacturing process of Fig. 9 C to 10C in the first embodiment, therefore will not repeat its description.
In addition, by this embodiment, can obtain and effect identical in the first embodiment.In addition, can make the thickness t 3 of thickness t 4 to the second bottom dielectric film FIL2 of the upper portion insulating film FIH that stops groove TRe thin.By this way, even if do not change the thickness of the first bottom dielectric film FIL1 and the second bottom dielectric film FIL2, also the thickness t 4 of upper portion insulating film FIH can be arranged to realize and guarantee and the thickness of process allowance LM and withstand voltage.
Specifically describe based on above embodiment the present invention that inventor proposes.But, the invention is not restricted to above-described embodiment, and can carry out various amendments and not deviate from purport of the present invention.
Obviously, the invention is not restricted to above embodiment, and can modifications and variations and do not deviate from scope of the present invention and spirit.

Claims (6)

1. a semiconductor device, comprising:
The drain electrode layer of the first conduction type;
The low concentration impurity layer of the first conduction type, it is formed on drain electrode layer and has the impurity concentration lower than drain electrode layer;
The basalis of the second conduction type, it is positioned on low concentration impurity layer;
Gate insulating film, is formed on the top place of the side surface of the first recess forming in basalis, and wherein said the first recess has the bottom that is arranged in low concentration impurity layer;
The first bottom dielectric film, is formed on the basal surface of the first recess and the bottom of side surface, than gate insulator thickness, and is connected to gate insulating film;
Gate electrode, is embedded in the first recess;
The source layer of the first conduction type, it is formed in basalis, more shallow than basalis, and position is close to the first recess in the time seeing in plane graph;
The second bottom dielectric film, is formed on the basal surface of the second recess and the bottom of side surface, and in the time seeing in plane graph, the second recess is around the first recess;
Upper portion insulating film, be formed on the second recess side surface top place and be connected to the second bottom dielectric film; And
Intercalation electrode, is embedded in the second recess,
Wherein the degree of depth of the second recess be more than or equal to the first recess depths 90% and be less than or equal to 110% of the first recess depths,
The thickness of the second bottom dielectric film be more than or equal to the first bottom insulator film thickness 95% and be less than or equal to 105% of the first bottom insulator film thickness, and
Upper portion insulating film is than gate insulator thickness.
2. semiconductor device as claimed in claim 1, wherein the thickness of upper portion insulating film be more than or equal to the second bottom insulator film thickness 95% and be less than or equal to 105% of the second bottom insulator film thickness.
3. semiconductor device as claimed in claim 1, is wherein formed parallel to each other multiple the first recesses,
In each in described multiple the first recesses, form described gate insulating film, the first bottom dielectric film and gate electrode, and
Distance between described multiple the first recess equals the distance between the first recess and second recess of the most close the second recess.
4. semiconductor device as claimed in claim 1, also comprises:
The 3rd recess, is connected to the first recess;
Extraction electrode, is formed in the 3rd recess and is connected to gate electrode;
The first contact, is connected to extraction electrode; And
The second contact, is connected to intercalation electrode,
Wherein the first bottom dielectric film is formed on the bottom place of the 3rd recess, and forms at the top place of the 3rd recess the dielectric film having with gate insulating film same thickness, and
Upper portion insulating film is thinner than the second bottom dielectric film.
5. a method of manufacturing semiconductor device, comprising:
In the first surface of the substrate of lamination, form the first recess and the second recess around the first recess, and cover the top of side surface of the first recess and the first surface of the substrate of lamination with diaphragm, wherein the Semiconductor substrate of the first conduction type is laminated in the substrate of this lamination with the semiconductor layer of first conduction type with the impurity concentration lower than this Semiconductor substrate;
By come thermal oxidation the first recess and the second recess using diaphragm as mask, form the second dielectric film on side surface and the basal surface that is positioned at the bottom of side surface and first dielectric film of bottom surface of the first recess and is positioned at the second recess;
Remove diaphragm;
By thermal oxidation the first recess, form than the first dielectric film and the thin gate insulating film of the second dielectric film at the top place of the side surface of the first recess; And
In the first recess, embed gate electrode and form intercalation electrode in the second recess.
6. a method of manufacturing semiconductor device, comprising:
In the first surface of the substrate of lamination, form the first recess and the second recess around the first recess, and cover top, the top of side surface of the second recess and the first surface of the substrate of lamination of the side surface of the first recess with diaphragm, wherein the Semiconductor substrate of the first conduction type is laminated in this laminated substrates with the semiconductor layer of first conduction type with the impurity concentration lower than this Semiconductor substrate;
By using diaphragm as mask thermal oxidation the first recess and the second recess, form the bottom of side surface and the first dielectric film of bottom surface that is positioned at the first recess and the bottom of side surface and the second dielectric film of bottom surface that is positioned at the second recess;
Removal is positioned at the diaphragm at the top place of the side surface of the second recess;
By come thermal oxidation the first recess and the second recess using diaphragm as mask, form three dielectric film thinner than the second dielectric film at the top place of the side surface of the second recess;
Remove diaphragm;
By thermal oxidation the first recess, form the thin gate insulating film of ratio the 3rd dielectric film at the top place of the side surface of the first recess; And
In the first recess, embed gate electrode and form intercalation electrode in the second recess.
CN201410015627.4A 2013-01-31 2014-01-14 Semiconductor device and the method for manufacturing semiconductor device Expired - Fee Related CN103972289B (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106449753A (en) * 2016-07-14 2017-02-22 中航（重庆）微电子有限公司 Low on-state resistance groove power MOS (Metal Oxide Semiconductor) device structure and fabrication method thereof
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CN107591440A (en) * 2017-08-31 2018-01-16 上海华虹宏力半导体制造有限公司 Groove grid super node device and its manufacture method
CN107706228A (en) * 2017-08-31 2018-02-16 上海华虹宏力半导体制造有限公司 Groove grid super node device and its manufacture method
CN109891594A (en) * 2016-11-04 2019-06-14 丰田自动车株式会社 Semiconductor devices

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8896047B2 (en) * 2012-05-22 2014-11-25 Infineon Technologies Ag Termination arrangement for vertical MOSFET
DE102014112338A1 (en) * 2014-08-28 2016-03-03 Infineon Technologies Austria Ag Semiconductor device and method for manufacturing a semiconductor device
DE102014117780B4 (en) * 2014-12-03 2018-06-21 Infineon Technologies Ag Semiconductor device with a trench electrode and method of manufacture
DE102014119465B3 (en) 2014-12-22 2016-05-25 Infineon Technologies Ag SEMICONDUCTOR DEVICE WITH STRIPULAR TRENCHGATE STRUCTURES, TRANSISTORMESIS AND DIODE MESAS
JP6406454B2 (en) * 2015-07-07 2018-10-17 富士電機株式会社 Semiconductor device
JP6739372B2 (en) 2017-02-21 2020-08-12 株式会社東芝 Semiconductor device
CN109326595B (en) * 2017-07-31 2021-03-09 联华电子股份有限公司 Semiconductor element and manufacturing method thereof
DE102018103973B4 (en) 2018-02-22 2020-12-03 Infineon Technologies Ag SILICON CARBIDE SEMICONDUCTOR COMPONENT
JP6966377B2 (en) 2018-04-19 2021-11-17 ルネサスエレクトロニクス株式会社 Semiconductor devices and their manufacturing methods
DE102019111308A1 (en) 2018-05-07 2019-11-07 Infineon Technologies Ag SILICON CARBIDE SEMICONDUCTOR ELEMENT
DE102018124740A1 (en) 2018-10-08 2020-04-09 Infineon Technologies Ag SEMICONDUCTOR COMPONENT WITH A SIC SEMICONDUCTOR BODY AND METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT
US10903322B2 (en) 2018-11-16 2021-01-26 Infineon Technologies Ag SiC power semiconductor device with integrated body diode
US10985248B2 (en) 2018-11-16 2021-04-20 Infineon Technologies Ag SiC power semiconductor device with integrated Schottky junction
US10586845B1 (en) 2018-11-16 2020-03-10 Infineon Technologies Ag SiC trench transistor device and methods of manufacturing thereof
JP2022093130A (en) 2020-12-11 2022-06-23 株式会社東芝 Semiconductor device, inverter circuit, drive device, vehicle, and elevator
CN114420564A (en) * 2022-03-28 2022-04-29 深圳市美浦森半导体有限公司 MOS (Metal oxide semiconductor) device with separated gate groove and manufacturing method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101542731A (en) * 2005-05-26 2009-09-23 飞兆半导体公司 Trench-gate field effect transistors and methods of forming the same
US20100219461A1 (en) * 2008-08-06 2010-09-02 Mark Rinehimer Structure With PN Clamp Regions Under Trenches
CN102017103A (en) * 2006-01-05 2011-04-13 飞兆半导体公司 Power device utilizing chemical mechanical planarization
CN102246306A (en) * 2008-12-08 2011-11-16 飞兆半导体公司 Trench-based power semiconductor devices with increased breakdown voltage characteristics

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3082522B2 (en) * 1993-07-27 2000-08-28 日産自動車株式会社 Insulated electrode and method of manufacturing the same
GB9917099D0 (en) * 1999-07-22 1999-09-22 Koninkl Philips Electronics Nv Cellular trench-gate field-effect transistors
JP3709814B2 (en) 2001-01-24 2005-10-26 株式会社豊田中央研究所 Semiconductor device and manufacturing method thereof
TW582087B (en) * 2003-04-09 2004-04-01 Nanya Technology Corp Method of forming bottle trench
GB0405325D0 (en) 2004-03-10 2004-04-21 Koninkl Philips Electronics Nv Trench-gate transistors and their manufacture
JP2006344760A (en) * 2005-06-08 2006-12-21 Sharp Corp Trench type mosfet and its fabrication process
KR100731141B1 (en) * 2005-12-29 2007-06-22 동부일렉트로닉스 주식회사 Semiconductor device and method for fabricating the same
US7718505B2 (en) * 2007-06-22 2010-05-18 Infineon Technologies Austria Ag Method of forming a semiconductor structure comprising insulating layers with different thicknesses
US9484451B2 (en) 2007-10-05 2016-11-01 Vishay-Siliconix MOSFET active area and edge termination area charge balance
JP5633992B2 (en) 2010-06-11 2014-12-03 トヨタ自動車株式会社 Semiconductor device and manufacturing method of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101542731A (en) * 2005-05-26 2009-09-23 飞兆半导体公司 Trench-gate field effect transistors and methods of forming the same
CN102017103A (en) * 2006-01-05 2011-04-13 飞兆半导体公司 Power device utilizing chemical mechanical planarization
US20100219461A1 (en) * 2008-08-06 2010-09-02 Mark Rinehimer Structure With PN Clamp Regions Under Trenches
CN102246306A (en) * 2008-12-08 2011-11-16 飞兆半导体公司 Trench-based power semiconductor devices with increased breakdown voltage characteristics

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106469672A (en) * 2015-08-10 2017-03-01 瑞萨电子株式会社 The manufacture method of semiconductor device
CN106469672B (en) * 2015-08-10 2021-12-24 瑞萨电子株式会社 Method for manufacturing semiconductor device
CN106449753A (en) * 2016-07-14 2017-02-22 中航（重庆）微电子有限公司 Low on-state resistance groove power MOS (Metal Oxide Semiconductor) device structure and fabrication method thereof
CN109891594A (en) * 2016-11-04 2019-06-14 丰田自动车株式会社 Semiconductor devices
CN106531809A (en) * 2016-11-15 2017-03-22 中航（重庆）微电子有限公司 Deep trench power MOS device structure and method for producing same
CN106531809B (en) * 2016-11-15 2019-12-17 华润微电子（重庆）有限公司 deep trench power MOS device structure and preparation method thereof
CN107591440A (en) * 2017-08-31 2018-01-16 上海华虹宏力半导体制造有限公司 Groove grid super node device and its manufacture method
CN107706228A (en) * 2017-08-31 2018-02-16 上海华虹宏力半导体制造有限公司 Groove grid super node device and its manufacture method

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