CN107591440A - Groove grid super node device and its manufacture method - Google Patents
Groove grid super node device and its manufacture method Download PDFInfo
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- CN107591440A CN107591440A CN201710768048.0A CN201710768048A CN107591440A CN 107591440 A CN107591440 A CN 107591440A CN 201710768048 A CN201710768048 A CN 201710768048A CN 107591440 A CN107591440 A CN 107591440A
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Abstract
The invention discloses a kind of groove grid super node device, gate groove extends to formation grid end cephalic groove groove in transition region on along its length；The side of gate groove top section formed with gate oxide, side bottom and lower surface formed with the first thicker oxide layer of thickness；The side of grid end cephalic groove groove and lower surface are also formed with the first oxide layer；Filled in gate groove and grid are filled in polysilicon gate and grid end cephalic groove groove draw that polysilicon is in contact and the grid in grid end cephalic groove groove are drawn polysilicon and also extended up to terminal protection area side and get over the ledge structure that is formed by field oxygen layer and the grid positioned at field oxygen layer grid draw the top of polysilicon and form contact hole and be connected to the grid being made up of front metal layer.The invention also discloses a kind of manufacture method of groove grid super node device.The present invention can improve the reliability and EAS abilities of grid simultaneously, so as to improve the robustness of device by forming the first thicker oxide layer of thickness in grid deriving structure region.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing field, more particularly to a kind of groove grid super node device；The present invention
Further relate to a kind of manufacture method of groove grid super node device.
Background technology
Superjunction devices such as super node MOSFET uses new structure of voltage-sustaining layer, utilizes a series of semiconductor P being alternately arranged
The super-junction structure of type thin layer and N-type thin layer composition in the off state at the lower voltage just consumes p-type thin layer and N-type thin layer
To the greatest extent, realize that electric charge mutually compensates for, so that p-type thin layer and N-type thin layer can realize high breakdown voltage under high-dopant concentration, from
And obtaining low on-resistance and high breakdown reverse voltage (BV) simultaneously, i.e., super node MOSFET is thin using PN i.e. p-type thin layer and N-type
Less electric conduction is kept again while reducing surface field (Resurf) technology inside layer charge balance to lift device BV
Resistance.
Superjunction devices generally includes electric charge flow region, transition region and terminal protection area, and electric charge flow region is also referred to as active area
(Active area), electric charge flow region are provided with the cellular construction of superjunction devices such as super node MOSFET, can be formed during break-over of device
Raceway groove turns on the source and drain of super node MOSFET.Electric charge flowing area is located at the intermediate region of superjunction devices；Terminal protection area is formed at
The week side of boss of the electric charge flow region, transition region is between the terminal protection area and the electric charge flow region.
Groove grid super node device and planar gate superjunction devices, wherein groove are divided into according to the grid structure difference of superjunction devices
The polysilicon gate of the grid structure of grid superjunction devices is formed in groove, and groove corresponding to grid is gate groove in addition, in grid ditch
The side of groove is then formed with relatively thin gate oxide.The depth of gate groove needs the depth for being more than the channel region being made up of p-well.With
The size reduction of device, the width of gate groove is typically small and the thinner thickness of gate oxide, typically not directly from groove
The top of grid forms contact hole and polysilicon gate is connected to the grid being made up of front metal layer；But moving area positioned at electric charge stream
The week side of boss transition region semiconductor substrate surface formed and gate groove in polysilicon gate contact connection grid draw polysilicon,
Grid is connected to by drawing polysilicon surface formation contact hole in grid.Often it was formed from transition region formed with one
The ledge structure of the field oxygen composition crossed in area and terminal protection area, grid, which draw polysilicon, to be needed to get over ledge structure and in Step-edge Junction
The outside of structure forms the contact hole for being connected to grid.
As shown in figure 1, it is the structural representation of existing groove grid super node device；Without detailed display electric charge flowing in Fig. 1
The structure chart of each device cell in area, the structural representation being merely displayed near transition region, on the surface of Semiconductor substrate 101
Formed with super-junction structure, N-type epitaxy layer generally is also formed with the surface of Semiconductor substrate 101, super-junction structure is formed at outside N-type
Prolong in layer.Formed with p-type ring 102 in transition region, p-type ring 102 can cover more than one p-type post, be along superjunction knot in Fig. 1
The section of the length direction of structure, therefore the structure that p-type post and N-type post are alternately arranged is not shown.Trench gate in electric charge flow region by
Gate oxide 104 between the polysilicon gate 105 and polysilicon gate 105 and gate groove that are formed in gate groove forms.Grid are drawn
Polysilicon 105a is located at the surface that Semiconductor substrate 101 is the Semiconductor substrate 101 formed with super-junction structure, and grid draw polysilicon
The surface of field oxygen layer 103 that 105a can be connected with polysilicon gate 105 and extend in terminal protection area.Interlayer film 106 covers
In the front of Semiconductor substrate 101, contact hole 107 is through interlayer film 106 and is formed respectively with top by front metal layer 108
Source electrode connected with grid, Fig. 1 only show the contact hole 107 connected with grid.Contact hole corresponding to source electrode is located at electric charge stream
The top of source region in dynamic area.Contact hole 107 corresponding to grid draws polysilicon positioned at the grid for extending the surface of oxygen layer 103 of showing up
105a top.
As can be seen that grid draw polysilicon 105a in the junction with polysilicon gate 105 and get over an oxygen layer 103 and formed
Ledge structure at all there is polysilicon ledge structure, along with the bottom that grid draw polysilicon 105a is also to use relatively thin grid
The epitaxial layer of oxide layer and bottom is isolated, so, grid draw polysilicon 105a's and polysilicon gate 105 in gate groove
Weak spot (weak point) all be present in the opening position and the opening position of the ledge structure of oxygen layer on the scene 103 being connected.Fig. 2 is
The photo of structure shown in Fig. 1, weak spot particular location as shown in the dotted line circle 201,202 and 203 in Fig. 2 pass through prolonged
After operating pressure (Stress), these weak spots are easily realized, so as to which the robustness of grid can be caused to reduce.As shown in figure 3, it is figure
The grid weakness point failure photo of the opening position of dotted line circle 201 in 2；By field time operating pressure, grid of the dotted line circle 201 at climbing
Aoxidize fault rupture.
In addition, failed except the weak spot opening position in grid deriving structure recited above easily produces grid oxygen fracture
Outside, when superjunction devices is applied, pass of single pulse avalanche breakdown energy (EAS) ability as the robustness (robust) of device
One of key energy also extremely important, the device of EAS abilities, is tended to fail in use, and even aircraft bombing is produced when serious
Phenomenon.So the lifting of EAS abilities, very key for the durability of lifting superjunction devices.
The improvement of EAS abilities, key are the conducting for delaying parasitic triode, and parasitic triode is superjunction devices such as superjunction
The N+ district's groups of MOSFET element into source region, p-well composition the drift region that is formed with N-type post of channel region and N+ district's groups into leakage
Area forms triode, and channel region is as base, and when base electric current is larger, parasitic triode will turn on.
Because parasitic triode will turn on when the base electric current of parasitic triode is larger, so as to reduce EAS abilities, so
In order to improve the EAS abilities of device, it usually needs guiding base of the avalanche current path away from parasitic triode, so as to reduce
The base electric current of parasitic triode；In addition, existing superjunction devices is very easy to send out at first near terminal corner or terminal
Raw EAS burns, and is a larger bottleneck for lifting overall EAS abilities.As shown in figure 4, it is that existing trench gate surpasses shown in Fig. 1
The photo that the generation EAS of junction device burns；Position shown in dotted line circle 204 is that the position that EAS burns occurs, and the position, which is located at, to be leaned on
In the electric charge flow region near the pad 204 of nearly grid, pad 204 is made up of front metal layer, the grid in usual Fig. 1
Metal wire can surround and be formed at the source electrode being made up of front metal layer in electric charge flow region, the metal wire of grid can be in pad
204 opening position is formed at the larger pad 204 of the area for being advantageous to be connected with the external world.The generation that EAS described in Fig. 4 burns
Be due to existing groove grid super node device grid draw polysilicon it is reverse-biased be it is easy collect hole, so as to which larger base can be formed
Electrode current, burnt so that parasitic triode turns on and EAS occurs.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of groove grid super node device, can improve the reliability of grid simultaneously
With improve EAS abilities, so as to improve the robustness of device.Therefore, the present invention also provides a kind of manufacture of groove grid super node device
Method.
In order to solve the above technical problems, the intermediate region of groove grid super node device provided by the invention is electric charge flow region,
Terminal protection area is formed at the week side of boss of the electric charge flow region, and transition region is located at the terminal protection area and the electric charge flow region
Between.
Super-junction structure is alternately arranged and formed by multiple N-type posts and p-type post, and groove grid super node device includes trench gate and by P
The channel region of trap composition, the N-type post in the groove grid super node break-over of device as drift region, by N+ district's groups into source region
It is formed at the surface of the channel region.
The trench gate is formed in the electric charge flow region, and the trench gate includes gate groove, along the gate groove
Length direction on the gate groove also extend into the transition region formation grid end cephalic groove groove.
Top section in the side of the gate groove is big formed with gate oxide, the depth of the gate oxide laterally
In the depth of the channel region；In the gate groove positioned at the side of the gate oxide bottom and lower surface formed with
One oxide layer；The thickness of first oxide layer is more than the thickness of the gate oxide, is filled with the gate groove by more
The polysilicon gate of crystal silicon composition.
In the side of the grid end cephalic groove groove and lower surface formed with the first oxide layer, filled out in the grid end cephalic groove groove
Polysilicon is drawn filled with the grid being made up of polysilicon.
Field oxygen layer is formed in the terminal protection area, the field oxygen layer is in the transition region and the terminal protection area
Interface is formed about a ledge structure.
First oxide layer in the grid end cephalic groove groove also extends to the grid to the direction in the terminal protection area
Until connecting at the ledge structure with the field oxygen layer on the outside of the groove of termination；The grid in the grid end cephalic groove groove are drawn
Polysilicon is also extended on the outside of the grid end cephalic groove groove to the direction in the terminal protection area until getting over the ledge structure simultaneously
Positioned at the field oxygen layer surface.
The top that polysilicon is drawn in the grid for extending to the field oxygen layer surface is connect formed with contact hole and by this
Contact hole is connected to the grid being made up of front metal layer.
Polysilicon is drawn by the grid and the grid draw polysilicon top contact hole and form grid deriving structure, passes through setting
First oxide layer that thickness is more than the gate oxide improves the reliability of the grid deriving structure so as to improve device
Robustness, at the same reduce device it is reverse-biased when the grid draw polysilicon to hole collection in the transition region so as to improve device
EAS abilities.
Further improve is that the super-junction structure is formed in N-type epitaxy layer, and the N-type epitaxy layer, which is formed at, partly to be led
Body substrate surface, formed with multiple superjunction grooves in the N-type epitaxy layer, the p-type post is by being filled in the superjunction groove
In p type semiconductor layer composition.
Further improve is that the p type semiconductor layer is p-type epitaxial layer.
Further improve is that the Semiconductor substrate is silicon substrate, and the N-type epitaxy layer is N-type silicon epitaxy layer, described
P type semiconductor layer is P-type silicon layer.
Further improve is that drain region is formed from the N+ district's groups at the super-junction structure back side at the drain region back side
Formed with the drain electrode being made up of metal layer on back.
Further improve is to surpass in the transition region formed with p-type ring, the p-type ring and outermost trench gate
Junction device unit is adjacent, the more than one superjunction unit of p-type ring cover.
Further improve is that the top of the source region is connected to by positive gold formed with contact hole and by the contact hole
Belong to the source electrode of layer composition.
In order to solve the above technical problems, the groove grid super node device of the manufacture method of groove grid super node device provided by the invention
The intermediate region of part is electric charge flow region, and terminal protection area is formed at the week side of boss of the electric charge flow region, and transition region is positioned at described
Between terminal protection area and the electric charge flow region；Comprise the following steps：
Step 1: being formed the super-junction structure formed is alternately arranged by multiple N-type posts and p-type post.
Step 2: field oxygen layer is formed in the terminal protection area；The field oxygen layer is in the transition region and the terminal
The interface of protection zone is formed about a ledge structure.
Step 3: the channel region being made up of p-well is formed in the electric charge flow region.
Step 4: the electric charge is located at using lithographic etch process formation gate groove and grid end cephalic groove groove, the gate groove
In flow region, the grid end cephalic groove groove is located in the transition region and the grid end cephalic groove groove is along length side by the gate groove
Formed to extension, the grid end cephalic groove groove and the gate groove interconnect.
Step 5: forming the first oxide layer, first oxide layer is formed at the side and bottom of the gate groove simultaneously
The side and lower surface of surface and the grid end cephalic groove groove and the outer table with outside the grid end cephalic groove groove of the gate groove
Face.
Step 6: using photoetching process to the transition outside the grid end head trench region and the grid end cephalic groove groove
Area and the terminal protection area are protected, and first oxide layer carve, the first oxide layer described in Hui Kehou is located at
On the side of the bottom less than the channel region of the gate groove and in lower surface and positioned at the grid end cephalic groove groove
Side and lower surface and first oxide layer is also extended to outside the grid end cephalic groove groove to the direction in the terminal protection area
Side at the ledge structure with the field oxygen layer until connect.
Step 7: the top section for being located at first oxide layer in the side of the gate groove forms gate oxide.
Step 8: carry out polycrystalline silicon deposit and carry out chemical wet etching while form polysilicon gate and grid extraction polysilicon；Institute
Polysilicon gate is stated to be filled in the gate groove；The grid are drawn polysilicon and are filled in the grid end cephalic groove groove and to the end
The direction of end protection zone is extended on the outside of the grid end cephalic groove groove until getting over the ledge structure and being located at the field oxygen layer table
Face.
Step 9: the surface of the channel region formed with N+ district's groups into source region.
Step 10: forming interlayer film, contact hole, front metal layer, the source of being formed is patterned to the front metal layer
Pole and grid；The contact hole connected with the source electrode is located at the top of the source region.
The contact hole connected with the grid is located at the top for the grid extraction polysilicon for extending to the field oxygen layer surface
Portion；Polysilicon is drawn by the grid and the grid draw polysilicon top contact hole and form grid deriving structure, by setting thickness
First oxide layer more than the gate oxide improves the reliability of the grid deriving structure so as to improve the robust of device
Property, at the same reduce device it is reverse-biased when the grid draw polysilicon to hole collection in the transition region so as to improve the EAS of device
Ability.
Further improve is that the super-junction structure is formed in N-type epitaxy layer, and the N-type epitaxy layer, which is formed at, partly to be led
Body substrate surface, formed with multiple superjunction grooves in the N-type epitaxy layer, the p-type post is by being filled in the superjunction groove
In p type semiconductor layer composition.
Further improve is that the p type semiconductor layer is p-type epitaxial layer.
Further improve is that the Semiconductor substrate is silicon substrate, and the N-type epitaxy layer is N-type silicon epitaxy layer, described
P type semiconductor layer is P-type silicon layer.
Further improve is, in addition to following back process：
Step 11: at the super-junction structure back side formed with N+ district's groups into drain region.
Step 12: the drain electrode being made up of metal layer on back is formed at the drain region back side.
Further improve is that the step of forming p-type ring, the p-type ring are additionally included in the transition region in step 2
It is adjacent with outermost device cell, the more than one superjunction unit of p-type ring cover.
Further improve is that the p-type ring and the channel region are formed simultaneously using identical p-well technique.
Further improve is that the width of the grid end cephalic groove groove is more than or equal to the width of the gate groove.
The present invention is specifically designed to the gate oxide of trench gate, and the gate oxide of prior art is divided into two parts,
I.e. trench gate of the invention includes the first thicker oxide layer for being formed at gate groove bottom and positioned at gate groove top and side
Face can cover channel region and the relatively thin gate oxide for controlling raceway groove to be formed, meanwhile, trench gate is extended in transition region
Grid end cephalic groove groove is formed, the first thicker oxide layer is used between the side of grid end cephalic groove groove and lower surface, in grid end cephalic groove
Filling draws polysilicon by grid in groove, and it can be that terminal protection area side extends and extended to and climbs laterally that grid, which draw polysilicon,
The ledge structure formed by field oxygen layer in terminal protection area is crossed, while the first thicker oxide layer also extends into grid end cephalic groove groove and arrived
Between ledge structure, first oxide layer thicker than gate oxide is formed so as to draw the bottom of polysilicon in grid；Due to positioned at
Polysilicon gate in electric charge flow region is the contact by drawing polysilicon with grid, then draws connecing for polysilicon and top by grid
The contact of contact hole is connected to grid, therefore grid draw contact hole corresponding to polysilicon and top as grid deriving structure, the present invention
Pass through the setting of the first thicker oxide layer so that the grid in grid deriving structure region draw the oxidated layer thickness of polysilicon bottom
Thickening and thickness can individually control relative to the gate oxide for controlling raceway groove to be formed, therefore can by thickening the first oxide layer
The reliability of grid deriving structure is improved so as to improving the robustness of device.
Meanwhile after the thickness increase of the first oxide layer in grid deriving structure region, grid draw polysilicon to bottom zone
The control ability in domain dies down, generally, when device is reverse-biased, to exhausting except being exhausted by p-type post for the drift region of device
Outside, the polysilicon gate in electric charge flow region and the grid in transition region and terminal protection area, which draw polysilicon, can also pass through oxide layer
Drift region is exhausted, it is reverse-biased in device to reduce grid extraction polysilicon by the thickness of the first oxide layer of increase by the present invention
When drift region is exhausted, so as to reduce device it is reverse-biased when grid draw polysilicon to hole collection energy in transition region, so as to carry
The EAS abilities of high device, this also can further improve the robustness of device.
Brief description of the drawings
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description：
Fig. 1 is the structural representation of existing groove grid super node device；
Fig. 2 is photo in Fig. 1；
Fig. 3 is grid weakness point failure photo in Fig. 1；
Fig. 4 is that the EAS of existing device shown in Fig. 1 burns photo；
Fig. 5 is the structural representation of groove grid super node device of the embodiment of the present invention；
Fig. 6 is the vertical plane structural representation at AA line positions in Fig. 5；
Fig. 7 is the vertical plane structural representation at BB line positions in Fig. 5；
Fig. 8 A- Fig. 8 C are showing in each step for the interior surface oxide layer that trench gate is formed in present invention method
It is intended to.
Embodiment
As shown in figure 5, it is the structural representation of groove grid super node device of the embodiment of the present invention；Fig. 6 is AA line positions in Fig. 5
The vertical plane structural representation at place；Fig. 7 is the vertical plane structural representation at BB line positions in Fig. 5；Groove of the embodiment of the present invention
The intermediate region of grid superjunction devices is electric charge flow region, and terminal protection area is formed at the week side of boss of the electric charge flow region, transition region
Between the terminal protection area and the electric charge flow region.
Super-junction structure is alternately arranged and formed by multiple N-type posts and p-type post, and groove grid super node device includes trench gate and by P
The channel region of trap composition, the N-type post in the groove grid super node break-over of device as drift region, by N+ district's groups into source region
It is formed at the surface of the channel region.The mainly structure chart near display transition region, and be along the length side of super-junction structure in Fig. 5
To sectional structure chart, therefore there is no display the N-type post and p-type post that are alternately arranged in Fig. 5.
The super-junction structure is formed in N-type epitaxy layer 1, and the N-type epitaxy layer 1 is formed at semiconductor substrate surface,
Formed with multiple superjunction grooves in the N-type epitaxy layer 1, the p-type post is by the P-type semiconductor that is filled in the superjunction groove
Layer such as p-type epitaxial layer forms, and the p type semiconductor layer can also include p-type polysilicon layer.Preferably, the Semiconductor substrate is
Silicon substrate, the N-type epitaxy layer 1 are N-type silicon epitaxy layer, and the p type semiconductor layer is P-type silicon layer.
Formed with p-type ring 2, the p-type ring 2 and outermost groove grid super node device cell phase in the transition region
Neighbour, the p-type ring 2 cover the more than one superjunction unit, and the p-type ring 2 covers more than one superjunction unit.
The trench gate is formed in the electric charge flow region, and the trench gate includes gate groove 301, along the grid ditch
The gate groove 301, which also extends into, on the length direction of groove 301 forms grid end cephalic groove groove 302 in the transition region.
The side of the gate groove 301 top section formed with gate oxide 4a, the gate oxide 4a is laterally
Depth be more than the channel region depth；In the gate groove 301 positioned at the side and bottom of the gate oxide 4a bottoms
Portion surface is formed with the first oxide layer 4；The thickness of first oxide layer 4 is more than the thickness of the gate oxide 4a, described
Filled with the polysilicon gate 5 being made up of polysilicon in gate groove 301.
In the side of the grid end cephalic groove groove 302 and lower surface formed with the first oxide layer 4, in the grid end cephalic groove groove
The grid being made up of polysilicon are filled with 302 and draw polysilicon 5a.
Field oxygen layer 3 is formed in the terminal protection area, the field oxygen layer 3 is in the transition region and the terminal protection area
Interface be formed about a ledge structure.
First oxide layer 4 in the grid end cephalic groove groove 302 also extends to institute to the direction in the terminal protection area
The outside of grid end cephalic groove groove 302 is stated until connecting at the ledge structure with the field oxygen layer 3；In the grid end cephalic groove groove 302
The grid draw polysilicon 5a and also extend to the outside of grid end cephalic groove groove 302 until climbing to the direction in the terminal protection area
Cross the ledge structure and be located at the surface of field oxygen layer 3.
Drawn in the grid for extending to the surface of field oxygen layer 3 and be formed through interlayer film 6 at the top of polysilicon 5a
Contact hole 7 is simultaneously connected to the grid being made up of front metal layer 8 by the contact hole 7.
The top of the source region is connected to the source being made up of front metal layer 8 formed with contact hole 7 and by the contact hole 7
Pole.
Drain region is formed from the N+ district's groups at the super-junction structure back side at the drain region back side formed with by back metal
The drain electrode of layer composition.
Polysilicon 5a is drawn by the grid and the grid draw polysilicon 5a top contacts hole 7 and form grid deriving structure, is led to
Cross and set first oxide layer 4 of the thickness more than the gate oxide 4a to improve the reliability of the grid deriving structure so as to carry
The robustness of high device, at the same reduce device it is reverse-biased when the grid draw polysilicon 5a to hole collection in the transition region so as to
Improve the EAS abilities of device.
The intermediate region of the groove grid super node device of the manufacture method of groove grid super node device of the embodiment of the present invention is electric charge
Flow region, terminal protection area are formed at the week side of boss of the electric charge flow region, and transition region is located at the terminal protection area and the electricity
Between lotus flow region；Comprise the following steps：
Step 1: being formed the super-junction structure formed is alternately arranged by multiple N-type posts and p-type post.
The super-junction structure is formed in N-type epitaxy layer 1, and the N-type epitaxy layer 1 is formed at semiconductor substrate surface,
Formed with multiple superjunction grooves in the N-type epitaxy layer 1, the p-type post is by the P-type semiconductor that is filled in the superjunction groove
Layer such as p-type epitaxial layer forms, and the p type semiconductor layer can also include p-type polysilicon layer.Preferably, the Semiconductor substrate is
Silicon substrate, the N-type epitaxy layer 1 are N-type silicon epitaxy layer, and the p type semiconductor layer is P-type silicon layer.
Step 2: field oxygen layer 3 is formed in the terminal protection area；The field oxygen layer 3 is in the transition region and the end
The interface of end protection zone is formed about a ledge structure.
Step 3: the channel region being made up of p-well is formed in the electric charge flow region.
The step of forming p-type ring 2, the p-type ring 2 and outermost device cell phase are additionally included in the transition region
Neighbour, the p-type ring 2 cover the more than one superjunction unit.
The p-type ring 2 can be formed simultaneously with the channel region, i.e., all formed using p-well technique.
Step 4: it is located at using lithographic etch process formation gate groove 301 and grid end cephalic groove groove 302, the gate groove 301
In the electric charge flow region, the grid end cephalic groove groove 302 is located in the transition region and the grid end cephalic groove groove 302 is by described
Gate groove 301 extends formation along its length, and the grid end cephalic groove groove 302 and the gate groove 301 interconnect.The grid end
The width of cephalic groove groove 302 is more than or equal to the width of the gate groove 301.
Step 5: as shown in Figure 8 A, forming the first oxide layer 4, first oxide layer 4 is formed at the gate groove simultaneously
The side and lower surface of 301 side and lower surface and the grid end cephalic groove groove 302 and the gate groove 301 it is outer and
Surface outside the grid end cephalic groove groove 302.
Step 6: as shown in Figure 8 A, the graphic structure of photoresist 303 is formed to the grid end cephalic groove groove using photoetching process
302 regions and the transition region outside the grid end cephalic groove groove 302 and the terminal protection area are protected, and Fig. 8 A are shown
The cross-section structure formed after photoresist 303, needs to remove the photoresist 303 in the region of gate groove 301 afterwards, described
The region of grid end cephalic groove groove 302 and the transition region and the photoresist in the terminal protection area outside the grid end cephalic groove groove 302
303 retain.
As shown in Figure 8 B, first oxide layer 4 carve, the first oxide layer 4 is located at the grid described in Hui Kehou
On the side of the bottom less than the channel region of groove 301 and in lower surface and positioned at the grid end cephalic groove groove 302
Side and lower surface and first oxide layer 4 also extends to the grid end cephalic groove groove to the direction in the terminal protection area
302 outsides at the ledge structure with the field oxygen layer 3 until connect.
Step 7: as shown in Figure 8 C, it is located at the top section of first oxide layer 4 in the side of the gate groove 301
Form gate oxide 4a.
Step 8: carry out polycrystalline silicon deposit and carry out chemical wet etching while form polysilicon gate 5 and grid extraction polysilicon 5a；
The polysilicon gate 5 is filled in the gate groove 301；The grid draw polysilicon 5a and are filled in the grid end cephalic groove groove 302
In and to the direction in the terminal protection area extend to the outside of the grid end cephalic groove groove 302 until getting over the ledge structure and position
In the surface of field oxygen layer 3.
Step 9: the surface of the channel region formed with N+ district's groups into source region.
Step 10: forming interlayer film 6, contact hole 7, front metal layer 8, shape is patterned to the front metal layer 8
Into source electrode and grid；The contact hole 7 connected with the source electrode is located at the top of the source region.
The contact hole 7 connected with the grid is located at the grid extraction polysilicon 5a for extending to the surface of field oxygen layer 3
Top；Polysilicon 5a is drawn by the grid and the grid draw polysilicon 5a top contacts hole 7 and form grid deriving structure, is passed through
First oxide layer 4 of the thickness more than the gate oxide 4a is set to improve the reliability of the grid deriving structure so as to improve
The robustness of device, at the same reduce device it is reverse-biased when the grid draw polysilicon 5a to hole collection in the transition region so as to carry
The EAS abilities of high device.
Also include following back process：
Step 11: at the super-junction structure back side formed with N+ district's groups into drain region.
Step 12: the drain electrode being made up of metal layer on back is formed at the drain region back side.
The present invention is described in detail above by specific embodiment, but these not form the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, and these also should
It is considered as protection scope of the present invention.
Claims (15)
- A kind of 1. groove grid super node device, it is characterised in that：The intermediate region of groove grid super node device is electric charge flow region, terminal Protection zone is formed at the week side of boss of the electric charge flow region, transition region be located at the terminal protection area and the electric charge flow region it Between；Super-junction structure is alternately arranged and formed by multiple N-type posts and p-type post, and groove grid super node device includes trench gate and by p-well group Into channel region, the N-type post in the groove grid super node break-over of device as drift region, by N+ district's groups into source region formed In the surface of the channel region；The trench gate is formed in the electric charge flow region, and the trench gate includes gate groove, in the length along the gate groove The gate groove also extends into formation grid end cephalic groove groove in the transition region on degree direction；Top section in the side of the gate groove is more than institute formed with gate oxide, the depth of the gate oxide laterally State the depth of channel region；In the gate groove positioned at the side of the gate oxide bottom and lower surface formed with the first oxygen Change layer；The thickness of first oxide layer is more than the thickness of the gate oxide, is filled with the gate groove by polysilicon The polysilicon gate of composition；In the side of the grid end cephalic groove groove and lower surface formed with the first oxide layer, it is filled with the grid end cephalic groove groove The grid being made up of polysilicon draw polysilicon；Field oxygen layer is formed in the terminal protection area, the field oxygen layer is in the boundary in the transition region and the terminal protection area Face is formed about a ledge structure；First oxide layer in the grid end cephalic groove groove also extends to the grid end head to the direction in the terminal protection area Until connecting at the ledge structure with the field oxygen layer on the outside of groove；The grid in the grid end cephalic groove groove draw polycrystalline Silicon is also extended on the outside of the grid end cephalic groove groove to the direction in the terminal protection area until getting over the ledge structure and being located at The field oxygen layer surface；The top of polysilicon is drawn formed with contact hole and by the contact hole in the grid for extending to the field oxygen layer surface It is connected to the grid being made up of front metal layer；Polysilicon is drawn by the grid and the grid draw polysilicon top contact hole and form grid deriving structure, by setting thickness First oxide layer more than the gate oxide improves the reliability of the grid deriving structure so as to improve the robust of device Property, at the same reduce device it is reverse-biased when the grid draw polysilicon to hole collection in the transition region so as to improve the EAS of device Ability.
- 2. groove grid super node device as claimed in claim 1, it is characterised in that：The super-junction structure is formed at N-type epitaxy layer In, the N-type epitaxy layer is formed at semiconductor substrate surface, described formed with multiple superjunction grooves in the N-type epitaxy layer P-type post is made up of the p type semiconductor layer being filled in the superjunction groove.
- 3. groove grid super node device as claimed in claim 2, it is characterised in that：The p type semiconductor layer is p-type epitaxial layer.
- 4. groove grid super node device as claimed in claim 2 or claim 3, it is characterised in that：The Semiconductor substrate is silicon substrate, institute It is N-type silicon epitaxy layer to state N-type epitaxy layer, and the p type semiconductor layer is P-type silicon layer.
- 5. groove grid super node device as claimed in claim 1 or 2, it is characterised in that：Drain region is formed from the super-junction structure The N+ district's groups at the back side are at the drain region back side formed with the drain electrode being made up of metal layer on back.
- 6. groove grid super node device as claimed in claim 1, it is characterised in that：Formed with p-type ring, institute in the transition region State p-type ring and outermost groove grid super node device cell is adjacent, the more than one superjunction unit of p-type ring cover.
- 7. groove grid super node device as claimed in claim 1, it is characterised in that：The top of the source region formed with contact hole simultaneously The source electrode being made up of front metal layer is connected to by the contact hole.
- 8. a kind of manufacture method of groove grid super node device, it is characterised in that the intermediate region of groove grid super node device is electric charge Flow region, terminal protection area are formed at the week side of boss of the electric charge flow region, and transition region is located at the terminal protection area and the electricity Between lotus flow region；Comprise the following steps：Step 1: being formed the super-junction structure formed is alternately arranged by multiple N-type posts and p-type post；Step 2: field oxygen layer is formed in the terminal protection area；The field oxygen layer is in the transition region and the terminal protection The interface in area is formed about a ledge structure；Step 3: the channel region being made up of p-well is formed in the electric charge flow region；Step 4: forming gate groove and grid end cephalic groove groove using lithographic etch process, the gate groove is located at electric charge flowing Qu Zhong, the grid end cephalic groove groove is located in the transition region and the grid end cephalic groove groove is to be prolonged along its length by the gate groove Stretch to be formed, the grid end cephalic groove groove and the gate groove interconnect；Step 5: forming the first oxide layer, first oxide layer is formed at side and the lower surface of the gate groove simultaneously And the side of the grid end cephalic groove groove and lower surface and the outer surface with outside the grid end cephalic groove groove of the gate groove；Step 6: using photoetching process to the transition region outside the grid end head trench region and the grid end cephalic groove groove and The terminal protection area is protected, and first oxide layer carve, the first oxide layer described in Hui Kehou is positioned at described On the side of the bottom less than the channel region of gate groove and in lower surface and positioned at the side of the grid end cephalic groove groove Also extended to lower surface and first oxide layer to the direction in the terminal protection area on the outside of the grid end cephalic groove groove directly Extremely connect at the ledge structure with the field oxygen layer；Step 7: the top section for being located at first oxide layer in the side of the gate groove forms gate oxide；Step 8: carry out polycrystalline silicon deposit and carry out chemical wet etching while form polysilicon gate and grid extraction polysilicon；It is described more Crystal silicon grid are filled in the gate groove；The grid draw polysilicon and are filled in the grid end cephalic groove groove and are protected to the terminal The direction in shield area is extended on the outside of the grid end cephalic groove groove until getting over the ledge structure and being located at the field oxygen layer surface；Step 9: the surface of the channel region formed with N+ district's groups into source region；Step 10: formed interlayer film, contact hole, front metal layer, the front metal layer is patterned to be formed source electrode and Grid；The contact hole connected with the source electrode is located at the top of the source region；The contact hole connected with the grid is located at the top for the grid extraction polysilicon for extending to the field oxygen layer surface；By The grid draw polysilicon and the grid draw polysilicon top contact hole and form grid deriving structure, by setting thickness to be more than institute The reliability of first oxide layer raising grid deriving structure of gate oxide is stated so as to improve the robustness of device, simultaneously Reduce device it is reverse-biased when the grid draw polysilicon to hole collection in the transition region so as to improve the EAS abilities of device.
- 9. the manufacture method of groove grid super node device as claimed in claim 8, it is characterised in that：The super-junction structure is formed at In N-type epitaxy layer, the N-type epitaxy layer is formed at semiconductor substrate surface, formed with multiple superjunction in the N-type epitaxy layer Groove, the p-type post are made up of the p type semiconductor layer being filled in the superjunction groove.
- 10. superjunction devices as claimed in claim 9, it is characterised in that：The p type semiconductor layer is p-type epitaxial layer.
- 11. the superjunction devices as described in claim 9 or 10, it is characterised in that：The Semiconductor substrate is silicon substrate, the N Type epitaxial layer is N-type silicon epitaxy layer, and the p type semiconductor layer is P-type silicon layer.
- 12. superjunction devices as claimed in claim 8 or 9, it is characterised in that：Also include following back process：Step 11: at the super-junction structure back side formed with N+ district's groups into drain region；Step 12: the drain electrode being made up of metal layer on back is formed at the drain region back side.
- 13. superjunction devices as claimed in claim 8, it is characterised in that：It is additionally included in step 2 in the transition region and forms P The step of type ring, the p-type ring and outermost device cell are adjacent, the more than one superjunction list of p-type ring cover Member.
- 14. superjunction devices as claimed in claim 13, it is characterised in that：The p-type ring and the channel region use identical p-well Technique is formed simultaneously.
- 15. superjunction devices as claimed in claim 8, it is characterised in that：The width of the grid end cephalic groove groove is more than or equal to described The width of gate groove.
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| CN201710768048.0A CN107591440A (en) | 2017-08-31 | 2017-08-31 | Groove grid super node device and its manufacture method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111477679A (en) * | 2020-04-17 | 2020-07-31 | 重庆伟特森电子科技有限公司 | Preparation method of asymmetric groove type SiC-MOSFET gate |
| CN115763521A (en) * | 2022-11-03 | 2023-03-07 | 上海功成半导体科技有限公司 | Super junction device terminal structure and preparation method thereof |
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