CN108807502B - Manufacturing method of NLDMOS device and LDMOS power device - Google Patents
Manufacturing method of NLDMOS device and LDMOS power device Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 52
- 238000005468 ion implantation Methods 0.000 claims abstract description 99
- 238000002955 isolation Methods 0.000 claims abstract description 98
- 238000001259 photo etching Methods 0.000 claims abstract description 46
- 230000005669 field effect Effects 0.000 claims abstract description 37
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 31
- 238000000206 photolithography Methods 0.000 claims description 24
- 239000000758 substrate Substances 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 239000002131 composite material Substances 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 15
- 239000000126 substance Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H01L29/0646—PN junctions
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Abstract
The invention provides a manufacturing method of a full-isolation type NLDMOS device and an LDMOS power device, which comprises the steps of depositing a dielectric layer on the surface of an epitaxial layer positioned above an N-type buried layer, photoetching the dielectric layer to remove redundant dielectric layer to form a field effect oxide layer, photoetching and performing first ion implantation on the epitaxial layer, respectively photoetching and performing ion implantation on the epitaxial layer by adopting a PGRD photomask and an NGRD photomask to respectively form a P-type drain drift region and an N-type drain drift region, simultaneously performing second ion implantation on a prefabricated P-type isolation structure positioned below the N-type drain drift region to form a P-type isolation structure between the epitaxial layer and the N-type buried layer, then forming a P-type well region in the P-type drain drift region, forming an N-type well region in the N-type drain drift region, and forming a grid structure on the field effect oxide layer. The invention simplifies the manufacturing process flow of the semiconductor device with the surface field effect oxide layer structure.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a manufacturing method of a full-isolation type NLDMOS device and a manufacturing method of a full-isolation type LDMOS power device.
Background
In a Laterally Diffused Metal Oxide Semiconductor (LDMOS) device, on-resistance is an important index, which affects the performance of the LDMOS device. In an LDMOS power device, in order to improve the performance of the LDMOS device, a surface field oxide layer is usually disposed in an NLDMOS device region of the LDMOS device instead of an embedded field oxide layer, and an embedded field oxide layer is still employed in a PLDMOS device region, where the NLDMOS refers to an N-type LDMOS and the PLDMOS refers to a P-type LDMOS. Referring to fig. 1, a conventional fully-isolated NLDMOS device includes an N-type buried layer NBL and a P-type buried layer PBL formed on a substrate (not shown), an epitaxial layer EPI formed on the NBL and the PBL, a plurality of P-type drain drift regions Pdrift and a plurality of N-type drain drift regions ndrit formed in the EPI, and P-type well regions Pwell and Nwell formed in the Pdrift and Ndrift, respectively, heavily doped P-type and N-type ion implantation regions P + and N +, a field oxide layer GO formed on a surface of the EPI, a Gate structure Gate formed on the Gate structure Gate, a P-type isolation structure PB formed between the Pdrift, Ndrift, and pdgo rift and NBL under the Gate structure, ndgate structure Gate. The fully isolated LDMOS means that the N-type drain drift regions Ndrift and NBL need to withstand voltage, and thus a P-type isolation structure needs to be formed. Some LDMOS do not require this Ptype, and there is no explicit voltage requirement between NGRD and NBL.
The manufacturing method of the full-isolation NLDMOS device in the prior art comprises the following steps:
step 01, providing a substrate;
step 02, forming an N-type buried layer and a P-type buried layer on a substrate;
step 03, forming epitaxial layers on the N-type buried layer and the P-type buried layer;
step 04, photoetching the epitaxial layer, filling a medium into a groove formed by photoetching, etching, and carrying out chemical mechanical grinding on the filled medium to flatten the medium to form a shallow trench isolation structure;
step 05, depositing a dielectric layer on the surface of the epitaxial layer positioned above the N-type buried layer;
step 06, performing photoetching on the dielectric layer by using a PGRD photomask to remove redundant dielectric layers to form a field effect oxide layer, and performing ion implantation on the exposed epitaxial layer to form a P-type drain drift region;
step 07, photoetching the dielectric layer by adopting an NGRD photomask to divide the field effect oxide layer into two parts, and performing ion implantation on the epitaxial layer to form an N-type drain electrode drift region;
step 08, photoetching and ion implantation are performed downwards through the P-type drain drift region and the N-type drain drift region to form a P-type isolation structure between the P-type isolation structure and the N-type buried layer;
step 09, photoetching and ion implantation are carried out in the N-type drain electrode drift region to form an N-type well region;
step 10, carrying out photoetching and ion implantation in the P-type drain drift region to form a P-type well region;
step 11, forming a grid structure on the field effect oxide layer;
and step 12, forming a heavily doped P-type ion implantation region and an N-type ion implantation region.
The method for manufacturing the full-isolation NLDMOS device comprises the steps of defining a field-effect oxide layer by a PGRD photomask, namely photoetching a deposited dielectric layer through the PGRD photomask to remove a non-redundant dielectric layer to form the field-effect oxide layer positioned on the surface of an epitaxial layer, and etching in the process of forming a P-type drain electrode drift region, a P-type well region and an N-type well region by the PGRD photomask, wherein the process flow is complex. In addition, the PGRD photomask in the method is used for ion implantation of the drain drift region of the PLDMOS, so the PGRD photomask is used for defining the field effect oxide layer, the PLDMOS can only use the traditional STI to be used as the field effect oxide layer, and the consequence is that the on-resistance cannot be reduced.
Disclosure of Invention
The invention aims to solve the technical problem of providing a manufacturing method of a full-isolation type NLDMOS device and a manufacturing method of a full-isolation type LDMOS power device so as to simplify the manufacturing process flow of a semiconductor device with a surface field effect oxide layer structure.
In order to solve the technical problem, the invention provides a method for manufacturing a full-isolation NLDMOS device, which comprises the following steps:
providing a substrate;
forming an N-type buried layer and a P-type buried layer on a substrate;
forming an epitaxial layer on the N-type buried layer and the P-type buried layer;
photoetching, etching and chemically mechanical grinding the epitaxial layer to form a shallow trench isolation structure;
depositing a dielectric layer on the surface of the epitaxial layer positioned above the N-type buried layer;
photoetching the dielectric layer by using the same mask plate to remove redundant dielectric layers to form a field effect oxide layer, photoetching the epitaxial layer and carrying out first ion implantation to form a P-type isolation structure between the P-type drain drift region and the N-type buried layer and form a prefabricated P-type isolation structure between the N-type drain drift region and the N-type buried layer;
and photoetching and ion implantation are carried out on the epitaxial layer by adopting a PGRD photomask to form a P-type drain electrode drift region, photoetching and ion implantation are carried out on the epitaxial layer by adopting the NGRD photomask to form an N-type drain electrode drift region, meanwhile, secondary ion implantation is carried out on a prefabricated P-type isolation structure positioned below the N-type drain electrode drift region to form a P-type isolation structure between the N-type drain electrode drift region and the N-type buried layer, a P-type well region is formed in the P-type drain electrode drift region, and an N-type well region is formed in the N-type drain electrode drift region.
A gate structure is formed over the field effect oxide layer.
Further, the method for manufacturing a fully-isolated NLDMOS device according to the present invention includes the steps of performing photolithography and ion implantation on the epitaxial layer by using a PGRD photomask to form a P-type drain drift region, performing photolithography and ion implantation on the epitaxial layer by using a NGRD photomask to form an N-type drain drift region, performing a second ion implantation on the prefabricated P-type isolation structure located below the N-type drain drift region to form a P-type isolation structure between the N-type drain drift region and the N-type buried layer, forming a P-type well region in the P-type drain drift region, and forming an N-type well region in the N-type drain drift region, which sequentially include:
firstly, photoetching and ion implantation are carried out on an epitaxial layer by adopting an NGRD photomask to form an N-type drain electrode drift region;
secondly, performing secondary ion implantation on the prefabricated P-type isolation structure positioned in the N-type drain electrode drift region to form a P-type isolation structure between the N-type drain electrode drift region and the N-type buried layer;
thirdly, photoetching and ion implantation are carried out on the epitaxial layer by adopting a PGRD photomask to form a P-type drain electrode drift region;
finally, a P-type well region is formed in the P-type drain drift region, and an N-type well region is formed in the N-type drain drift region.
Further, the method for manufacturing a fully-isolated NLDMOS device according to the present invention includes the steps of performing photolithography and ion implantation on the epitaxial layer by using a PGRD photomask to form a P-type drain drift region, performing photolithography and ion implantation on the epitaxial layer by using a NGRD photomask to form an N-type drain drift region, performing a second ion implantation on the prefabricated P-type isolation structure located below the N-type drain drift region to form a P-type isolation structure between the N-type drain drift region and the N-type buried layer, forming a P-type well region in the P-type drain drift region, and forming an N-type well region in the N-type drain drift region, which sequentially include:
firstly, photoetching and ion implantation are carried out on an epitaxial layer by adopting a PGRD photomask to form a P-type drain electrode drift region;
secondly, photoetching and ion implantation are carried out on the epitaxial layer by adopting an NGRD photomask to form an N-type drain electrode drift region;
thirdly, performing second ion implantation on the prefabricated P-type isolation structure positioned below the N-type drain drift region to form a P-type isolation structure between the N-type drain drift region and the N-type buried layer;
finally, a P-type well region is formed in the P-type drain drift region, and an N-type well region is formed in the N-type drain drift region.
Further, the method for manufacturing a fully-isolated NLDMOS device according to the present invention includes the steps of performing photolithography and ion implantation on the epitaxial layer by using a PGRD photomask to form a P-type drain drift region, performing photolithography and ion implantation on the epitaxial layer by using a NGRD photomask to form an N-type drain drift region, performing a second ion implantation on the prefabricated P-type isolation structure located below the N-type drain drift region to form a P-type isolation structure between the N-type drain drift region and the N-type buried layer, forming a P-type well region in the P-type drain drift region, and forming an N-type well region in the N-type drain drift region, which sequentially include:
firstly, photoetching and ion implantation are carried out on an epitaxial layer by adopting an NGRD photomask to form an N-type drain electrode drift region;
secondly, performing secondary ion implantation on the prefabricated P-type isolation structure below the N-type drain drift region to form a P-type isolation structure between the N-type drain drift region and the N-type buried layer;
thirdly, forming an N-type well region in the N-type drain electrode drift region;
then, photoetching and ion implantation are carried out on the epitaxial layer by adopting a PGRD photomask to form a P-type drain electrode drift region;
and finally, forming a P-type well region in the P-type drain drift region.
Further, the method for manufacturing a fully-isolated NLDMOS device according to the present invention includes the steps of performing photolithography and ion implantation on the epitaxial layer by using a PGRD photomask to form a P-type drain drift region, performing photolithography and ion implantation on the epitaxial layer by using a NGRD photomask to form an N-type drain drift region, performing a second ion implantation on the prefabricated P-type isolation structure located below the N-type drain drift region to form a P-type isolation structure between the N-type drain drift region and the N-type buried layer, forming a P-type well region in the P-type drain drift region, and forming an N-type well region in the N-type drain drift region, which sequentially include:
firstly, photoetching and ion implantation are carried out on an epitaxial layer by adopting a PGRD photomask to form a P-type drain electrode drift region;
secondly, forming a P-type well region in the P-type drain drift region;
thirdly, photoetching and ion implantation are carried out on the epitaxial layer by adopting an NGRD photomask to form an N-type drain electrode drift region;
then, performing second ion implantation on the prefabricated P-type isolation structure below the N-type drain drift region to form a P-type isolation structure between the N-type drain drift region and the N-type buried layer;
and finally, forming an N-type well region in the N-type drain drift region.
Furthermore, according to the manufacturing method of the fully-isolated NLDMOS device provided by the present invention, the ion source of the first ion implantation is the same as that of the second ion implantation.
Furthermore, according to the manufacturing method of the fully-isolated NLDMOS device provided by the invention, the ion source is boron.
Furthermore, in the manufacturing method of the fully-isolated NLDMOS device provided by the present invention, the field effect oxide layer is a composite structure including an oxide and a nitride formed on the substrate.
Furthermore, according to the manufacturing method of the fully-isolated NLDMOS device provided by the invention, the oxide is silicon dioxide, and the nitride is silicon nitride.
Compared with the prior art, the manufacturing method of the full-isolation NLDMOS device comprises the steps of photoetching a dielectric layer to form a uniform-effect oxide layer, photoetching an epitaxial layer and carrying out first ion implantation to form a P-type isolation structure between a P-type drain drift region and an N-type buried layer and a prefabricated P-type isolation structure between an N-type drain drift region and an N-type buried layer, forming a P-type drain drift region and an N-type drain drift region, carrying out second ion implantation to the isolation structure below the N-type drain drift region to form an isolation structure between the N-type drain drift region and the N-type buried layer, forming a P-type drain drift region and an N-type drain drift region, and finally forming a grid structure, a P-type ion implantation region and an N-type ion implantation region. Therefore, compared with the traditional P-type isolation structure, the method has the advantages that the forming steps of the mask plate are not added, only the sequence of forming the P-type isolation structure is changed, and the etching process is not needed in the process of forming the P-type drain drift region and the N-type drain drift region.
In order to solve the above technical problem, the present invention further provides a method for manufacturing a fully isolated LDMOS power device, which includes the following steps;
forming a field effect oxide layer of the NLDMOS device on the surface of an epitaxial layer of the NLDMOS device region by adopting the manufacturing method of the full-isolation NLDMOS device;
and forming a field effect oxide layer of the PLDMOS device on the surface of the epitaxial layer of the PLDMOS device region by adopting the manufacturing method of the PLDMOS device, which is the reverse process of the manufacturing method of the full-isolation type NLDMOS device.
Compared with the prior art, the manufacturing method of the full-isolation LDMOS power device provided by the invention has the advantages that the isolation structure between the power device and the buried layer is formed, and then the process steps of the P-type drain drift region, the N-type drain drift region, the P-type well region and the N-type well region are carried out, so that the PLDMOS device and the NLDMOS device in the semiconductor devices such as the LDMOS power device and the like form a surface field oxide layer structure. Compared with the traditional PLDMOS device which is a trench-embedded field effect oxide layer, the on-resistance of the PLDMOS device is reduced, so that a semiconductor device with lower on-resistance can be formed, and the performance of the semiconductor device is improved. Compared with an LDMOS power device, the manufacturing method of the invention not only simplifies the manufacturing process flow of the semiconductor device, but also can manufacture the semiconductor devices of the PLDMOS device and the NLDMOS device which have the surface field effect oxide layer structure simultaneously.
Drawings
Fig. 1 is a schematic cross-sectional structure of an NLDMOS device;
fig. 2 is a schematic structural diagram of an NLDMOS device according to an embodiment of the present invention;
fig. 3 is a process flow diagram of an NLDMOS device according to an embodiment of the present invention.
Detailed Description
The invention is described in detail below with reference to the attached drawing figures:
referring to fig. 2 and fig. 3, an embodiment of the present invention provides a method for manufacturing a fully-isolated NLDMOS device, including the following steps:
at step 110, a substrate (not shown) is provided. Wherein the substrate is a P-type silicon substrate, other alternative materials are also possible.
And 130, forming an epitaxial layer EPI on the N-type buried layer NBL and the P-type buried layer PBL.
150, depositing a dielectric layer on the surface of the epitaxial layer EPI positioned on the N-type buried layer NBL;
and 160, photoetching the dielectric layer by using the same mask plate to remove the redundant dielectric layer to form a field effect oxide layer GO, photoetching the epitaxial layer EPI and performing first ion implantation to form a P-type isolation structure PB between the P-type drain drift region Pdrift and the N-type buried layer NBL and form a prefabricated P-type isolation structure PB between the N-type drain drift region Ndrift and the N-type buried layer NBL. And removing the redundant dielectric layer to form a dielectric layer reserved in the field effect oxide layer GO, wherein the dielectric layer reserved in the field effect oxide layer GO comprises a part of dielectric layer covering the P-type drain drift region and a part of dielectric layer reserved in the N-type drain drift region, and the rest part is a removed region. After a part of the dielectric layer above the N-type drain drift region is removed, the field effect oxide layer GO is divided into symmetrical mirror image structures.
And step 180, forming a Gate structure Gate on the field effect oxide layer GO.
The forming step 107 can be implemented by the following four schemes.
Scheme one
Step 1071, carrying out photoetching and ion implantation on the epitaxial layer EPI by adopting an NGRD photomask to form an N-type drain drift region Ndrift;
step 1072, performing a second ion implantation on the prefabricated P-type isolation structure PB located in the N-type drain drift region Ndrift to form the P-type isolation structure PB between the N-type drain drift region Ndrift and the N-type buried layer NBL;
step 1073, photoetching and ion implantation are carried out on the epitaxial layer EPI by adopting a PGRD photomask to form a P-type drain drift region Pdrift;
step 1074, a P-well region is formed in the P-drain drift region Pdrift and an N-well region is formed in the N-drain drift region Ndrift. Wherein in step 1074, the order of the P-well region and the N-well region may be replaced.
Scheme two
Step 2071, performing photolithography and ion implantation on the epitaxial layer EPI by using a PGRD photomask to form a P-type drain drift region Pdrift;
step 2072, performing photolithography and ion implantation on the EPI layer EPI by using the NGRD photomask to form an N-type drain drift region Ndrift;
step 2073, performing a second ion implantation on the prefabricated P-type isolation structure PB located below the N-type drain drift region Ndrift to form a P-type isolation structure PB between the N-type drain drift region Ndrift and the N-type buried layer NBL;
step 2074, form a P-well in the P-drain drift region Pdrift and an N-well in the N-drain drift region Ndrift. Wherein, in step 2074, the order of the P-well and N-well regions may be replaced.
Scheme three
3071, performing photolithography and ion implantation on the epitaxial layer EPI by using an NGRD photomask to form an N-type drain drift region Ndrift;
step 3072, performing second ion implantation on the prefabricated P-type isolation structure PB below the N-type drain drift region Ndrift to form the P-type isolation structure PB between the N-type drain drift region Ndrift and the N-type buried layer NBL;
3073, forming an N-type well region in the N-type drain drift region Ndrift;
3074, performing photoetching and ion implantation on the epitaxial layer EPI by using a PGRD photomask to form a P-type drain drift region Pdrift;
3075, a P-well region is formed in the P-drain drift region Pdrift.
Scheme four
Step 4071, performing photolithography and ion implantation on the EPI layer EPI by using a PGRD photomask to form a P-type drain drift region Pdrift;
step 4072, forming a P-type well region in the P-type drain drift region Pdrift;
step 4073, performing photolithography and ion implantation on the EPI layer EPI by using an NGRD photomask to form an N-type drain drift region Ndrift;
step 4074, performing a second ion implantation on the prefabricated P-type isolation structure PB below the N-type drain drift region Ndrift to form a P-type isolation structure PB between the N-type drain drift region Ndrift and the N-type buried layer NBL;
step 4075, an N-well region is formed in the N-drain drift region Ndrift.
The method for manufacturing the fully-isolated NLDMOS device comprises the steps of photoetching a dielectric layer to form a field effect oxide layer GO, photoetching an epitaxial layer EPI, carrying out first ion implantation to form a P-type isolation structure PB between a P-type drain drift region Pdrrift and an N-type buried layer NBL and a prefabricated P-type isolation structure PB between an N-type drain drift region Ndrift and an N-type buried layer NBL, then forming the P-type drain drift region Pdrrift and the N-type drain drift region Ndrift, then carrying out second ion implantation to an isolation structure below the N-type drain drift region Ndrift to form an isolation structure between the N-type drain drift region Ndrift and the N-type buried layer NBL, then forming the P-type drain drift region and the N-type drain drift region, and finally forming a Gate structure Gate, the P-type ion implantation region and the N-type ion implantation region. Therefore, the field effect oxide layer GO is defined by one mask plate, compared with the traditional P-type isolation structure without adding the formation steps of the mask plate, the sequence of forming the P-type isolation structure PB is changed, so that the etching process is not needed in the process of forming the P-type drain drift region Pdrift and the N-type drain drift region Ndrift, namely, compared with the prior art, the etching step in the process of forming the P-type drain drift region or the N-type drain drift region is at least omitted, the manufacturing process flow of the semiconductor device with the surface field effect oxide layer structure is simplified, and the production efficiency of the semiconductor device is improved.
After the Gate structure Gate is formed, the embodiment of the invention can further comprise the steps of forming a heavily doped P-type ion implantation area and an N-type ion implantation area to form a source drain area and extracting an electrode.
According to the manufacturing method of the fully-isolated NLDMOS device provided by the embodiment of the invention, the ion sources of the first ion implantation and the second ion implantation are the same and are both boron, and other P-type ion sources can also be adopted.
In order to form a better field effect oxide layer GO structure, according to the manufacturing method of the fully-isolated NLDMOS device provided by the embodiment of the present invention, the field effect oxide layer GO is a composite structure including an oxide and a nitride formed on a substrate. Wherein the oxide is silicon dioxide and the nitride is silicon nitride.
According to the idea of the invention, the PLDMOS device can be manufactured by adopting a process opposite to the manufacturing method of the full-isolation NLDMOS device, namely, the steps of forming the isolation structure between the PLDMOS device and the buried layer and then forming the drift region and the well region are firstly carried out, and the type of ion implantation in the implantation process is opposite to that of the NLDMOS device.
The embodiment of the invention also provides a manufacturing method of the full-isolation LDMOS power device, which comprises the following steps;
forming a field effect oxide layer GO of the NLDMOS device on the surface of an epitaxial layer EPI of the NLDMOS device region by adopting the manufacturing method of the full-isolation NLDMOS device;
and forming a field effect oxide layer GO of the PLDMOS device on the surface of the epitaxial layer EPI of the PLDMOS device region by adopting the manufacturing method of the PLDMOS device, which is the reverse process of the manufacturing method of the full-isolation type NLDMOS device.
The invention provides a method for manufacturing a full-isolation LDMOS power device, which comprises the steps of forming an isolation structure between a P-type drain drift region Pdrift, an N-type drain drift region Ndrift, a P-type well region and an N-type well region, and then forming a surface field oxide layer structure on a PLDMOS device and an NLDMOS device in semiconductor devices such as an LDMOS power device. Compared with the traditional PLDMOS device which is a trench-embedded field effect oxide layer, the on-resistance of the PLDMOS device is reduced, so that a semiconductor device with lower on-resistance can be formed, and the performance of the semiconductor device is improved. Compared with an LDMOS power device, the manufacturing method of the invention not only simplifies the manufacturing process flow of the semiconductor device, but also can manufacture the semiconductor devices of the PLDMOS device and the NLDMOS device which have the surface field effect oxide layer structure simultaneously.
The present invention is not limited to the above-described embodiments, and various changes and modifications within the scope of the present invention are within the scope of the present invention.
Claims (10)
1. A method for manufacturing a full-isolation NLDMOS device is characterized by comprising the following steps:
providing a substrate;
forming an N-type buried layer and a P-type buried layer on a substrate;
forming an epitaxial layer on the N-type buried layer and the P-type buried layer;
photoetching, etching and chemically mechanical grinding the epitaxial layer to form a shallow trench isolation structure;
depositing a dielectric layer on the surface of the epitaxial layer positioned above the N-type buried layer;
photoetching the dielectric layer by using the same mask plate to remove redundant dielectric layers to form a field effect oxide layer, photoetching the epitaxial layer and carrying out first ion implantation to form a P-type isolation structure between the P-type drain drift region and the N-type buried layer and form a prefabricated P-type isolation structure between the N-type drain drift region and the N-type buried layer;
photoetching and ion-implanting the epitaxial layer by adopting a PGRD photomask to form a P-type drain electrode drift region, photoetching and ion-implanting the epitaxial layer by adopting an NGRD photomask to form an N-type drain electrode drift region, simultaneously carrying out secondary ion-implantation on a prefabricated P-type isolation structure positioned below the N-type drain electrode drift region to form a P-type isolation structure between the N-type drain electrode drift region and an N-type buried layer, forming a P-type well region in the P-type drain electrode drift region and forming an N-type well region in the N-type drain electrode drift region;
a gate structure is formed over the field effect oxide layer.
2. The method of claim 1, wherein the steps of performing photolithography and ion implantation on the epitaxial layer using the PGRD mask to form a P-type drain drift region, performing photolithography and ion implantation on the epitaxial layer using the NGRD mask to form an N-type drain drift region, performing a second ion implantation on the pre-fabricated P-type isolation structure located below the N-type drain drift region to form a P-type isolation structure between the N-type drain drift region and the N-type buried layer, forming a P-type well region in the P-type drain drift region, and forming an N-type well region in the N-type drain drift region sequentially include:
firstly, photoetching and ion implantation are carried out on an epitaxial layer by adopting an NGRD photomask to form an N-type drain electrode drift region;
secondly, performing secondary ion implantation on the prefabricated P-type isolation structure positioned below the N-type drain drift region to form a P-type isolation structure between the N-type drain drift region and the N-type buried layer;
thirdly, photoetching and ion implantation are carried out on the epitaxial layer by adopting a PGRD photomask to form a P-type drain electrode drift region;
finally, a P-type well region is formed in the P-type drain drift region, and an N-type well region is formed in the N-type drain drift region.
3. The method of claim 1, wherein the steps of performing photolithography and ion implantation on the epitaxial layer using the PGRD mask to form a P-type drain drift region, performing photolithography and ion implantation on the epitaxial layer using the NGRD mask to form an N-type drain drift region, performing a second ion implantation on the pre-fabricated P-type isolation structure located below the N-type drain drift region to form a P-type isolation structure between the N-type drain drift region and the N-type buried layer, forming a P-type well region in the P-type drain drift region, and forming an N-type well region in the N-type drain drift region sequentially include:
firstly, photoetching and ion implantation are carried out on an epitaxial layer by adopting a PGRD photomask to form a P-type drain electrode drift region;
secondly, photoetching and ion implantation are carried out on the epitaxial layer by adopting an NGRD photomask to form an N-type drain electrode drift region;
thirdly, performing second ion implantation on the prefabricated P-type isolation structure positioned below the N-type drain drift region to form a P-type isolation structure between the N-type drain drift region and the N-type buried layer;
finally, a P-type well region is formed in the P-type drain drift region, and an N-type well region is formed in the N-type drain drift region.
4. The method of claim 1, wherein the steps of performing photolithography and ion implantation on the epitaxial layer using the PGRD mask to form a P-type drain drift region, performing photolithography and ion implantation on the epitaxial layer using the NGRD mask to form an N-type drain drift region, performing a second ion implantation on the pre-fabricated P-type isolation structure located below the N-type drain drift region to form a P-type isolation structure between the N-type drain drift region and the N-type buried layer, forming a P-type well region in the P-type drain drift region, and forming an N-type well region in the N-type drain drift region sequentially include:
firstly, photoetching and ion implantation are carried out on an epitaxial layer by adopting an NGRD photomask to form an N-type drain electrode drift region;
secondly, performing secondary ion implantation on the prefabricated P-type isolation structure below the N-type drain drift region to form a P-type isolation structure between the N-type drain drift region and the N-type buried layer;
thirdly, forming an N-type well region in the N-type drain electrode drift region;
then, photoetching and ion implantation are carried out on the epitaxial layer by adopting a PGRD photomask to form a P-type drain electrode drift region;
and finally, forming a P-type well region in the P-type drain drift region.
5. The method of claim 1, wherein the steps of performing photolithography and ion implantation on the epitaxial layer using the PGRD mask to form a P-type drain drift region, performing photolithography and ion implantation on the epitaxial layer using the NGRD mask to form an N-type drain drift region, performing a second ion implantation on the pre-fabricated P-type isolation structure located below the N-type drain drift region to form a P-type isolation structure between the N-type drain drift region and the N-type buried layer, forming a P-type well region in the P-type drain drift region, and forming an N-type well region in the N-type drain drift region sequentially include:
firstly, photoetching and ion implantation are carried out on an epitaxial layer by adopting a PGRD photomask to form a P-type drain electrode drift region;
secondly, forming a P-type well region in the P-type drain drift region;
thirdly, photoetching and ion implantation are carried out on the epitaxial layer by adopting an NGRD photomask to form an N-type drain electrode drift region;
then, performing second ion implantation on the prefabricated P-type isolation structure below the N-type drain drift region to form a P-type isolation structure between the N-type drain drift region and the N-type buried layer;
and finally, forming an N-type well region in the N-type drain drift region.
6. The method of manufacturing a fully-isolated NLDMOS device of claim 1 wherein said first and second ion implantations are performed with the same ion source.
7. The method of manufacturing a fully-isolated NLDMOS device of claim 6 wherein said ion source is boron.
8. The method of manufacturing a fully-insulated NLDMOS device of claim 1 wherein said field-effect oxide layer is a composite structure comprising an oxide and a nitride formed on a substrate.
9. The method of manufacturing a fully-isolated NLDMOS device of claim 8 wherein said oxide is silicon dioxide and said nitride is silicon nitride.
10. A method for manufacturing a full-isolation LDMOS power device is characterized by comprising the following steps;
forming a field effect oxide layer of the NLDMOS device on the surface of the epitaxial layer of the NLDMOS device region by adopting the manufacturing method of the full-isolation NLDMOS device as claimed in any one of claims 1 to 9;
and forming a field effect oxide layer of the PLDMOS device on the surface of the epitaxial layer of the PLDMOS device region by adopting the manufacturing method of the PLDMOS device.
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