CN113410305B - Radiation-resistant reinforced LDMOS transistor and preparation method - Google Patents
Radiation-resistant reinforced LDMOS transistor and preparation method Download PDFInfo
- Publication number
- CN113410305B CN113410305B CN202110663157.2A CN202110663157A CN113410305B CN 113410305 B CN113410305 B CN 113410305B CN 202110663157 A CN202110663157 A CN 202110663157A CN 113410305 B CN113410305 B CN 113410305B
- Authority
- CN
- China
- Prior art keywords
- layer
- sio
- hto
- gate
- silicon oxynitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000005855 radiation Effects 0.000 title claims abstract description 54
- 238000002360 preparation method Methods 0.000 title abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 97
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 97
- 239000010703 silicon Substances 0.000 claims abstract description 97
- 229910004298 SiO 2 Inorganic materials 0.000 claims abstract description 82
- 238000005121 nitriding Methods 0.000 claims abstract description 60
- 238000000034 method Methods 0.000 claims abstract description 45
- UBMXAAKAFOKSPA-UHFFFAOYSA-N [N].[O].[Si] Chemical compound [N].[O].[Si] UBMXAAKAFOKSPA-UHFFFAOYSA-N 0.000 claims abstract description 28
- 239000002131 composite material Substances 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 230000003014 reinforcing effect Effects 0.000 claims abstract description 17
- 230000008021 deposition Effects 0.000 claims abstract description 16
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000001301 oxygen Substances 0.000 claims abstract description 9
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 4
- 229920005591 polysilicon Polymers 0.000 claims abstract description 4
- 238000002513 implantation Methods 0.000 claims description 28
- 238000007254 oxidation reaction Methods 0.000 claims description 28
- 238000000151 deposition Methods 0.000 claims description 25
- 238000000137 annealing Methods 0.000 claims description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052757 nitrogen Inorganic materials 0.000 claims description 17
- 238000002955 isolation Methods 0.000 claims description 16
- 230000003647 oxidation Effects 0.000 claims description 16
- 238000009792 diffusion process Methods 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 14
- 238000001259 photo etching Methods 0.000 claims description 13
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- 238000006243 chemical reaction Methods 0.000 claims description 8
- 229910052681 coesite Inorganic materials 0.000 claims description 8
- 229910052906 cristobalite Inorganic materials 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 229910052682 stishovite Inorganic materials 0.000 claims description 8
- 229910052905 tridymite Inorganic materials 0.000 claims description 8
- 238000000206 photolithography Methods 0.000 claims description 7
- NCMAYWHYXSWFGB-UHFFFAOYSA-N [Si].[N+][O-] Chemical compound [Si].[N+][O-] NCMAYWHYXSWFGB-UHFFFAOYSA-N 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 238000009740 moulding (composite fabrication) Methods 0.000 claims description 2
- 230000002787 reinforcement Effects 0.000 abstract description 10
- 239000010410 layer Substances 0.000 description 188
- 238000005516 engineering process Methods 0.000 description 11
- 239000002245 particle Substances 0.000 description 9
- 230000015556 catabolic process Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 8
- 238000001459 lithography Methods 0.000 description 8
- 239000012535 impurity Substances 0.000 description 7
- 229910007991 Si-N Inorganic materials 0.000 description 6
- 229910006294 Si—N Inorganic materials 0.000 description 6
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 4
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 4
- 230000003471 anti-radiation Effects 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 238000011160 research Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000003090 exacerbative effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000005527 interface trap Effects 0.000 description 1
- XZWYZXLIPXDOLR-UHFFFAOYSA-N metformin Chemical compound CN(C)C(=N)NC(N)=N XZWYZXLIPXDOLR-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000000191 radiation effect Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
The invention discloses an LDMOS transistor with radiation resistance reinforcement and a preparation method thereof.A P well and a drift region are formed on the surface of a substrate in parallel; siO is laminated on the P well in turn 2 A silicon oxynitride layer and an HTO silicon oxynitride layer; a polycrystalline gate is formed on the HTO nitrogen oxygen silicon layer; a plurality of field oxides are formed on the drift region; a field ring is formed between the field oxygen; the field ring is formed with SiO 2 A thin silicon oxynitride layer; p-well, poly gate, field oxide and SiO 2 A dielectric layer is formed on the silicon oxynitride layer. The method comprises forming a P well and a drift region on the surface of a substrate; sequential growth of SiO on P-well 2 Nitriding the gate oxide layer to form SiO 2 Forming an HTO silicon oxynitride layer by nitriding a deposited HTO gate oxide layer, and forming SiO 2 The nitrogen-oxygen silicon layer and the HTO nitrogen-oxygen silicon layer form a composite gate dielectric structure, and polysilicon is deposited to form a gate; forming a field ring with reinforced total dose between field oxides on the drift region, sequentially growing SiO on the field ring 2 Thin oxide layer and nitrided to SiO 2 Forming a drift region reinforcing structure by the thin nitrogen oxygen silicon layer; in P-well, poly gate, field oxide and SiO 2 And a dielectric layer is formed on the silicon oxynitride layer by deposition.
Description
Technical Field
The invention belongs to the technical field of aerospace microelectronics, and particularly relates to a radiation-resistant reinforced LDMOS transistor and a preparation method thereof.
Background
With the development of large-scale projects such as manned aerospace and space exploration, the demands of integrated circuits such as anti-radiation high-performance linear power supplies, analog switches, high-voltage drivers and the like of aerospace microelectronic systems are urgent, and higher demands are put on the radiation resistance of the circuits. The circuits are manufactured by adopting a BCD (Bipolar, CMOS, DMOS) digital-analog mixing process. At present, the research on the radiation-resistant reinforcement technology of CMOS and bipolar devices is relatively mature, the serialized radiation-resistant CMOS and radiation-resistant bipolar integrated circuits are applied to satellites and space aircrafts, the research on the radiation-resistant technology of high-voltage LDMOS devices in BCD technology is relatively less, and the LDMOS reinforcement technology of a system is not formed, so that the conversion application of the BCD technology to the field of the radiation-resistant reinforcement integrated circuits is limited.
For the high-voltage LDMOS device, the high-voltage LDMOS device is mainly influenced by two effects of ionization total dose radiation and single particle radiation:
(1) The total dose radiation can generate electron-hole pairs in the gate oxide layer and the field oxide layer of the device, electrons drift out of the oxide layer or are recombined rapidly due to higher mobility, and holes are formed in Si/SiO 2 Trapped near the interface by traps at SiO 2 Positive charges are formed in the layer while the total dose of radiation also acts on the Si/SiO 2 The interface is introduced into an interface state, so that charge trapping is aggravated, the drift of the threshold voltage Vth of the device is finally caused, the characteristic parameters of the N-type channel LDMOS such as the reduction of the starting voltage of a field parasitic tube, the increase of leakage current, the reduction of breakdown voltage and the like are caused, and the circuit is disabled when serious.
(2) The single particle radiation can generate electron-hole pairs in the LDMOS device, and for the N-type channel LDMOS, electrons move along the track of incident particles to the drain electrode under the action of the electric field of the drift region, holes move to the grid electrode, and local transient field intensity is generated at the Si/SiO2 interface due to the charge collection effect. When the instantaneous increase in the electric field is large enough, it will cause the gate dielectric to burn out locally. On the other hand, when electron-hole pairs generated by heavy particle incidence form transient current through the transverse base region of the parasitic bipolar transistor flowing to the collector under the dual actions of drift and diffusion effect, the parasitic bipolar transistor is turned on, and the device burns out as the positive feedback current continuously increases.
In the prior art, in the aspect of improving the single particle radiation resistance, related researches propose to introduce a layer of P-type doped buried layer below the field oxide of the drift region of the N-type channel LDMOS device, and the generation rate of electron-hole pairs of the drift region is greatly reduced through transverse electric field modulation, so that the threshold value of single particle burnout (SEB) is improved. In the aspect of radiation reinforcement of total dose resistance, trap charge and interface state density are reduced mainly by manufacturing a thin gate oxide layer, so that the purpose of reducing the threshold voltage variation before and after irradiation is achieved, however, the thinning of the gate oxide layer is not beneficial to guaranteeing the single-particle gate penetration resistance of a device.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a radiation-resistant reinforced LDMOS transistor and a preparation method thereof, which are used for solving the problems of poor radiation resistance of the traditional LDMOS device, complex structure and high process difficulty of the traditional radiation-resistant reinforcing technology.
In order to achieve the above purpose, the present invention provides the following technical solutions:
an LDMOS transistor with radiation resistance reinforcement comprises a substrate;
a well and a drift region are formed on the surface of the substrate in parallel; siO is sequentially laminated on the well 2 A silicon oxynitride layer and an HTO silicon oxynitride layer; a polycrystalline grid is formed on the HTO nitrogen oxygen silicon layer;
a plurality of field oxides are formed on the drift region; a field ring is formed between the field oxygen; the field ring is formed with SiO 2 A thin silicon oxynitride layer; the well, the poly gate, the field oxide and SiO 2 A dielectric layer is formed on the thin SiON layer.
Preferably, the SiO 2 The silicon oxynitride layer is prepared by mixing SiO 2 The gate oxide layer is formed by nitriding, the SiO 2 The thickness of the oxynitride layer is in the range of
The HTO nitrogen oxygen silicon layer is formed by nitriding an HTO gate oxygen layer, and the HTO nitrogen oxygen silicon layer has the thickness of
The SiO is 2 The silicon oxynitride layer and the HTO silicon oxynitride layer form a radiation-resistant reinforced composite gate structure.
Preferably, the SiO2 thin SiON layer is formed by nitriding a SiO2 thin oxide layer, and the thickness of the SiO2 thin SiON layer is
Preferably, a source doped region and a body leading-out end doped region inside the well; a drain doped region is formed on the drift region.
Preferably, a metal is disposed on the dielectric layer.
A method for preparing an LDMOS transistor with radiation resistance reinforcement comprises the following steps,
forming a well and a drift region on the surface of the substrate;
sequential growth of SiO on wells 2 Nitriding the gate oxide layer to form SiO 2 Forming an HTO silicon oxynitride layer by nitriding a deposited HTO gate oxide layer, and forming SiO 2 The nitrogen-oxygen silicon layer and the HTO nitrogen-oxygen silicon layer form a composite gate dielectric structure, and polysilicon is deposited to form a gate;
forming field rings between field oxides on the drift region, sequentially growing SiO on the field rings 2 Thin oxide layer and nitrided to SiO 2 Forming a drift region reinforcing structure by the thin nitrogen oxygen silicon layer;
in wells, poly gates, field oxide and SiO 2 And a dielectric layer is formed on the thin nitrogen oxygen silicon layer by deposition.
Preferably, the method specifically comprises the following steps,
step 1, forming an isolation region on the surface of a silicon substrate;
step 4, growing SiO on the well 2 A gate oxide layer of SiO 2 Forming SiO after nitriding the gate oxide layer 2 Silicon oxynitride layer on SiO 2 Depositing an HTO gate oxide layer on the surface of the silicon oxynitride layer, nitriding the HTO gate oxide layer to form an HTO silicon oxynitride layer, and performing SiO 2 The silicon oxynitride layer and the HTO silicon oxynitride layer form a composite gate dielectric;
and 7, forming metal on the dielectric layer.
Preferably, the preparation of the composite gate structure specifically comprises the following processes,
step 1, forming SiO on the well by adopting an oxidation process 2 The temperature range of the oxidation reaction of the gate oxide layer is 800-1000 ℃;
step 4, HTO gate oxide layer is formed on N 2 NO or N 2 Nitriding and annealing are carried out in an O atmosphere environment to form an HTO silicon oxynitride layer, the nitriding temperature is between 850 and 1000 ℃, and the SiO is formed 2 And forming a composite gate dielectric structure by the nitrogen oxide silicon layer and the HTO nitrogen oxide silicon layer.
Preferably, the drift region reinforcing structure specifically comprises the steps of,
step 1, silicon nitride is deposited on the surface of a drift region as a mask, a window pattern of field oxidation is formed through photoetching and etching, and then oxidation reaction is carried out to form a field oxide layer;
step 4, at SiO 2 And forming a dielectric layer on the thin nitrogen oxygen silicon layer by a CVD method to form a drift region reinforcing structure.
Compared with the prior art, the invention has the following beneficial technical effects:
the invention provides a radiation-resistant reinforced LDMOS transistor, which is formed by adopting a composite gate dielectric structure and a drift region reinforcing process, wherein the composite gate dielectric can reduce the variation of threshold voltage before and after the total dose radiation of a device, improve the single-particle gate penetrating (SEGR) threshold value of the device, and nitride the original SiO 2 Si-H bonds and Si dangling bonds in the gate oxide layer are converted into firmer Si-N bonds to form silicon oxynitride, so that the radiation resistance of the gate oxide is improved. Meanwhile, the drift region reinforcing process can reduce the degradation of breakdown voltage after total dose radiation, and the invention can remarkably improve the reliability of the LDMOS device applied in a space radiation environment.
The invention provides a preparation method of an LDMOS transistor with radiation resistance reinforcement, which is an LDMOS process with a composite gate medium and a drift region reinforcement structure. Sequentially growing SiO in wells according to an improved process 2 Forming a gate oxide layer and SiO 2 Depositing an HTO gate oxide layer, forming an HTO nitrogen oxide silicon layer, and depositing polysilicon to form a gate; forming a field ring with enhanced total dose in the drift region, and then sequentially growing thin SiO according to an improved process 2 Layer, and at N 2 NO or N 2 And annealing in an O atmosphere environment to form a thin silicon oxynitride layer serving as a reinforcing oxide layer of the drift region, and further forming a dielectric layer thereon. The invention uses the original SiO 2 The single gate structure is adjusted to SiO 2 The composite gate structure of the SiON layer/HTO SiON layer can avoid SiO 2 The problem of leakage paths formed by line defects in the single-gate structure is solved, so that the reliability of gate oxide is improved, and the single-particle gate penetration resistance is improved. And, at SiO 2 And an annealing process of nitrogen-containing atmosphere is added after HTO growth, defects and traps in an oxide layer are reduced, the reliability of gate oxide can be further improved, and the threshold drift amount of a device after radiation can be reduced, so that the total dose radiation resistance is improved. The invention adjusts the original CVD medium structure into thin thermal oxide SiO 2 The composite dielectric structure of the silicon oxynitride/CVD dielectric can reduce the charge and interface trap of the total dose radiation at the interface of the drift region and the dielectric, reduce the influence of the radiation effect on the partial pressure of the field ring, and improve the degradation degree of the breakdown voltage of the device after radiation.
Drawings
FIG. 1 is a schematic diagram of a conventional LDMOS transistor (for example, an N-channel LDMOS);
FIG. 2 is a graph showing the effect of total dose radiation on the LDMOS (for example, an N-channel LDMOS);
FIG. 3 is a schematic diagram of an LDMOS structure with radiation-resistant reinforcement according to the present invention;
in the accompanying drawings: 1 is a trap; 2 is a drift region; 3 is field oxygen; 4 is a field ring; 5 is SiO 2 A gate oxide layer; 5' is SiO 2 A silicon oxynitride layer; 6 is an HTO gate oxide layer; 6' is an HTO silicon oxynitride layer; 7 is a polycrystalline grid; 8 is a source doped region; 9 is a body terminal doping region; 10 is a drain doped region; 11 is SiO 2 A thin oxide layer; 11' is SiO 2 A thin silicon oxynitride layer; 12 is a dielectric layer; 13 is a metal.
Detailed Description
The invention will now be described in further detail with reference to specific examples, which are intended to illustrate, but not to limit, the invention.
A typical conventional LDMOS device structure is shown in fig. 1 (an N-channel LDMOS is taken as an example). Under the radiation environment, the silicon oxide can be formed on the grid oxide SiO 2 Field oxide SiO 2 Electron-hole pairs are generated in the layer, the electrons being in SiO 2 The medium mobility is high and most of it is quickly removed from the oxide layer. The mobility of holes is slow, and the rest of holes are SiO-bonded with electrons 2 Absence of layerTrapping to form positive charge of oxide trap, and irradiation effect on SiO 2 Creating an interface state near the interface with silicon further exacerbating charge trapping. The influence on the gate oxide layer is mainly represented by threshold voltage drift and saturation current reduction, and the influence on the field oxide layer is mainly represented by field parasitic tube leakage, breakdown voltage reduction, and the like.
As shown in fig. 2 (taking an N-type channel LDMOS as an example), under the effect of total dose radiation, a large amount of positive charges are induced near the gate oxide layer and the field oxide layer of the LDNMOS device and the interface of the silicon below, which on one hand causes the effective concentration on the surface of the P-well to be reduced, resulting in the threshold voltage of the device to be reduced; on the other hand, the voltage division effect of the field ring is affected, so that the breakdown voltage of the device is reduced.
Aiming at the application requirement of the space radiation environment on the LDMOS device, the invention provides the LDMOS device structure of the composite gate and drift region reinforcing process, and SiO is grown in turn according to the improved process 2 Gate oxide layer 5, formation of SiO 2 A nitrogen-oxygen silicon layer 5', an HTO gate oxide layer 6 is deposited and an anti-radiation reinforced composite gate layer is formed through an annealing process of a nitrogen-containing atmosphere; a field ring 4 is formed on the surface by implantation over the drift region, over which SiO is formed 2 A thin oxide layer 11 and an annealing process is performed in a nitrogen-containing atmosphere to form SiO 2 A thin silicon oxynitride layer 11' is subsequently formed by CVD over which a dielectric layer 12 is formed.
After the process of the reinforcing structure is finished, the rest working procedures are finished according to the conventional process flow.
As shown in fig. 3, the structural schematic diagram of the radiation-resistant reinforced LDMOS device provided by the present invention sequentially includes:
a well 1 and a drift region 2 adjacent thereto;
a field ring 4 located inside the drift region 2 between the field oxides 3, 3;
SiO located above the well 1 2 Silicon oxynitride layer 5' on SiO 2 An HTO silicon oxynitride layer 6' over the silicon oxynitride layer 5', a poly gate 7 over the HTO silicon oxynitride layer 6 ';
a source doped region 8 and a body leading-out end doped region 9 which are positioned in the well 1;
a drain doped region 10 located inside the drift region 2;
SiO located above the drift region 2 2 A thin silicon oxynitride layer 11';
is positioned in the well 1, the polycrystalline grid 7, the field oxide 3 and the SiO 2 A dielectric 12 over the thin silicon oxynitride layer 11';
a metal 13 located inside and above the medium 12.
Growing SiO on silicon substrate in consideration of influence on reliability and radiation resistance of gate dielectric 2 The oxidation reaction temperature of the gate oxide layer 5 is generally 800-1000 ℃, and for LDMOS processes with different operating voltage requirements, siO 2 The thickness of the gate oxide layer 5 is generally
SiO 2 After the growth of the gate oxide layer 5 is completed, N 2 NO or N 2 Nitriding annealing is carried out in an O atmosphere environment to form SiO 2 The nitriding temperature of the SiON layer 5' is generally 850-1000 ℃ and the nitriding time is 30-60 min, and the original SiO can be obtained by nitriding 2 The Si-H bond and the Si dangling bond in the gate oxide layer 5 are converted into firmer Si-N bond to form silicon oxynitride, thereby improving the radiation resistance of the gate oxide.
In SiO 2 A layer of HTO gate oxide 6 is deposited on the surface of the SiON layer 5', and the HTO gate oxide 6' is formed by SiH 2 Cl 2 And N 2 O is formed by deposition reaction at 800-850 ℃ according to the volume ratio of 1 (5-10), and the thickness of the HTO grid oxide layer 6 is generally equal to that of LDMOS technology with different working voltage requirements
HTO gate oxide layer 6 is finally formed on N 2 NO or N 2 Nitriding annealing is carried out in an O atmosphere environment to form an HTO silicon oxynitride layer 6', for the LDMOS process, the nitriding temperature is generally 850-1000 ℃ and the nitriding time is 30-60 min, and the SiO is formed 2 The silicon oxynitride layer 5 'and the HTO silicon oxynitride layer 6' together form a radiation-resistant composite gate structure.
The processing technology for forming the radiation-resistant composite gate dielectric structure in the structure shown in fig. 3 comprises the following steps:
step 1: siO formation by oxidation process 2 The temperature of the oxidation reaction of the gate oxide layer 5 is generally 800-1000 ℃ and SiO for LDMOS technology 2 The thickness of the gate oxide layer 5 is
The oxidation process may be a dry oxidation or other oxidation process.
Step 2: siO (SiO) 2 After the growth of the gate oxide layer 5 is completed, N 2 NO or N 2 Nitriding annealing is carried out in an O atmosphere environment to form SiO 2 The nitriding temperature of the SiON layer 5' is generally 850-1000 ℃ and the nitriding time is 30-60 min, and the original SiO can be obtained by nitriding 2 The Si-H bond and the Si dangling bond in the gate oxide layer 5 are converted into more firm Si-N bond to form silicon oxynitride, thereby improving the reliability of gate oxide.
Step 3: in SiO 2 A layer of HTO gate oxide layer 6 is deposited on the 5' surface of the silicon oxynitride layer, and the HTO gate oxide layer 6 is formed by SiH 2 Cl 2 And N 2 O is formed by deposition reaction at 800-850 ℃ according to the volume ratio of 1 (5-10), and for LDMOS technology, the thickness of HTO gate oxide layer 6 is
Step 4: HTO gate oxide layer 6 is finally formed on N 2 NO or N 2 Nitriding annealing is carried out in an O atmosphere environment to form an HTO silicon oxynitride layer 6', for the LDMOS process, the nitriding temperature is generally 850-1000 ℃ and the nitriding time is 30-60 min, and the SiO is formed 2 The silicon oxynitride layer 5 'and the HTO silicon oxynitride layer 6' together form a radiation-resistant composite gate structure.
Forming field rings 4 on the surface of the drift region 2 through photoetching, injection, diffusion or annealing, wherein 1 or more injection windows of the field rings 4 can be formed according to different breakdown voltage requirements, the width of the field rings 4 is 2-6 mu m, and the interval between the field rings 4 is 4-10 mu m; forming a thin oxide layer on the field ring 4, wherein the oxidation temperature is set at 800-900 ℃, and SiO 2 The thickness of the thin oxygen layer 11 is
In SiO 2 After the formation of the thin oxygen layer 11, at N 2 NO or N 2 Nitriding annealing in O atmosphere environment to form SiO 2 The temperature of the silicon oxynitride layer 11' is 850-1000 ℃ and the time is 30-60 min.
And forming a dielectric layer 12, a metal layer and other structures on the silicon oxynitride layer by adopting a traditional LDMOS transistor process method.
The processing technology for forming the drift region reinforcing structure in the structure of fig. 3 comprises the following steps:
step 1: silicon nitride is deposited on the surface of the drift region 2 as a mask, a window pattern for field oxidation is formed through photoetching and etching, and then oxidation reaction is carried out to form field oxide 3. Defining an implantation window of the field ring 4 by photoetching, doping the surface of the N-type drift region 2 by ion implantation, wherein the implantation energy is generally 30-300 keV, and the implantation dosage is generally 1×10 14 /cm 2 ～1×10 15 /cm 2 And then diffusion activation is carried out on the injected impurities by combining thermal processes such as diffusion, annealing and the like.
Step 2: adopting dry oxidation or H with the volume ratio of 1 (1-2) 2 :O 2 Wet oxidation to form SiO 2 The temperature of the oxidation reaction of the thin oxide layer 11 is generally 800-1000 ℃ and the time is 30-120 min, and SiO 2 The thickness of the thin oxide layer 11 is
Step 3: siO (SiO) 2 After the growth of the thin oxygen layer 11 is completed, N 2 NO or N 2 High temperature nitriding annealing in O atmosphere environment to form SiO 2 The temperature of nitriding the thin silicon oxynitride layer 11' is generally 850-1000 ℃ for 30-60 min, and the original SiO can be nitrided 2 The Si-H bonds and Si dangling bonds in the thin oxide layer 11 are converted into firmer Si-N bonds, and silicon oxynitride is formed, so that the radiation resistance of the gate oxide is improved.
Step 4: in SiO 2 Thin silicon oxynitrideDielectric layer 12 is formed on layer 11' by CVD method, and dielectric layer 12 may be SiO 2 Or SiO 2 And a silicon nitride composite film layer.
The above is the whole process module of the anti-radiation composite gate and drift region reinforcing process, and the realization of the anti-radiation LDMOS transistor is not affected although the specific process flows of different production lines are different.
Example 1
The embodiment takes the trench isolation type SOI radiation-resistant reinforced LDNMOS process as an example, and comprises the following steps;
(1) Forming an isolation region;
and depositing silicon nitride on the surface of the top silicon layer of the silicon substrate on the insulator as a masking layer, defining an isolation region by photoetching, and taking the region outside the isolation region as an active region. Etching off the top silicon of the isolation region to form an isolation groove, and then depositing HDPSiO 2 Planarization by Chemical Mechanical Polishing (CMP) of the layer to polish away HDP SiO on the active region 2 A layer leaving HDPSiO in the isolation trench 2 And removing the silicon nitride masking layer through a wet etching process.
(2) Forming a drift region 2 and a field ring 4;
a drift region 2 is formed in the top-layer silicon by photolithography, implantation, diffusion processes. Silicon nitride is deposited on the surface of the drift region 2 as a mask, a window pattern of the field oxide 3 is formed through photoetching and etching, and then oxidation reaction is carried out to form the field oxide 3. An implantation window of the field ring 4 is defined between the field oxides 3 of the drift region 2 by lithography, and the surface of the drift region 2 is doped by ion implantation, the implantation of impurities is generally boron, the implantation energy is generally 30 keV-300 keV, and the implantation dosage is generally 1×10 14 /cm 2 ～1×10 15 /cm 2 Is then diffusion activated by thermal processes such as diffusion, annealing, etc.
For the N-channel LDNMOS of this embodiment, the drift region 2 is an N-type drift region, and the field ring 4 is a P-type field ring.
(3) Forming a well 1;
defining a pattern window of the trap 1 in the top silicon by photoetching, and carrying out P-type impurity injectionThe well 1 is formed by thermal diffusion. The implantation of impurity adopts boron, the implantation energy is controlled between 100keV and 300keV, and the implantation dosage is controlled at 1 multiplied by 10 12 /cm 2 ～1×10 13 /cm 2 The push-well temperature is controlled between 1100 ℃ and 1150 ℃.
For the N-channel LDNMOS of the present embodiment, well 1 is a P-well.
(4) Forming a composite gate dielectric;
growth of SiO on silicon substrate by dry oxidation 2 A gate oxide layer 5 for controlling the temperature of oxidation reaction at 800-1000 ℃ in consideration of the influence of radiation resistance, siO 2 The thickness of the gate oxide layer 5 is
SiO 2 After the growth of the gate oxide layer 5 is completed, N 2 NO or N 2 High temperature nitriding annealing in O atmosphere environment to form SiO 2 The nitriding temperature of the silicon oxynitride layer 5' is controlled between 850 and 1000 ℃ for 30 to 60 minutes, and the original SiO can be treated by nitriding 2 The Si-H bond and the Si dangling bond in the gate oxide layer 5 are converted into more firm Si-N bond to form silicon oxynitride, thereby improving the reliability of gate oxide.
In SiO 2 A layer of HTO gate oxide 6 is deposited on the surface of the silicon oxynitride layer 5', and the HTO gate oxide 6 is formed by SiH 2 Cl 2 And N 2 O is formed by deposition reaction at 800-850 ℃ according to the volume ratio of 1 (5-10), and the thickness of the HTO gate oxide layer 6 is
HTO gate oxide layer 6 is finally formed on N 2 NO or N 2 High-temperature nitriding annealing is carried out in an O atmosphere environment to form an HTO silicon oxynitride layer 6', the nitriding temperature is controlled between 850 ℃ and 1000 ℃ and the nitriding time is 30min to 60min, and SiO is formed 2 The silicon oxynitride layer 5 'and the HTO silicon oxynitride layer 6' together form a radiation-resistant composite gate structure.
(5) Forming a polycrystalline grid;
poly deposition and doping are performed and poly gate 7 is formed by poly lithography and etching.
Wherein the portion of the poly gate 7 covering the field region forms a field plate having a minimum length of 1 μm.
(6) The doping areas of the source electrode, the drain electrode and the body leading-out end are injected;
photolithography and implantation of the source doped region 8 and the body-leading-out doped region 9 are performed in the well 1, photolithography and implantation of the drain doped region 10 are performed in the drift region 2, and the implantation dose is controlled to be 1×10 15 /cm 2 On the order of (2).
For the N-channel LDNMOS of this embodiment, the source and drain doped regions are N-type and the body-leading-out doped region is P-type.
(7) And (3) forming a pore layer.
Including deposition of interlayer dielectric (Interlevel Dielectrics, ILD), planarization of dielectric layer CMP (Chemical Mechanical Polishing), lithography and etching of holes.
(8) Metallization and passivation.
Including hole filling, tungsten CMP planarization, metal deposition, lithography and etching, and finally passivation layer deposition and etching, to form a complete device.
For multilayer metal wiring, deposition and CMP planarization of the inter-metal dielectric layer (Intermetal Dielectrics, IMD) are also involved.
Example 2
The embodiment takes a field isolation type body silicon radiation-resistant reinforced LDPMOS process as an example, and comprises the following steps of;
(1) Forming an isolation region;
silicon nitride is deposited on the surface of a silicon substrate as a masking layer, a window pattern of an isolation field region is formed through photoetching and etching, then oxidation reaction is carried out to form a field oxide layer, a field oxide layer region is an isolation region, and a region between the field oxide layer region and the isolation region is an active region.
(2) Forming a drift region 2 and a field ring 4;
the drift region 2 is formed by photolithography, implantation, and diffusion steps. An implantation window of the field ring 4 is defined between the field oxides 3 in the drift region 2 by lithography, the surface of the drift region 2 is doped by ion implantation, the implantation of impurities is typically boron, and the implantation energy is typically 30KeV-300 keV, the implantation dose is generally 1×10 14 /cm 2 ～1×10 15 /cm 2 Is then diffusion activated by thermal processes such as diffusion, annealing, etc.
For the P-channel LDPMOS of the present embodiment, the drift region 2 is a P-type drift region, and the field ring 4 is an N-type field ring.
(3) Forming a well 1;
and defining a pattern window of the well 1 on the surface of the silicon substrate by photoetching, carrying out N-type impurity implantation, and forming the well 1 by thermal diffusion. The implantation impurity adopts phosphorus, the implantation energy is controlled between 100keV and 300keV, and the implantation dosage is controlled to be 1 multiplied by 10 12 /cm 2 ～1×10 13 /cm 2 The push-well temperature is controlled between 1100 ℃ and 1150 ℃.
For the P-channel LDPMOS of the present embodiment, well 1 is an N-well.
(4) Forming a composite gate dielectric;
growing SiO on silicon substrate by oxidation process 2 A gate oxide layer 5, in which the oxidation temperature is controlled to 800-1000 ℃ in consideration of the influence of the radiation resistance, siO 2 The thickness of the gate oxide layer 5 is
SiO 2 After the growth of the gate oxide layer 5 is completed, N 2 NO or N 2 Nitriding annealing is carried out in an O atmosphere environment to form SiO 2 The nitriding temperature of the silicon oxynitride layer 5' is controlled between 850 and 1000 ℃ for 30 to 60 minutes, and the original SiO can be treated by nitriding 2 The Si-H bond and the Si dangling bond in the gate oxide layer 5 are converted into more firm Si-N bond to form silicon oxynitride, thereby improving the reliability of gate oxide.
In SiO 2 A layer of HTO gate oxide 6 is deposited on the surface of the silicon oxynitride layer 5', and the HTO gate oxide 6 is formed by SiH 2 Cl 2 And N 2 O is formed by deposition reaction at 800-850 ℃ according to the volume ratio of 1 (5-10), and the thickness of the HTO gate oxide layer 6 is
HTO gate oxide layer 6 is finally formed on N 2 NO or N 2 Nitriding and annealing are carried out in an O atmosphere environment to form an HTO silicon oxynitride layer 6', the nitriding temperature is controlled between 850 ℃ and 1000 ℃ and the time is 30min to 60min, and SiO is formed 2 The silicon oxynitride layer 5 'and the HTO silicon oxynitride layer 6' together form a radiation-resistant composite gate structure.
(5) Forming a polycrystalline grid;
poly deposition and doping are performed and poly gate 7 is formed by poly lithography and etching.
Wherein the portion of the poly gate 7 covering the field region forms a field plate having a minimum length of 1 μm.
(6) The doping areas of the source electrode, the drain electrode and the body leading-out end are injected;
photolithography and implantation of the source doped region 8 and the body-leading-out doped region 9 are performed in the well 1, photolithography and implantation of the drain doped region 10 are performed in the drift region 2, and the implantation dose is controlled to be 1×10 15 /cm 2 On the order of (2).
For the P-channel LDPMOS of this embodiment, the source and drain doped regions are P-type and the body-leading-out doped region is N-type.
(7) And (3) forming a pore layer.
Including deposition of interlayer dielectric (Interlevel Dielectrics, ILD), planarization of dielectric layer CMP (Chemical Mechanical Polishing), lithography and etching of holes.
(8) Metallization and passivation.
Including hole filling, tungsten CMP planarization, metal deposition, lithography and etching, and finally passivation layer deposition and etching, to form a complete device.
For multilayer metal wiring, deposition and CMP planarization of the inter-metal dielectric layer (Intermetal Dielectrics, IMD) are also involved.
Claims (7)
1. An LDMOS transistor reinforced by radiation resistance is characterized by comprising a substrate;
a well (1) and a drift region (2) are formed on the surface of the substrate in parallel; siO is sequentially laminated on the well (1) 2 Silicon oxynitride layer (5') and HTO silicon oxynitrideA layer (6'); a polycrystalline gate (7) is formed on the HTO nitrogen oxygen silicon layer (6');
a plurality of field oxides (3) are formed on the drift region (2); a field ring (4) is formed between the field oxygen (3); siO is formed on the field ring (4) 2 A thin silicon oxynitride layer (11'); the well (1), the poly gate (7), the field oxide (3) and SiO 2 A dielectric layer (12) is formed on the thin nitrogen oxygen silicon layer (11');
the SiO is 2 The silicon oxynitride layer (5') is formed by depositing SiO 2 The gate oxide layer (5) is formed by nitriding, and the SiO is formed by 2 The thickness of the silicon oxynitride layer (5') is 200-600A;
the HTO nitrogen oxygen silicon layer (6 ') is formed by nitriding the HTO gate oxygen layer (6), and the thickness of the HTO nitrogen oxygen silicon layer (6') is 100-400A;
the SiO2 nitrogen oxygen silicon layer (5 ') and the HTO nitrogen oxygen silicon layer (6') form a radiation-resistant reinforced composite gate structure;
the SiO2 thin SiON layer (11 ') is formed by nitriding the SiO2 thin oxide layer (11), and the thickness of the SiO2 thin SiON layer (11') is 100-300A.
2. A radiation-hardened LDMOS transistor according to claim 1, characterized in that the source doped region (8) and the body-outlet doped region (9) inside the well (1); a drain doped region (10) is formed on the drift region (2).
3. A radiation-hardened LDMOS transistor according to claim 1, characterized in that the dielectric layer (12) is provided with a metal (13).
4. A method for preparing an LDMOS transistor reinforced by radiation resistance is characterized by comprising the following steps,
forming a well (1) and a drift region (2) on the surface of a substrate;
sequentially growing SiO on the well (1) 2 Gate oxide layer (5)Nitriding to form SiO 2 A silicon oxynitride layer (5 '), depositing an HTO gate oxide layer (6), and nitriding to form an HTO silicon oxynitride layer (6'), siO 2 The nitrogen-oxygen silicon layer (5 ') and the HTO nitrogen-oxygen silicon layer (6') form a composite gate dielectric structure, and the polysilicon (7) is deposited to form a gate;
a field ring (4) is formed between the field oxides (3) on the drift region (2), siO is grown on the field ring (4) in turn 2 Thin oxide layer (11) and nitrided to SiO 2 The thin silicon oxynitride layer (11') forms a drift region reinforcing structure;
in the well (1), the polycrystalline gate (7), the field oxide (3) and SiO 2 A dielectric layer (12) is deposited on the thin SiON layer (11').
5. The method for fabricating a radiation-hardened LDMOS transistor as defined in claim 4, comprising the steps of,
step 1, forming an isolation region on the surface of a silicon substrate;
step 2, forming a drift region (2) on a silicon substrate with an isolation region formed by photolithography, implantation and diffusion processes, forming a plurality of field oxides (3) on the drift region (2), forming field rings (4) between the field oxides (3), and forming SiO on the field rings (4) 2 A thin oxide layer (11) of SiO 2 Nitriding the thin oxide layer (11) to form SiO 2 A thin silicon oxynitride layer (11') forming a drift region reinforcing structure;
step 3, forming a well (1) on the surface of the silicon substrate through photoetching and ion implantation;
step 4, growing SiO on the well (1) 2 A gate oxide layer (5) of SiO 2 Forming SiO after nitriding the gate oxide layer (5) 2 A silicon oxynitride layer (5') formed on SiO 2 Depositing an HTO gate oxide layer (6) on the surface of the silicon oxynitride layer (5 '), nitriding the HTO gate oxide layer (6) to form an HTO silicon oxynitride layer (6'), and forming SiO 2 The nitrogen-oxygen silicon layer (5 ') and the HTO nitrogen-oxygen silicon layer (6') form a composite gate medium;
step 5, forming a polycrystalline gate (7) on the HTO nitrogen oxygen silicon layer (6');
step 6 of the method, in which,well (1), poly gate (7), field oxide (3) and SiO 2 A dielectric layer (12) is formed on the thin nitrogen oxygen silicon layer (11');
and 7, forming a metal (13) on the dielectric layer (12).
6. The method for fabricating a radiation-hardened LDMOS transistor as recited in claim 4, wherein said fabricating of said composite gate dielectric structure comprises the steps of,
step 1, forming SiO on the well (1) by adopting an oxidation process 2 The temperature range of the oxidation reaction of the gate oxide layer (5) is 800-1000 ℃;
step 2, siO 2 After the growth of the gate oxide layer (5) is completed, the gate oxide layer is grown on N 2 NO or N 2 Nitriding annealing is carried out in an O atmosphere environment to form SiO 2 The nitriding temperature of the silicon oxynitride layer (5') ranges from 850 ℃ to 1000 ℃ and the nitriding time ranges from 30min to 60min;
step 3, at SiO 2 Depositing an HTO gate oxide layer (6) on the surface of the nitrogen oxide silicon layer (5'), wherein the HTO gate oxide layer (6) is formed by SiH 2 Cl 2 And N 2 O is generated by deposition reaction at 800-850 ℃ according to the volume ratio of (1) (5-10);
step 4, HTO gate oxide layer (6) is formed on N 2 NO or N 2 Nitriding annealing is carried out in an O atmosphere environment to form an HTO nitrogen oxygen silicon layer (6'), the nitriding temperature ranges from 850 ℃ to 1000 ℃ and SiO is formed 2 The silicon oxynitride layer (5 ') and the HTO silicon oxynitride layer (6') form a composite gate dielectric structure.
7. The method of manufacturing a radiation-hardened LDMOS transistor as claimed in claim 4, wherein said drift region reinforcing structure comprises the steps of,
step 1, silicon nitride is deposited on the surface of a drift region (2) as a mask, a window pattern for field oxidation is formed through photoetching and etching, and then oxidation reaction is carried out to form a field oxide layer (3);
step 2, forming SiO on the drift region (2) by adopting an oxidation process 2 Thin oxide layer (11), oxidationThe temperature range of the reaction is 800-1000 ℃;
step 3, siO 2 After the growth of the thin oxide layer (11) is completed, the thin oxide layer is grown on the surface of N 2 NO or N 2 High temperature nitriding annealing in O atmosphere environment to form SiO 2 The temperature range of nitriding of the thin silicon oxynitride layer (11') is 850-1000 ℃ and the time is 30-60 min;
step 4, at SiO 2 A dielectric layer (12) is formed on the thin silicon oxynitride layer (11') by a CVD method to form a drift region reinforcing structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110663157.2A CN113410305B (en) | 2021-06-15 | 2021-06-15 | Radiation-resistant reinforced LDMOS transistor and preparation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110663157.2A CN113410305B (en) | 2021-06-15 | 2021-06-15 | Radiation-resistant reinforced LDMOS transistor and preparation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113410305A CN113410305A (en) | 2021-09-17 |
| CN113410305B true CN113410305B (en) | 2023-07-04 |
Family
ID=77684071
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110663157.2A Active CN113410305B (en) | 2021-06-15 | 2021-06-15 | Radiation-resistant reinforced LDMOS transistor and preparation method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113410305B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113903791A (en) * | 2021-12-09 | 2022-01-07 | 广州粤芯半导体技术有限公司 | Semiconductor device and method for manufacturing the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102446733A (en) * | 2011-12-08 | 2012-05-09 | 上海先进半导体制造股份有限公司 | Power device with high-voltage radio-frequency lateral diffusion structure and production method of power device |
| CN108807502A (en) * | 2018-06-08 | 2018-11-13 | 上海华虹宏力半导体制造有限公司 | A kind of manufacturing method of NLDMOS device and LDMOS power devices |
| CN112382656A (en) * | 2020-11-13 | 2021-02-19 | 西安微电子技术研究所 | Lateral diffusion MOS field effect transistor and preparation method thereof |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7345342B2 (en) * | 2001-01-30 | 2008-03-18 | Fairchild Semiconductor Corporation | Power semiconductor devices and methods of manufacture |
| KR100788758B1 (en) * | 2006-02-06 | 2007-12-26 | 양재우 | low-voltage organic thin film transistor and fabrication method thereof |
| CN102054774B (en) * | 2009-10-28 | 2012-11-21 | 无锡华润上华半导体有限公司 | VDMOS (vertical double diffused metal oxide semiconductor) transistor compatible LDMOS (laterally diffused metal oxide semiconductor) transistor and manufacturing method thereof |
| US9659981B2 (en) * | 2012-04-25 | 2017-05-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Backside illuminated image sensor with negatively charged layer |
| JP6216142B2 (en) * | 2012-05-28 | 2017-10-18 | キヤノン株式会社 | Manufacturing method of semiconductor device |
| US20140264588A1 (en) * | 2013-03-14 | 2014-09-18 | Taiwan Semiconductor Manufacturing Co. Ltd. | Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) with Step Oxide |
| CN104576359B (en) * | 2013-10-23 | 2017-10-27 | 无锡华润上华科技有限公司 | The preparation method of power diode |
| US10050115B2 (en) * | 2014-12-30 | 2018-08-14 | Globalfoundries Inc. | Tapered gate oxide in LDMOS devices |
| US9929144B2 (en) * | 2016-04-15 | 2018-03-27 | International Business Machines Corporation | Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor |
| CN112510080B (en) * | 2020-11-30 | 2023-06-06 | 西安微电子技术研究所 | Radiation reinforcing structure of single particle high voltage resistant MOS field effect transistor and preparation method |
-
2021
- 2021-06-15 CN CN202110663157.2A patent/CN113410305B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102446733A (en) * | 2011-12-08 | 2012-05-09 | 上海先进半导体制造股份有限公司 | Power device with high-voltage radio-frequency lateral diffusion structure and production method of power device |
| CN108807502A (en) * | 2018-06-08 | 2018-11-13 | 上海华虹宏力半导体制造有限公司 | A kind of manufacturing method of NLDMOS device and LDMOS power devices |
| CN112382656A (en) * | 2020-11-13 | 2021-02-19 | 西安微电子技术研究所 | Lateral diffusion MOS field effect transistor and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113410305A (en) | 2021-09-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10062759B2 (en) | Silicon carbide semiconductor device and method for manufacturing same | |
| US9466700B2 (en) | Semiconductor device and method of fabricating same | |
| US6869848B2 (en) | Method of manufacturing flash memory device | |
| CN102194885B (en) | N-type buried-channel silicon carbide metal oxide semiconductor field effect transistor (DEMOSFET) device and preparation method thereof | |
| US8125044B2 (en) | Semiconductor structure having a unidirectional and a bidirectional device and method of manufacture | |
| US9306007B2 (en) | Semiconductor device and method for manufacturing the same | |
| CN110518070B (en) | Silicon carbide LDMOS device suitable for monolithic integration and manufacturing method thereof | |
| US7919801B2 (en) | RF power transistor structure and a method of forming the same | |
| CN103782386A (en) | Power MOSFET with integrated gate resistor and diode-connected MOSFET | |
| CN113410305B (en) | Radiation-resistant reinforced LDMOS transistor and preparation method | |
| JPS62155552A (en) | Simultaneous manufacture of bipolar transistor and cmos transistor | |
| US8133783B2 (en) | Semiconductor device having different structures formed simultaneously | |
| CN113690320B (en) | Vertical DMOSFET (bipolar diffused Metal oxide semiconductor field Effect transistor), preparation method thereof and BCD (Bipolar complementary Metal-oxide-semiconductor field Effect transistor) device | |
| CN112510081B (en) | Reinforcing structure and preparation method of radiation-resistant groove type MOS (metal oxide semiconductor) tube for satellite | |
| JPS62156873A (en) | Semiconductor device | |
| CN108807502A (en) | A kind of manufacturing method of NLDMOS device and LDMOS power devices | |
| CN111987073B (en) | Neutron irradiation-based anti-irradiation reinforced SOI device and preparation method thereof | |
| JP4304779B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN110854076B (en) | HTO/SiO for improving gate oxide reliability and radiation resistance2Composite gate CMOS device and process | |
| CN104347403A (en) | Manufacturing method of insulated gate bipolar transistor | |
| CN105161526B (en) | The method for improving vertical conductive structure SiC MOSFET channel mobilities | |
| TWI225306B (en) | Method of forming double junction region and method of forming transfer transistor using the same | |
| KR100682178B1 (en) | Method for manufacturing CMOS | |
| CN109950306B (en) | VDMOS device with total dose irradiation resistance and manufacturing method thereof | |
| JPH0318064A (en) | Aluminum-boron p well |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |