CN106531218A - Bit line voltage conversion driving and current testing circuit - Google Patents
Bit line voltage conversion driving and current testing circuit Download PDFInfo
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- CN106531218A CN106531218A CN201610988434.6A CN201610988434A CN106531218A CN 106531218 A CN106531218 A CN 106531218A CN 201610988434 A CN201610988434 A CN 201610988434A CN 106531218 A CN106531218 A CN 106531218A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
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Abstract
The invention relates to a bit line voltage conversion driving and current testing circuit. The bit line voltage conversion driving and current testing circuit comprises a master-slave flip-flop, a voltage logical selection driving circuit and a current type sensitive amplifier circuit; the master-slave flip-flop receives input signals, and outputs digital signals obtained by sampling of the input signals to the voltage logical selection driving circuit; the voltage logical selection driving circuit receives the digital signals and input control signals, and obtains level signals for driving a bit line and a source of a FLASH unit through on-off selection of logical signals and data stored by an internal latch; and the current type sensitive amplifier circuit receives and amplifies the level signals, and outputs logical high and low levels used for driving bit line voltage and testing bit line current. By means of the bit line voltage conversion driving and current testing circuit disclosed by the invention, drains and sources of storage unit arrays in different columns can be randomly driven by utilizing high levels and low levels; therefore, coupling of capacitors among the storage unit arrays can be reduced; the fact that a FLASH storage unit has relatively high reliability in programming and erasing operations can be ensured, so that the FLASH storage unit can work rapidly and stably; and the performance of the while circuit system is improved.
Description
Technical field
The present invention relates to the driving and current testing circuit in digital circuit, more particularly to digital circuit.
Background technology
FPGA (field programmable gate array) be modern communication technology, electronic technology, computer technology, in automatic technology
Widely used important tool.FLASH memory is a kind of novel non-volatilization semiconductor memory, and it combines other storages
The advantage of device, with high density, low cost and the characteristics of high reliability.And the fpga chip based on FLASH, then it is the two is organic
Ground combines, it is achieved thereby that high density storage and transfer function.As this chip has low cost, storage density big
Feature, has been widely used for every field, including PC and peripheral hardware, telecommunications switch, network interconnection apparatus, network interconnection, instrument and meter, vapour
Car electronics, while also including emerging voice, image, data storage class product.
Bit-line voltage conversion with regard to FPGA and memory at present drives the complex structure with current testing circuit, during work
Power consumption it is excessive, data propagation delay time is excessive, is unsuitable to apply to extensive, low-power consumption, the IC-components of high speed
Among structure.
The content of the invention
For above-mentioned technical deficiency, the present invention proposes a kind of bit-line voltage conversion of FPGA based on FLASH units and drives
Dynamic and current testing circuit, can rapidly and accurately provide two kinds of level needed for bit line, and can test and be connected with bit line
FLASH units in size of current.
The technical solution adopted for the present invention to solve the technical problems is：Bit-line voltage conversion drives and testing current electricity
Road, including：
Master-slave flip-flop, receives input signal, and the data signal for obtaining of sampling to which export to voltage logic and select to drive
Dynamic circuit；
Voltage logic selects drive circuit, receives the control signal of data signal and input, and is deposited by Internal latches
The switch of the data and logical signal of storage is selected, and obtains the level signal of the bit line and source electrode of driving FLASH units；
Current-type sensitive amplifier circuit, receives level signal and is amplified and exports logic low and high level for bit line electricity
The driving of pressure and the test of bit line current.
The voltage logic selects drive circuit to include PMOS, transmission gate, latch, NMOS tube, decoding switch circuit；
The source electrode of PMOS 3 is connected with power supply, the connection of the output control terminal of grid and latch, drain electrode and PMOS 2
Source electrode connects；The grid of PMOS 2 selects the input H5_9 of drive circuit, drain electrode and the first of transmission gate as voltage logic
Transmission end connects；
Two control ends of transmission gate select input H5_4, H5_8 of drive circuit, transmission respectively as voltage logic
Second transmission end of door selects output end BL of drive circuit as voltage logic；
The pulse signal end of latch selects the input H5_7 of drive circuit, the input of latch as voltage logic
It is connected with the source of decoding switch circuit, the input control end of latch is connected with the control end of decoding switch circuit.
The decoding switch circuit includes NMOS tube 4, NMOS tube 5 and NMOS tube 6, NMOS tube 8, NMOS tube 9 and NMOS tube
10；
The grid of NMOS tube 4 is connected with the input control end of latch as control end, grounded drain, source electrode and NMOS tube
5 source electrode connection；The grid of NMOS tube 5 as voltage logic select drive circuit input H5_6, the drain electrode of NMOS tube 5 with
The drain electrode of NMOS tube 6 selects output end SL of drive circuit as voltage logic, and is connected with the first transmission end of transmission gate；
The grid of NMOS tube 6 selects the input H5_5 of drive circuit, source ground as voltage logic；
The drain electrode of NMOS tube 9 is connected with the input of latch, and grid is connected with the grid of NMOS tube 8, and as voltage
Logic selects the input ADD of drive circuit；The source electrode of NMOS tube 9 is connected with the drain electrode of NMOS tube 10, the source electrode of NMOS tube 10
Ground connection, grid are connected with the output end of master-slave flip-flop；The source electrode of NMOS tube 8 is that output end OUT is sensitive for connecting current mode
Amplifier, drain electrode are connected with the second transmission end of transmission gate.
The Current-type sensitive amplifier circuit includes current comparator, PMOS and phase inverter；
Two offset sides of the current comparator are respectively used to connect external control signal；The input IN of current comparator
Output end OUT of drive circuit is selected to be connected with voltage logic, output end is connected with the input of phase inverter；
The input of phase inverter is connected with the drain electrode of PMOS 33, and the source electrode of PMOS 33 is connected with power supply, and grid is used for
Connection external control signal；The output end of phase inverter is used to connect FLASH units.
The current comparator includes PMOS and NMOS tube；PMOS 6, the source electrode of PMOS 7 are connected with power supply, grid
Interconnection, drain electrode is drained with NMOS tube 11 respectively, the drain electrode of NMOS tube 12 is connected；11 grid of NMOS tube, 12 grounded-grid of NMOS tube,
11 source electrode of NMOS tube is connected with current loading circuit, input IN of 12 source electrode of NMOS tube as current comparator；The PMOS
The grid of pipe 6 is connected with drain electrode；11 grid of the NMOS tube is used as offset side H5_3；
Current loading circuit includes three NMOS tubes；The grid of NMOS tube 22, the grid of NMOS tube 23 are connected with power supply,
24 grid of NMOS tube is used as offset side H5_2；The drain electrode of NMOS tube 22 is connected with the source electrode of NMOS tube 11, source electrode and NMOS tube 24
Drain electrode connection, the source electrode of NMOS tube 24 is connected with the drain electrode of NMOS tube 23, the source ground of NMOS tube 23.
The invention has the advantages that and advantage：
There is provided a kind of new bit-line voltage conversion driving circuit, it is possible to use two kinds of different low and high levels are driven at random
The drain electrode of the memory cell array of dynamic different lines and source electrode, so as to reduce the coupling of electric capacity between memory cell array, it is ensured that
FLASH memory cell, works with higher reliability in programming, erasing operation with enabling FLASH fast and stables, improves
The performance of whole circuit system.
Description of the drawings
Fig. 1 is the programming of the FPGA based on FLASH units of an embodiment of the present invention, erasing bit-line voltage conversion driving
Produce the theory diagram of circuit；
Fig. 2 is a kind of circuit theory diagrams of implementation of master-slave flip-flop in circuit block diagram shown in Fig. 1；
Fig. 3 is that a kind of circuit of implementation of voltage logic transmission selection drive circuit in circuit block diagram shown in Fig. 1 is former
Reason figure；
Fig. 4 is a kind of circuit theory diagrams of implementation of Current-type sensitive amplifier circuit in circuit block diagram shown in Fig. 1.
Specific embodiment
With reference to embodiment, the present invention is described in further detail.
The invention provides a kind of bit-line levels conversion of FPGA based on FLASH drives and current testing circuit, including
The master-slave flip-flop sampled by input signal；Selected for control voltage logic according to the signal of master-slave flip-flop output
Whether the output for selecting drive circuit changes state；Voltage logic selects drive circuit, is configured to according to its internal port input
Control signal, the data stored by Internal latches and the switch of logical signal are selected, and obtain driving the bit line of FLASH units
With the level signal of source electrode；Current-type sensitive amplifier circuit, is configured to the electricity for testing the FLASH units being connected with bit line
Flow valuve, and export logic low and high level.Wherein one in FLASH ten bit lines of memory cell are selected, the circuit is driven
When, can rapidly and accurately provide two kinds of level required for the bit line, it is ensured that the reliability of system, meet many to greatest extent
Plant based on the bit-line voltage conversion drive module in the FPGA system of FLASH, be simple in structure and convenient in use.
The bit-line voltage conversion of the FPGA based on FLASH units provided according to the present invention drives test circuit to include：It is main
Slave flipflop, voltage logic select drive circuit, Current-type sensitive amplifier.Master-slave flip-flop is configured to adopt input signal
Sample, the sampled signal for obtaining are input into voltage logic and select drive circuit, used as the control signal of write Internal latches " 0 "；
Voltage logic selects drive circuit according to the control signal of its internal port input, on the one hand obtains driving the level signal of wordline
BL, SL, on the other hand make the bit line of the FLASH units of outside be connected to one with the Current-type sensitive amplifier input of inside
Rise；Current-type sensitive amplifier exports logic level by detecting the electric current of FLASH units.
In some embodiments, master-slave flip-flop is combined by a series of gates.
In some embodiments, voltage logic selects drive circuit to include a latch and some logical transport door electricity
Road, be adapted to provide for needed for bit line being respectively used to programming, two kinds of level of erase process.
In some embodiments, voltage logic selects drive circuit according to the assignment of its port control signal, selects to use
In programming, the bit-line voltage of erase process export.
In some embodiments, Current-type sensitive amplifier is connected with bit line BL, is adapted to detect for the electric current of FLASH units
Value.
Bit-line voltage conversion drives and current testing circuit, including：
Master-slave flip-flop, receives input signal, and and export according to the data signal obtained to the sampling of input signal；
Voltage logic selects drive circuit, is configured to the control signal according to its internal port input, by inner lock storage
The switch of the data and logical signal of device storage is selected, and obtains the level signal of the bit line and source electrode of driving FLASH units；
Current-type sensitive amplifier circuit, is configured to the current value for testing the FLASH units being connected with bit line, and defeated
Go out logic low and high level.
Driven and current testing circuit based on the bit-line voltage conversion of the FPGA of FLASH units, wherein principal and subordinate triggering
Device is combined by gate, voltage logic select drive circuit combined by Internal latches and simple logical transport door and
Into the structure of Current-type sensitive amplifier does the telescopic cathode-input amplifier structure for loading using current source.
Drive circuit, wherein Internal latches is selected to be used for storing based on the bit-line voltage logic of the FPGA of FLASH units
Data, logical transport door are used for controlling and transmission signal.
Driven and current testing circuit based on the bit-line voltage conversion of the FPGA of FLASH units, wherein principal and subordinate triggering
During the signal input voltage logic of device output selects the grid of input 10 transmission gate of NMOS of drive circuit, input is constituted
The control signal of logical zero, among " 0 " write voltage logic is selected drive circuit, and stores in latch.
Driven and current testing circuit based on the bit-line voltage conversion of the FPGA of FLASH units, wherein the voltage logic
Select drive circuit to include latch and transmission logic gate circuit, be adapted to provide for being respectively used to needed for bit line and program, wiped
Two kinds of level of journey.
Driven and current testing circuit based on the bit-line voltage conversion of the FPGA of FLASH units, wherein the voltage logic
Select drive circuit that the assignment of the control port signal for selecting drive circuit is transmitted according to the voltage logic, select for compiling
Journey, the bit line of erase process and source voltage are simultaneously exported.
Driven and current testing circuit based on the bit-line voltage conversion of the FPGA of FLASH units, wherein the current mode is clever
Quick amplifier circuit, according to the assignment and circuit structure of the control port signal, the FLASH being connected with bit line for test is mono-
The current value of unit, and export logic low and high level.
Fig. 1 is the bit-line voltage conversion driving circuit structure of the FPGA based on FLASH units of an embodiment of the present invention
Schematic diagram.
As shown in figure 1, the drive circuit includes that master-slave flip-flop 10, voltage logic selects drive circuit 20 and current mode spirit
Quick amplifier 30.
Master-slave flip-flop 10 is set to sample input signal, is output as voltage logic and selects drive circuit 20 to provide
Control signal.Voltage logic selects drive circuit 20 to be set to signal and other logic controls according to the output of master-slave flip-flop 10
Signal processed coordinates jointly, and then carries out conversion of the voltage between high and low level, provides for output bit-line BL, source S L signal
Suitable low and high level.
Voltage logic select drive circuit 20 be set to according to H5_9, H5_8, H5_7, H5_6, H5_5, H5_4, ADD etc. its
The logical combination of the input signal of internal port, is the one kind in selecting two kinds of level in programming, erasing, respectively as driving
The output signal of FLASH memory cell bit line and source level.
The circuit that Fig. 2 show schematically show a kind of implementation of master-slave flip-flop 10 in circuit block diagram shown in Fig. 1 is former
Reason figure.
As shown in Fig. 2 according to a kind of embodiment, master-slave flip-flop circuit 10 is combined by a series of gates.Its
In, port RESET1, RESET2, RESET3 are the enable signals from outside input master-slave flip-flop 10, CLK input sample clocks
Signal, the frequency of the sampled clock signal are arranged according to circuit specific function to be realized, DIN input sample input signals, by
Master flip-flop is sampled to which, slave flipflop output signal H5_1_O, selects one of drive circuit 20 as voltage logic
Input.
Wherein, CLK realizes positive inverted output signal by a phase inverter, respectively as master flip-flop and slave flipflop when
Clock signal, realizes clock sampling function；Remaining NAND gate and nor gate constitute touching for feedback arrangement known in the art
Device is sent out, the function of data register is realized.
Fig. 3 show schematically show a kind of realization side of voltage logic selection drive circuit 20 in circuit block diagram shown in Fig. 1
The circuit theory diagrams of formula.Wherein, VPPH power supplys are the high voltages provided after stable by external analog charge pump circuit.
As shown in figure 3, voltage logic select drive circuit 20 input control signal include port H5_9, H5_8, H5_7,
The signal of H5_6, H5_5, H5_4, ADD input.Wherein, port H5_9 is input into additional enable signal, port H5_8 and port H5_4
Additional enable signal is input into, decides whether BL, SL link together by the switch of controlling transmission door, port H5_6 and port
H5_5 is input into additional enable signal, source signal can be fixed as logical zero, and H5_7 input applying pulse signals in port are used
By the data dump in latch, port ADD is input into additional enable signal, determines whether voltage logic selects drive circuit 20
Normal work, port V6_10 inputs are the output of slave flipflop 10, decide whether internally latch transmission " 0 " data.As schemed
Shown in 1, above-mentioned port selects all to be drawn outside drive circuit 20 in voltage logic, to use during test circuit.Voltage
It is BL, SL that logic selects the output signal of drive circuit 20, is ultimately connected to the bit line and source voltage of FLASH memory cell
On, and output signal OUT is when being to be operated in test pattern, and the electric current of FLASH memory cell is detected by being connected with bit line BL
Value.
As shown in figure 3, driving voltage VPPH is input into the source electrode of PMOS PMOS 3, the drain electrode of PMOS 3 is connected to PMOS
2 source electrode, it is output port SL that the drain electrode of PMOS 2 is accessed in transmission gate one end of PMOS 1 and NMOS 7 compositions, and other end connects
Output port BL；Port H5_9 is connected into the grid of PMOS 2, and port H5_8 is connected into the grid of PMOS 1, and port H5_4 is connected into
The grid of NMOS7, the logical action that these pipes are constituted is that driving voltage VPPH is passed to certain one end of BL or SL.
PMOS PMOS 5, PMOS 4 and NMOS tube NMOS 3, NMOS 4 and NMOS 1 constitute latch circuit, end
Mouth H5_7 is connected into the grid of NMOS 1, and it provides a narrow high level pulse signal, for writing for latch next time
Enter the operation that new data are zeroed out.
The grid of PMOS 5 and NMOS 3 and the gate interconnection of PMOS 3, the drain electrode of PMOS 4 and NMOS 2, i.e. latch
Output be connected into NMOS 4 grid and NMOS 9 drain electrode, the source electrode of NMOS 5 is connected with the drain electrode of NMOS 4, NMOS's 5
Drain electrode is connected with the drain electrode of NMOS 6, is connected to output port SL；Port H5_6 is connected into the grid of NMOS 5, and port H5_5 is connected into
The grid of NMOS 6, by the selection of control signal, can be by SL clampers to earth signal.
The source electrode of NMOS 9 is connected with the drain electrode of NMOS 10, the grid of NMOS 9 and the gate interconnection of NMOS 8, NMOS 8
Drain electrode be connected to output end BL, source electrode is connected to output end OUT；Port V6_10 is connected into the grid of NMOS 10, and it derives from principal and subordinate
The output signal of flip-flop circuit 10；Port ADD is connected into the grid of NMOS 9 and NMOS 8 simultaneously, and it determines that voltage logic is selected
The whether normal work of drive circuit 20 is selected, while also making Current-type sensitive amplifier 30 be connected with FLASH units.
According to above-mentioned embodiment, the input control port that voltage logic selects drive circuit 20 is carried out into regular tax
Value, can be switched on or off metal-oxide-semiconductor, so as to respectively according to the difference electricity that FLASH memory is required in programming, erasing operation
Pressure, provides output level for output port BL, SL, reaches the purpose for driving bit line.
Fig. 4 show schematically show a kind of implementation of Current-type sensitive amplifier 30 in circuit block diagram shown in Fig. 1
Circuit theory diagrams.
As shown in figure 4, the input control signal of Current-type sensitive amplifier 30 includes port H5_0, H5_2, H5_3 input
Signal.Wherein, port H5_0 is input into additional enable signal, transmit power vd DP by PMOS 33, port H5_2 with
Port H5_3 is input into additional enable signal, and used as bias control terminal, input port IN is connected with the bit line of FLASH units, defeated
Exit port OUT provides output logic level.
As shown in figure 4, supply voltage VDDP is input into the source electrode of PMOS 7 and PMOS 6, PMOS 7 and PMOS 6 constitutes electricity
Stream mirror support structures, NMOS 11 and NMOS 12 composition common gate amplifier structures, the termination input port of source electrode one of NMOS 12
IN, is connected with FLASH units；NMOS 22, NMOS 24 and NMOS 23 constitute electric current leakage support structures, there is provided fixed big all the way
Little electric current；PMOS 8 is managed and NMOS 13 constitutes inverter structure, increases the driving force of Current-type sensitive amplifier 30.
Embodiments of the invention are the foregoing is only, the scope of patent protection of the present invention is not thereby limited, the present invention is also
Above-mentioned various modules additionally can be improved, or be replaced using technically equivalent ones, for example：Increase further
Other modules of optimization etc..Therefore the equivalent structure change made by all specifications and diagramatic content with the present invention, or directly
Or apply to indirectly other correlative technology fields be all contained in the same manner the present invention it is covered in the range of.
Claims (5)
1. bit-line voltage conversion drives and current testing circuit, it is characterised in that include：
Master-slave flip-flop, receives input signal, and the data signal for obtaining of sampling to which export to voltage logic and select to drive electricity
Road；
Voltage logic selects drive circuit, receives the control signal of data signal and input, and by Internal latches storage
The switch of data and logical signal is selected, and obtains the level signal of the bit line and source electrode of driving FLASH units；
Current-type sensitive amplifier circuit, receives level signal and is amplified and exports logic low and high level for bit-line voltage
Drive the test with bit line current.
2. bit-line voltage conversion according to claim 1 drives and current testing circuit, it is characterised in that the voltage is patrolled
Collecting selection drive circuit includes PMOS, transmission gate, latch, NMOS tube, decoding switch circuit；
The source electrode of PMOS 3 is connected with power supply, the connection of the output control terminal of grid and latch, the source electrode of drain electrode and PMOS 2
Connection；The grid of PMOS 2 selects the input H5_9 of drive circuit, drain electrode to transmit with the first of transmission gate as voltage logic
End connection；
Two control ends of transmission gate select input H5_4, H5_8 of drive circuit respectively as voltage logic, transmission gate
Second transmission end selects output end BL of drive circuit as voltage logic；
The pulse signal end of latch as voltage logic select drive circuit input H5_7, the input of latch with translate
The source connection of code switch circuit, the input control end of latch are connected with the control end of decoding switch circuit.
3. bit-line voltage conversion according to claim 2 drives and current testing circuit, it is characterised in that the decoding is opened
Powered-down road includes NMOS tube 4, NMOS tube 5 and NMOS tube 6, NMOS tube 8, NMOS tube 9 and NMOS tube 10；
The grid of NMOS tube 4 is connected with the input control end of latch as control end, grounded drain, source electrode and NMOS tube 5
Source electrode connects；The grid of NMOS tube 5 as voltage logic select drive circuit input H5_6, the drain electrode of NMOS tube 5 with
The drain electrode of NMOS tube 6 selects output end SL of drive circuit as voltage logic, and is connected with the first transmission end of transmission gate；
The grid of NMOS tube 6 selects the input H5_5 of drive circuit, source ground as voltage logic；
The drain electrode of NMOS tube 9 is connected with the input of latch, and grid is connected with the grid of NMOS tube 8, and as voltage logic
Select the input ADD of drive circuit；The source electrode of NMOS tube 9 is connected with the drain electrode of NMOS tube 10, the source ground of NMOS tube 10,
Grid is connected with the output end of master-slave flip-flop；The source electrode of NMOS tube 8 is that output end OUT is used to connect the sensitive amplification of current mode
Device, drain electrode are connected with the second transmission end of transmission gate.
4. bit-line voltage conversion according to claim 1 drives and current testing circuit, it is characterised in that the current mode
Sensitive amplifier circuit includes current comparator, PMOS and phase inverter；
Two offset sides of the current comparator are respectively used to connect external control signal；The input IN of current comparator and electricity
Pressure logic selects the output end OUT connection of drive circuit, output end to be connected with the input of phase inverter；
The input of phase inverter is connected with the drain electrode of PMOS 33, and the source electrode of PMOS 33 is connected with power supply, and grid is used to connect
External control signal；The output end of phase inverter is used to connect FLASH units.
5. bit-line voltage conversion according to claim 1 drives and current testing circuit, it is characterised in that the electric current ratio
Include PMOS and NMOS tube compared with device；PMOS 6, the source electrode of PMOS 7 are connected with power supply, gate interconnection, drain electrode respectively with
NMOS tube 11 drains, the drain electrode connection of NMOS tube 12；11 grid of NMOS tube, 12 grounded-grid of NMOS tube, 11 source electrode of NMOS tube and electricity
Current load circuit connects, input IN of 12 source electrode of NMOS tube as current comparator；The grid of the PMOS 6 is connected with drain electrode
Connect；11 grid of the NMOS tube is used as offset side H5_3；
Current loading circuit includes three NMOS tubes；The grid of NMOS tube 22, the grid of NMOS tube 23 are connected with power supply, NMOS tube
24 grids are used as offset side H5_2；The drain electrode of NMOS tube 22 is connected with the source electrode of NMOS tube 11, the drain electrode of source electrode and NMOS tube 24
Connection, the source electrode of NMOS tube 24 are connected with the drain electrode of NMOS tube 23, the source ground of NMOS tube 23.
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| CN201610988434.6A CN106531218B (en) | 2016-11-10 | 2016-11-10 | Bit line voltage conversion driving and current testing circuit |
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|---|---|---|---|
| CN201610988434.6A CN106531218B (en) | 2016-11-10 | 2016-11-10 | Bit line voltage conversion driving and current testing circuit |
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| CN112233714A (en) * | 2020-12-11 | 2021-01-15 | 深圳市芯天下技术有限公司 | Data output drive circuit and nonvolatile flash memory |
| CN113223588A (en) * | 2021-06-11 | 2021-08-06 | 上海交通大学 | Bit line voltage reading device |
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| CN106531218B (en) | 2020-01-24 |
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