CN102664040A - High-speed low-power flash memory architecture and operation method thereof - Google Patents
High-speed low-power flash memory architecture and operation method thereof Download PDFInfo
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Abstract
The invention relates to a high-speed low-power flash memory architecture and an operation method thereof. The high-speed low-power flash memory architecture is characterized in that the high-speed low-power flash memory architecture comprises multiple memory cells; each row of the memory cells are connected to a second multiplexer by corresponding GBL lines; the second multiplexer is provided with multiple second detector amplifier; each one of the memory cells comprises multiple flash memory bit units; control terminals of each line of the flash memory bit units in a line memory group are connected with each other and then are connected to corresponding WL bit line terminals; source terminals of the flash memory bit units in the line memory group and the flash memory bit units in a row memory group are connected with each other and then are connected to SL bit line terminals; drain terminals of each row of the flash memory bit units in the row memory group are connected with each other and then are connected to corresponding BL bit line terminals; the corresponding BL bit line terminals in the row memory group are connected to a first multiplexer; and the first multiplexer is provided with multiple first detector amplifier. The high-speed low-power flash memory architecture has a compact structure and a fast operation speed, reduces power consumption and a use cost of a processor system and has a wide application scope.
Description
Technical field
The present invention relates to a kind of flash memory structure and method of operating, especially a kind of high speed and low-power consumption flash memory architecture and method of operating belong to the technical field of flash memory.
Background technology
In processor system, it is to be integrated into many functional blocks in the integrated circuit.The most frequently used processor system comprises a microprocessor or microcontroller (CPU), static RAM (SRAM) module, flash memory and some other companion chip, and above-mentioned processor system is installed in the same motherboard.
Usually the system program of microprocessor or microcontroller is to exist in the flash memory.When system started, system program downloaded to from flash memory in static RAM (SRAM) module, microprocessor or the microcontroller programmed instruction of from static RAM (SRAM) module, taking.Here the main cause that adopts above-mentioned treatment step is that the speed that reads at random of flash memory is too slow, and the reading speed of flash memory can not be with the speed of microprocessor or microcontroller (CPU).Therefore, usually will download to program earlier in static RAM (SRAM) module; Like this will a static RAM (SRAM) between microprocessor or microcontroller (CPU) and flash memory, increased system cost, make that simultaneously the power consumption of entire process device system is higher.
Summary of the invention
The objective of the invention is to overcome the deficiency that exists in the prior art, a kind of high speed and low-power consumption flash memory architecture and method of operating are provided, its compact conformation, operating speed is fast, reduces power consumption, can reduce the use cost of processor system, and is applied widely.
According to technical scheme provided by the invention; Said high speed and low-power consumption flash memory architecture; Comprise some memory partitionings; After arranging, the said memory partitioning rule of correspondence forms row memory partitioning group and row memory partitioning group; Said every row memory partitioning group all links to each other with second MUX through corresponding GBL line, and some second detecting amplifiers are set on said second MUX, and second MUX amplifies and convert to the store status of digital signal output memory partitioning by second detecting amplifier after through the memory partitioning in the GBL line options respective column memory partitioning group of correspondence;
Comprise some flash bit cells in the memory partitioning, said flash bit cell comprises that control is extreme, source terminal and drain electrode end; Some flash bit cell rules are arranged and are formed row storage group and row storage group; Be connected with corresponding WL bit line end after the control of every capable flash bit cell extremely interconnects in the row storage group; Row is stored group and is listed as and all is connected with SL bit line end after the source terminal of storing flash bit cell in the group interconnects; Be connected with corresponding BL bit line end after the drain electrode end of every row flash bit cell interconnects in the row storage group, and corresponding BL bit line end links to each other with first MUX in the row storage group; Some first detecting amplifiers are set on first MUX, and link to each other with second MUX through first detecting amplifier and corresponding GBL line; First MUX is selected to be input in second MUX and second detecting amplifier through corresponding GBL line by first detecting amplifier detection amplification back behind the corresponding flash bit cell through the BL bit line end of correspondence.
No more than 256 of the quantity of connection flash bit cell on the BL bit line end arbitrarily in the said row storage group.
Said flash bit cell is an electron tunneling oxide layer flash memory.Said first detecting amplifier comprises voltage comparator or current comparator.
The method of operating of a kind of high speed and low-power consumption flash memory architecture; Comprise some memory partitionings; After arranging, the said memory partitioning rule of correspondence forms row memory partitioning group and row memory partitioning group; Said every row memory partitioning group all links to each other with second MUX through corresponding GBL line, and some second detecting amplifiers are set on said second MUX;
Comprise some flash bit cells in the memory partitioning, said flash bit cell comprises that control is extreme, source terminal and drain electrode end; Some flash bit cell rules are arranged and are formed row storage group and row storage group; Be connected with corresponding WL bit line end after the control of every capable flash bit cell extremely interconnects in the row storage group; Row is stored group and is listed as and all is connected with SL bit line end after the source terminal of storing flash bit cell in the group interconnects; Be connected with corresponding BL bit line end after the drain electrode end of every row flash bit cell interconnects in the row storage group, and corresponding BL bit line end links to each other with first MUX in the row storage group; Some first detecting amplifiers are set on first MUX, and link to each other with second MUX through first detecting amplifier and corresponding GBL line;
Method of operating to memory partitioning comprises expert group and the method for operating that is listed as storage group of storing of memory partitioning, row is stored group comprise data write operation, data read operation and data erase operation with the method for operating that is listed as flash bit cell in the storage group;
The second operation bias voltage is loaded on the SL bit line end all the time; Choose row storage group and row storage group and intersects the flash bit cell of confirming, and the first operation bias voltage is loaded on the WL bit line end of correspondence, the 3rd operates bias voltage loads on remaining WL bit line end; Select corresponding BL bit line end through MUX, and the 4th operation bias voltage is loaded on the BL bit line end of selecting correspondence, the 5th operation bias voltage loads on remaining BL bit line end;
When the first operation bias voltage, the second operation bias voltage and the 4th operation bias voltage corresponding matching; Make the BL bit line end choose and WL bit line end intersect definite flash bit cell and reach the required voltage of passage of heat electronics injection; And the second operation bias voltage, the 3rd operation bias voltage and the 5th operation bias voltage corresponding matching; Make when row storage group does not match with voltage that is listed as all the other flash bit cells in the storage group and required passage of heat electronics injecting voltage; In the flash bit cell that said intersection is confirmed, writing required data, realize data write operation to flash memory architecture;
When the first operation bias voltage, the second operation bias voltage and the 4th operation bias voltage corresponding matching; Can measure the current value that flows through the definite flash bit cell of said intersection; Simultaneously; The second operation bias voltage, the 3rd operation bias voltage and the 5th operation bias voltage corresponding matching; Turn-off row and store group and the electric current output that is listed as all the other flash bit cells in the storage group,, realize data read operation flash memory architecture can read the store status of the definite flash bit cell of said intersection;
When the first operation bias voltage, the second operation bias voltage and the 4th operation bias voltage corresponding matching; So that the voltage difference of the source terminal of the flash bit cell that links to each other with the first operation bias voltage and control end and required erasing voltage coupling; And the 3rd operation bias voltage and the 4th operation bias voltage corresponding matching; When the source terminal of the feasible flash bit cell that links to each other with the 3rd operation bias voltage and the voltage difference of control end and required erasing voltage do not match; Can store the row storage group that links to each other corresponding with the first operation bias voltage, realize data erase operation to flash memory architecture.
No more than 256 of the quantity of connection flash bit cell on the BL bit line end arbitrarily in the said row storage group.
When row storage group and row storage group being intersected the flash bit cell confirmed when reading, the first operation bias voltage is 5V, and the second operation bias voltage is 0V, and the 3rd operation bias voltage is 0V, and the 4th to operate bias voltage be 1V, and the 5th operates bias voltage is 0V or floats.
Write fashionablely when row storage group and row storage group being intersected the flash bit cell confirmed, the first operation bias voltage is 9V, and the second operation bias voltage is 0V, and the 3rd operation bias voltage is 0V, and the 4th to operate bias voltage be 5V, and the 5th to operate bias voltage be 0V.
When row storage group and row storage group being intersected the flash bit cell confirmed when wiping, the first operation bias voltage be-9V, and the second operation bias voltage is 9V, and the 3rd to operate bias voltage be 0V, and the 4th operates bias voltage and the 5th operates bias voltage and be and float.
Said flash bit cell is an electron tunneling oxide layer flash memory.
Advantage of the present invention: comprise some flash bit cells in the memory partitioning; Flash bit cell rule is arranged and is formed row storage group and row storage group; WL bit line end links to each other with the control end of every capable flash bit cell in the row storage group; BL bit line end links to each other with the drain electrode end of every row flash bit cell in the row storage group, and SL bit line end links to each other with the source terminal of row storage group and row storage group; BL bit line end links to each other with first detecting amplifier through first MUX; Link to each other with second MUX through corresponding GBL line through first detecting amplifier in the memory partitioning; Some second detecting amplifiers are set on second MUX; Can reduce the capacitive load on the BL bit line end through the quantity that flash bit cell on the BL bit line end is set, improve and detect switching time, simultaneously; After the multilayer selection amplification through first MUX, first detecting amplifier, second MUX and second detecting amplifier, can make to be complementary with the time for reading of microprocessor or microcontroller the storage time that forms the flash framework; Compact conformation, operating speed is fast, reduces power consumption, can reduce the use cost of processor system, and is applied widely.
Description of drawings
Fig. 1 is the structural representation of memory partitioning of the present invention.
Fig. 2 is a structural representation of the present invention.
Description of reference numerals: 1-first MUX, 2-first detecting amplifier, 3-GBL line, 4-second MUX and 5-second detecting amplifier.
Embodiment
Below in conjunction with concrete accompanying drawing and embodiment the present invention is described further.
As shown in Figure 2: in order to reduce power consumption; Improve reading speed; The present invention includes some memory partitionings; After arranging, the said memory partitioning rule of correspondence forms row memory partitioning group and row memory partitioning group; Said every row memory partitioning group all links to each other with second MUX 4 through corresponding GBL line 3, some second detecting amplifier, 5, the second MUXs 4 is set on said second MUX 4 amplifies and convert to the store status of digital signal output memory partitioning by second detecting amplifier 5 after through the memory partitioning in the GBL line options respective column memory partitioning group of correspondence.
As shown in Figure 1: comprise some flash bit cells in the memory partitioning, said flash bit cell comprises that control is extreme, source terminal and drain electrode end; Some flash bit cell rules are arranged and are formed row storage group and row storage group; Be connected with corresponding WL bit line end after the control of every capable flash bit cell extremely interconnects in the row storage group; Row is stored group and is listed as and all is connected with SL bit line end after the source terminal of storing flash bit cell in the group interconnects; Be connected with corresponding BL bit line end after the drain electrode end of every row flash bit cell interconnects in the row storage group, and corresponding BL bit line end links to each other with first MUX 1 in the row storage group; Some first detecting amplifiers 2 are set on first MUX 1, and link to each other with second MUX 4 through first detecting amplifier 2 and corresponding GBL line; First MUX 1 is selected to be input in second MUX 4 and second detecting amplifier 5 through corresponding GBL line by first detecting amplifier, 2 detection amplification backs behind the corresponding flash bit cell through the BL bit line end of correspondence.The quantity of the quantity of said GBL line 3 and first detecting amplifier 2 is consistent, and first detecting amplifier 2 can be consistent according to the columns of row storage group in the memory partitioning, also can be less than the columns of row storage group.
After the above-mentioned connection, the SL bit line end in every capable memory partitioning can correspondingly connect, and also can not connect, so that keep relative independence in every capable memory partitioning between each memory partitioning.
Wherein, No more than 256 of the quantity of connection flash bit cell on the BL bit line end arbitrarily in the said row storage group; The number of the flash memory bit cell that usually connects on the BL bit line end is 128 or 256, selects corresponding BL bit line end through MUX, after choosing through BL bit line end; According to the corresponding matching of WL bit line end and SL bit line end, just can realize corresponding flash bit cell is operated accordingly again.Said flash bit cell is an electron tunneling oxide layer flash memory.Said local detecting amplifier comprises voltage comparator or current comparator.Second detecting amplifier 5 also can adopt voltage comparator, can export the corresponding digital amount simultaneously.
The purpose of above-mentioned setting is to reduce the capacitive load on the BL bit line end; Group of row storage simultaneously and row storage group constitute memory partitioning; And it is continuous with corresponding GBL line through some first detecting amplifiers 2; Thereby the store status of flash bit cell in the memory partitioning is selected to amplify back output through first MUX 1 and first detecting amplifier 2; And through reading the store status of flash bit cell after 4 selections of second MUX and 5 amplifications of second detecting amplifier fast; Quantity and multilayer through the flash bit cell is set are selected to amplify, and can make the state reading speed of formation flash memory architecture and the reading speed of microprocessor or microcontroller mate.
Because first detecting amplifier 2 and second detecting amplifier 5 include voltage comparator, voltage comparator can be regarded an A/D converting unit as, and the quantity of first detecting amplifier 2 is provided with as required, and second detecting amplifier 5 plays the function of A/D conversion; Carrying out voltage ratio at voltage comparator is generally to have reference voltage, and another input end of voltage comparator is the output voltage values of flash bit cell; Reference voltage is generally fixing; And the output voltage values of flash bit cell will need the corresponding time when 0 rises to relevant voltage; And the rise time can according to switching time=(voltage * electric capacity)/electric current, therefore amplify through 2 cascades of first detecting amplifier and quantity that flash bit cell on the BL bit line is set can reduce electric capacity, to improve switching time; So that the time for reading of flash memory architecture can be complementary with the microprocessor in the processor system or the reading speed of microcontroller; Can save existing SRAM, save cost, reduce power consumption.
The flash memory architecture of some memory partitionings formation is carried out method of operating comprise method of operating single flash bit cell in the memory partitioning; When the flash bit cell carries out required operation in to different memory partitionings, can reach operation to whole flash memory architecture.Single flash bit cell has the control utmost point, drain electrode end, source terminal and floating gate electrode, when loading correspondent voltage, can realize that the data to single flash bit cell write, data write and the data manipulation operation.When some flash bit cell rules arrange form row storage group and row storage group after, can reach through following manner row storage group is operated with the single flash bit cell in the row storage group.Be in particular:
Row storage group is comprised data write operation, data read operation and data erase operation with the method for operating that is listed as flash bit cell in the storage group;
The second operation bias voltage is loaded on the SL bit line end all the time; Choose row storage group and row storage group and intersects the flash bit cell of confirming, and the first operation bias voltage is loaded on the WL bit line end of correspondence, the 3rd operates bias voltage loads on remaining WL bit line end; Select corresponding BL bit line end through MUX, and the 4th operation bias voltage is loaded on the BL bit line end of selecting correspondence, the 5th operation bias voltage loads on remaining BL bit line end; The loading of the 4th operation bias voltage and the 5th operation bias voltage chooses the back to confirm correspondent voltage through MUX;
When the first operation bias voltage, the second operation bias voltage and the 4th operation bias voltage corresponding matching; Make the BL bit line end choose and WL bit line end intersect definite flash bit cell and reach the required voltage of passage of heat electronics injection; And the second operation bias voltage, the 3rd operation bias voltage and the 5th operation bias voltage corresponding matching; Make when row storage group does not match with voltage that is listed as all the other flash bit cells in the storage group and required passage of heat electronics injecting voltage; In the flash bit cell that said intersection is confirmed, writing required data, realize data write operation to flash memory architecture;
When the first operation bias voltage, the second operation bias voltage and the 4th operation bias voltage corresponding matching; Can measure the current value that flows through the definite flash bit cell of said intersection; Simultaneously; The second operation bias voltage, the 3rd operation bias voltage and the 5th operation bias voltage corresponding matching; Turn-off row and store group and the electric current output that is listed as all the other flash bit cells in the storage group,, realize data read operation flash memory architecture can read the store status of the definite flash bit cell of said intersection;
When the first operation bias voltage, the second operation bias voltage and the 4th operation bias voltage corresponding matching; So that the voltage difference of the source terminal of the flash bit cell that links to each other with the first operation bias voltage and control end and required erasing voltage coupling; And the 3rd operation bias voltage and the 4th operation bias voltage corresponding matching; When the source terminal of the feasible flash bit cell that links to each other with the 3rd operation bias voltage and the voltage difference of control end and required erasing voltage do not match; Can store the row storage group that links to each other corresponding with the first operation bias voltage, realize data erase operation to flash memory architecture.
Can know from the aforesaid operations method, when flash memory architecture is operated write operation,, the second operation bias voltage loaded on the SL bit line end all the time adding first bias voltage on the WL bit line end in the memory partitioning; Choose row storage group and row storage group and intersects the flash bit cell of confirming, and the first operation bias voltage is loaded on the WL bit line end of correspondence, the 3rd operates bias voltage loads on remaining WL bit line end; Select corresponding BL bit line end through MUX, and the 4th operation bias voltage is loaded on the BL bit line end of selecting correspondence, the 5th operation bias voltage loads on remaining BL bit line end; The loading of the 4th operation bias voltage and the 5th operation bias voltage chooses the back to confirm correspondent voltage through MUX.Wherein, the loading of voltage and selection can be passed through GBL line 3 on the BL bit line end, after loading through GBL line 3, select corresponding flash bit cell through first MUX 1 again.When needs to memory partitioning in flash bit cell when writing data and obliterated data, identical to on-load voltage in the memory partitioning with the mode of existing on-load voltage; And need read the store status of corresponding flash bit cell in the memory partitioning time; In order to improve store status; The present invention carries out initial option through first MUX 1 and first detecting amplifier 2 and amplifies; Amplify once more through outer second MUX 4 of memory partitioning and second detecting amplifier 5 again and change back digital signal output, select to amplify the mode of exporting through this multilayer and can improve reading speed memory partitioning stored state.
Through concrete operating voltage the operating process of single flash bit cell is analyzed below; Concrete operations voltage is: when row storage group and row storage group being intersected definite flash bit cell when reading; The first operation bias voltage is 5V, and the second operation bias voltage is 0V, and the 3rd operation bias voltage is 0V; The 4th operation bias voltage is 1V, and the 5th operation bias voltage is 0V or floats.
Write fashionablely when row storage group and row storage group being intersected the flash bit cell confirmed, the first operation bias voltage is 9V, and the second operation bias voltage is 0V, and the 3rd operation bias voltage is 0V, and the 4th to operate bias voltage be 5V, and the 5th to operate bias voltage be 0V.
When row storage group and row storage group being intersected the flash bit cell confirmed when wiping, the first operation bias voltage be-9V, and the second operation bias voltage is 9V, and the 3rd to operate bias voltage be 0V, and the 4th operates bias voltage and the 5th operates bias voltage and be and float.
When operating bias voltage, first of 5V loads on the corresponding WL bit line end; 0V the 3rd operation bias voltage loads on remaining WL bit line end; The second operation bias voltage of 0V loads on the SL bit line end, and the BL bit line end of choosing through MUX adds 1V voltage, and remaining BL bit line terminal voltage is 0V or floats.Before the flash bit cell of confirming by BL bit line end and WL bit line end, be written into data; The data storage that writes is in floating gate electrode; Under the corresponding matching through the first operation bias voltage, the second operation bias voltage and the 4th operation bias voltage, there are not electric current or very little electric current to flow through; When being in erase status before the flash bit cell; Do not have electronics in the floating gate electrode, seldom electronics or positive ion are stored in the floating gate electrode; Under the corresponding matching through the first operation bias voltage, second operating voltage and the 4th operation bias voltage; There is bigger electric current to flow through; To distinguish what store in the flash bit cell after the conversion be " 1 " perhaps " 0 " thereby amplify through first detecting amplifier 2 and second detecting amplifier 5, realizes the data read operation to flash bit cell in row storage group and the row storage group.
When 9V first the operation bias voltage be loaded into WL bit line end, 0V the 3rd the operation bias voltage load on remaining WL bit line end; The second operation bias voltage of 0V loads on SL bit line end; The 4th operation bias voltage of 5V loads on the BL bit line end of choosing, and the 5th operation bias voltage of 0V loads on remaining BL bit line end; Corresponding matching through the first operation bias voltage, the second operation bias voltage and the 3rd operation bias voltage; Can inject (hot channel electron injiection) through passage of heat electronics passes electronics in the silicon dioxide entering floating gate electrode; Passage of heat electronics is injected to write operation means commonly used in the technology, can realize the data of single flash bit cell are write; And the flash bit cell that links to each other with the 3rd operation bias voltage and the 5th operation bias voltage does not match owing to required passage of heat electronics injecting voltage; Remaining flash bit cell can not carry out write operation, the interference when avoiding that other flash bit cells are write data.
When the first operation bias voltage of-9V is loaded on the WL bit line end; The 3rd operation bias voltage of 0V is loaded into remaining WL bit line end; The second operation bias voltage of 9V loads on the SL bit line end; The 4th operation bias voltage and the 5th operation bias voltage are the voltage of floating, and under the corresponding matching through the first operation bias voltage and the second operation bias voltage, can reach the required electric field of FN (Fowler-Nordheim) tunnel effect; Electronics in the floating gate electrode in the flash memory bit cell will flow out to SL bit line end, to reach the storage purpose of wiping in the floating gate electrode.Because the 3rd operation bias voltage is 0V, the magnitude of voltage between the second operation bias voltage and the 3rd operation bias voltage can not reach the required voltage of FN tunnel effect, so row storage group stores with row, and remaining flash bit cell can not be wiped free of in the group.Because the 4th operation bias voltage and the 5th operation bias voltage are the voltage status of floating; The first operation bias voltage links to each other with the control end of all flash bit cells in the delegation; The 3rd operating voltage links to each other with the source terminal of all flash bit cells; Therefore when wiping, can the flash bit cell that load in the first operation bias voltage corresponding row storage group all be wiped.
Comprise some flash bit cells in the memory partitioning of the present invention; Flash bit cell rule is arranged and is formed row storage group and row storage group; WL bit line end links to each other with the control end of every capable flash bit cell in the row storage group; BL bit line end links to each other with the drain electrode end of every row flash bit cell in the row storage group, and SL bit line end links to each other with the source terminal of row storage group and row storage group; BL bit line end links to each other with first detecting amplifier 2 through first MUX 1; First detecting amplifier 2 through in the memory partitioning links to each other with second MUX 4 through corresponding GBL line 3; Some second detecting amplifiers 5 are set on second MUX 4; Can reduce the capacitive load on the BL bit line end through the quantity that flash bit cell on the BL bit line end is set; Improve and detect switching time; Simultaneously, after selecting to amplify through the multilayer of first MUX 1, first detecting amplifier 2, second MUX 4 and second detecting amplifier 5, can make to be complementary with the time for reading of microprocessor or microcontroller the storage time of formation flash framework; Compact conformation, operating speed is fast, reduces power consumption, can reduce the use cost of processor system, and is applied widely.
Claims (10)
1. high speed and low-power consumption flash memory architecture; It is characterized in that: comprise some memory partitionings; After arranging, the said memory partitioning rule of correspondence forms row memory partitioning group and row memory partitioning group; Said every row memory partitioning group all links to each other with second MUX (4) through corresponding GBL line; Some second detecting amplifiers (5) are set on said second MUX (4), and second MUX (4) amplifies and converts to the store status of digital signal output memory partitioning by second detecting amplifier (5) after through the memory partitioning in the corresponding GBL line options respective column memory partitioning group;
Comprise some flash bit cells in the memory partitioning, said flash bit cell comprises that control is extreme, source terminal and drain electrode end; Some flash bit cell rules are arranged and are formed row storage group and row storage group; Be connected with corresponding WL bit line end after the control of every capable flash bit cell extremely interconnects in the row storage group; Row is stored group and is listed as and all is connected with SL bit line end after the source terminal of storing flash bit cell in the group interconnects; Be connected with corresponding BL bit line end after the drain electrode end of every row flash bit cell interconnects in the row storage group, and corresponding BL bit line end links to each other with first MUX (1) in the row storage group; Some first detecting amplifiers (2) are set on first MUX (1), and link to each other with second MUX (4) through first detecting amplifier (2) and corresponding GBL line; First MUX (1) is selected to be input in second MUX (4) and second detecting amplifier (5) through corresponding GBL line by first detecting amplifier (1) detection amplification back behind the corresponding flash bit cell through the BL bit line end of correspondence.
2. high speed according to claim 1 and low-power consumption flash memory architecture is characterized in that: no more than 256 of the quantity of connection flash bit cell on the BL bit line end arbitrarily in the said row storage group.
3. high speed according to claim 1 and low-power consumption flash memory architecture is characterized in that: said flash bit cell is an electron tunneling oxide layer flash memory.
4. high speed according to claim 1 and low-power consumption flash memory architecture is characterized in that: said first detecting amplifier (1) comprises voltage comparator or current comparator.
5. the method for operating of high speed and low-power consumption flash memory architecture; It is characterized in that: comprise some memory partitionings; After arranging, the said memory partitioning rule of correspondence forms row memory partitioning group and row memory partitioning group; Said every row memory partitioning group all links to each other with second MUX (4) through corresponding GBL line, and some second detecting amplifiers (5) are set on said second MUX (4);
Comprise some flash bit cells in the memory partitioning, said flash bit cell comprises that control is extreme, source terminal and drain electrode end; Some flash bit cell rules are arranged and are formed row storage group and row storage group; Be connected with corresponding WL bit line end after the control of every capable flash bit cell extremely interconnects in the row storage group; Row is stored group and is listed as and all is connected with SL bit line end after the source terminal of storing flash bit cell in the group interconnects; Be connected with corresponding BL bit line end after the drain electrode end of every row flash bit cell interconnects in the row storage group, and corresponding BL bit line end links to each other with first MUX (1) in the row storage group; Some first detecting amplifiers (2) are set on first MUX (1), and link to each other with second MUX (4) through first detecting amplifier (2) and corresponding GBL line;
Method of operating to memory partitioning comprises expert group and the method for operating that is listed as storage group of storing of memory partitioning, row is stored group comprise data write operation, data read operation and data erase operation with the method for operating that is listed as flash bit cell in the storage group;
The second operation bias voltage is loaded on the SL bit line end all the time; Choose row storage group and row storage group and intersects the flash bit cell of confirming, and the first operation bias voltage is loaded on the WL bit line end of correspondence, the 3rd operates bias voltage loads on remaining WL bit line end; Select corresponding BL bit line end through MUX, and the 4th operation bias voltage is loaded on the BL bit line end of selecting correspondence, the 5th operation bias voltage loads on remaining BL bit line end;
When the first operation bias voltage, the second operation bias voltage and the 4th operation bias voltage corresponding matching; Make the BL bit line end choose and WL bit line end intersect definite flash bit cell and reach the required voltage of passage of heat electronics injection; And the second operation bias voltage, the 3rd operation bias voltage and the 5th operation bias voltage corresponding matching; Make when row storage group does not match with voltage that is listed as all the other flash bit cells in the storage group and required passage of heat electronics injecting voltage; In the flash bit cell that said intersection is confirmed, writing required data, realize data write operation to flash memory architecture;
When the first operation bias voltage, the second operation bias voltage and the 4th operation bias voltage corresponding matching; Can measure the current value that flows through the definite flash bit cell of said intersection; Simultaneously; The second operation bias voltage, the 3rd operation bias voltage and the 5th operation bias voltage corresponding matching; Turn-off row and store group and the electric current output that is listed as all the other flash bit cells in the storage group,, realize data read operation flash memory architecture can read the store status of the definite flash bit cell of said intersection;
When the first operation bias voltage, the second operation bias voltage and the 4th operation bias voltage corresponding matching; So that the voltage difference of the source terminal of the flash bit cell that links to each other with the first operation bias voltage and control end and required erasing voltage coupling; And the 3rd operation bias voltage and the 4th operation bias voltage corresponding matching; When the source terminal of the feasible flash bit cell that links to each other with the 3rd operation bias voltage and the voltage difference of control end and required erasing voltage do not match; Can store the row storage group that links to each other corresponding with the first operation bias voltage, realize data erase operation to flash memory architecture.
6. the method for operating of high speed according to claim 5 and low-power consumption flash memory architecture is characterized in that: no more than 256 of the quantity of connection flash bit cell on the BL bit line end arbitrarily in the said row storage group.
7. the method for operating of high speed according to claim 5 and low-power consumption flash memory architecture; It is characterized in that: when row storage group and row storage group being intersected definite flash bit cell when reading; The first operation bias voltage is 5V, and the second operation bias voltage is 0V, and the 3rd operation bias voltage is 0V; The 4th operation bias voltage is 1V, and the 5th operation bias voltage is 0V or floats.
8. the method for operating of high speed according to claim 5 and low-power consumption flash memory architecture; It is characterized in that: write fashionable when row storage group and row storage group being intersected definite flash bit cell; The first operation bias voltage is 9V, and the second operation bias voltage is 0V, and the 3rd operation bias voltage is 0V; The 4th operation bias voltage is 5V, and the 5th operation bias voltage is 0V.
9. the method for operating of high speed according to claim 5 and low-power consumption flash memory architecture; It is characterized in that: when row storage group and row storage group being intersected definite flash bit cell when wiping; The first operation bias voltage is-9V; The second operation bias voltage is 9V, and the 3rd operation bias voltage is 0V, and the 4th operation bias voltage and the 5th operation bias voltage are to be floated.
10. the method for operating of high speed according to claim 5 and low-power consumption flash memory architecture is characterized in that: said flash bit cell is an electron tunneling oxide layer flash memory.
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| CN201210098584.1A CN102664040B (en) | 2012-04-01 | 2012-04-01 | High-speed low-power flash memory architecture and operation method thereof |
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| CN201210098584.1A CN102664040B (en) | 2012-04-01 | 2012-04-01 | High-speed low-power flash memory architecture and operation method thereof |
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| CN102664040B CN102664040B (en) | 2014-08-13 |
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| CN201210098584.1A Active CN102664040B (en) | 2012-04-01 | 2012-04-01 | High-speed low-power flash memory architecture and operation method thereof |
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| CN102969021A (en) * | 2012-11-21 | 2013-03-13 | 无锡来燕微电子有限公司 | Memory capable of being changed to multiple specification requirement grades and technical field of operating method thereof |
| CN102969020A (en) * | 2012-11-21 | 2013-03-13 | 无锡来燕微电子有限公司 | Memory with multiple specification grades selectable and operating method thereof |
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| CN102664040B (en) | 2014-08-13 |
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