CN111310394B

CN111310394B - Multi-level selection structure applied to antifuse Field Programmable Gate Array (FPGA)

Info

Publication number: CN111310394B
Application number: CN202010128823.8A
Authority: CN
Inventors: 蔺旭辉; 曹杨; 曹靓; 王晓玲
Original assignee: CETC 58 Research Institute
Current assignee: CETC 58 Research Institute
Priority date: 2020-02-28
Filing date: 2020-02-28
Publication date: 2022-02-01
Anticipated expiration: 2040-02-28
Also published as: CN111310394A

Abstract

The invention discloses a multi-level selection structure applied to an anti-fuse FPGA, and belongs to the technical field of integrated circuit design. The multi-level selection structure comprises a first path, a second path and a third path, wherein the first path is used for applying programming voltage VPP to one end of an antifuse to be programmed to perform high-voltage programming; a second path providing voltage VKS for unprogrammed antifuses for pre-charge protection; the third path is used for enabling the control signal to start the charge pump circuit after the programming of the antifuse FPGA circuit is finished, and an output signal of the charge pump circuit starts the third path to provide a working voltage VCCA for a unit connected with the antifuse; and a fourth path for applying a low voltage GND to the other end of the antifuse to be programmed during programming to realize programming of the antifuse. By using the multi-level selection structure applied to the anti-fuse FPGA provided by the invention, the anti-fuse FPGA can flexibly carry out programming, testing and normal working modes, and the programming test working efficiency of the circuit is improved.

Description

Multi-level selection structure applied to antifuse Field Programmable Gate Array (FPGA)

Technical Field

The invention relates to the technical field of integrated circuit design, in particular to a multi-level selection structure applied to an antifuse Field Programmable Gate Array (FPGA).

Background

An FPGA (Field Programmable Gate Array) is a novel device developed on the basis of Programmable logic circuit devices such as PAL, GAL, CPLD, etc., and is used as a semi-custom circuit in the Field of Application Specific Integrated Circuits (ASICs), which has a flexible and expandable architecture design technology, large-capacity Programmable logic resources and large-scale wiring resources, far exceeding the original Programmable Gate circuits. Because of high integration level, strong flexibility, low development cost, short development period, low risk and strong reliability, the system has gradually replaced ASIC circuits in the field of system development and design.

The circuit types of the common mainstream FPGA are mainly SRAM type, antifuse type and FLASH type according to the internal programmable principle. SRAM-type and FLASH-type FPGAs are widely used mainly in the civilian field, wherein SRAM-type FPGAs occupy a large market share. The conventional civil FPGA does not have the anti-irradiation capability and cannot meet the requirements of the complex irradiation environment fields such as aerospace military industry and the like.

The antifuse-type FPGA is a one-time programmable device due to the particularity of the antifuse unit, so that the antifuse FPAG has the advantages of high read-write speed, low power consumption, wide application temperature range, strong irradiation resistance, safety, strong confidentiality, hundreds of measurements and the like in the programming use process, and is widely applied to the complex fields of aerospace, aviation, military and the like. According to the long-term design research on the antifuse FPGA circuit, the flexible and reliable programming test circuit structure is very important for the programming test process of the antifuse FPGA. During circuit programming, a reliable and stable programming voltage waveform, a half programming voltage waveform, is required. During the testing process, a hundred percent test may be implemented. In normal operation, a very stable and reliable operating voltage is required.

Disclosure of Invention

The invention aims to provide a multi-level selection structure applied to an antifuse FPGA (field programmable gate array), so that the antifuse FPGA can flexibly perform programming, testing and normal working modes, and the programming test working efficiency of a circuit is improved.

In order to solve the above technical problem, the present invention provides a multi-level selection structure applied to an antifuse FPGA, wherein the multi-level selection structure comprises:

the programming method comprises the steps that a first path is used for applying programming voltage VPP to one end of an antifuse to be programmed to carry out high-voltage programming;

a second path providing voltage VKS for unprogrammed antifuses for pre-charge protection;

the third path is used for enabling the control signal to start the charge pump circuit after the programming of the antifuse FPGA circuit is finished, and an output signal of the charge pump circuit starts the third path to provide a working voltage VCCA for a unit connected with the antifuse;

and a fourth path for applying a low voltage GND to the other end of the antifuse to be programmed during programming to realize programming of the antifuse.

Optionally, the first path includes NMOS transistors NM1 and NM2, and the input signal VIN of the NMOS transistor NM1 is derived from a level shift circuit in a previous stage;

in the programming process, the magnitude of the input signal VIN is the voltage VSV, the NMOS transistor NM1 turns on the NMOS transistor NM2 through the voltage VSV, outputs the programming voltage VPP to the node Z, and applies the programming voltage VPP to one end of the antifuse after passing through a control-path NMOS transistor, thereby performing high-voltage programming on the antifuse.

Optionally, the second path comprises PMOS tubes PM 1-PM 4 and NMOS tube NM 4;

the gate voltages of the PMOS transistor PM2 and the PMOS transistor PM3 are low voltages, the substrate voltage is VSV, and the PMOS transistor PM2 and the PMOS transistor PM3 are in a conducting state;

the gate voltage of the NMOS transistor NM4 comes from the power-on start module, and when precharging, a high level VKS _ CTRL may be output, and the NMOS transistor NM4 is turned on;

the gate voltage of the PMOS tube PM4 is connected with a low voltage GND, the substrate voltage is VSV, and the PMOS tube PM4 is conducted;

the voltage VKS is output to a node Z through the conducted PMOS tube PM2, PMOS tube PM3, PMOS tube PM4 and NMOS tube NM4, and then is applied to an unprogrammed antifuse, and the unprogrammed antifuse is subjected to a pre-charge protection measure to prevent from being programmed mistakenly.

Optionally, the third path includes a PMOS transistor PM1 and an NMOS transistor NM 3;

the gate voltage of the NMOS tube NM3 comes from the output high level of a charge pump circuit in the antifuse FPGA circuit, and the NMOS tube NM3 is conducted;

the gate voltage of the PMOS transistor PM1 is low, and the PMOS transistor PM1 is conducted;

the operating voltage VCCA is output to the node Z through two transistors, a PMOS transistor PM1 and an NMOS transistor NM3, and then applied to the antifuse to supply the operating voltage VCCA to the cell connected to the antifuse.

Optionally, the fourth path includes an NMOS transistor NM5, where the NMOS transistor NM5 is turned on to output a low voltage GND to a node Z; in the programming of the antifuse, a low voltage GND is applied to the other end of the antifuse through a node Z, and programming of the antifuse is realized.

Optionally, when performing a pre-charge protection measure on an unprogrammed antifuse, applying a programming voltage VPP to one end of the antifuse unit, and applying a voltage VKS to the other end of the antifuse unit; the voltage VKS is half of the programming voltage VPP, and the voltage difference across the antifuse is 1/2 VPP.

The invention provides a multi-level selection structure applied to an antifuse Field Programmable Gate Array (FPGA), which comprises a first path, a second path and a third path, wherein the first path is used for applying programming voltage VPP to one end of an antifuse to be programmed to perform high-voltage programming; a second path providing voltage VKS for unprogrammed antifuses for pre-charge protection; the third path is used for enabling the control signal to start the charge pump circuit after the programming of the antifuse FPGA circuit is finished, and an output signal of the charge pump circuit starts the third path to provide a working voltage VCCA for a unit connected with the antifuse; and a fourth path for applying a low voltage GND to the other end of the antifuse to be programmed during programming to realize programming of the antifuse. With this configuration, stable and reliable antifuse cell programming voltage VPP, half programming voltage VKS (1/2 VPP), internal block operating voltage VCCA and low voltage GND (0) and test read internal some wiring signals can be obtained. Different working modes can be selected to be started through an external control signal, different level voltages are output, and programming reliability of the anti-fuse unit is guaranteed. The structure can flexibly realize different modes of programming, testing, working and the like of the antifuse FPGA circuit, and greatly improves the programming test efficiency of the antifuse FPGA circuit.

Drawings

FIG. 1 is a schematic diagram of a multi-level selection architecture for an antifuse FPGA, as provided by the present invention;

FIG. 2 is a schematic diagram of an example of a multi-level selection architecture for an antifuse FPGA to obtain data for a transmitted programming code stream in accordance with the present invention;

FIG. 3 is an example schematic diagram of a multi-level selection architecture in accordance with the present invention as applied to anti-fuse cell programming and pre-programming operations;

FIG. 4 is a schematic diagram of an example of the internal wiring test applied to an antifuse FPGA circuit in accordance with the multi-level selection architecture of the present invention.

Detailed Description

The multi-level selection structure applied to the antifuse FPGA according to the present invention is further described in detail with reference to the accompanying drawings and the specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Example one

The invention provides a multi-level selection structure applied to an antifuse Field Programmable Gate Array (FPGA). As shown in fig. 1, the multi-level selection structure includes 5 types of voltage sources, which are a programming voltage VPP of the antifuse, a voltage VSV for controlling the turn-on and turn-off of a programming pass transistor, a voltage VKS (1/2 VPP, also called a half-programming voltage) for the antifuse precharge, a voltage VCCA for normal operation after the antifuse programming, and a low voltage GND for supplying a low voltage when the antifuse cell is programmed.

Referring to fig. 1, in the first path 1, during programming of the antifuse, a programming voltage VPP is applied to one end of the antifuse to be programmed to perform high-voltage programming, and a conductive filament is formed inside the MTM antifuse cell, so that the two ends can be permanently connected. The input signal VIN of the NMOS transistor NM1 is derived from the level shift circuit of the previous stage, during the programming process, the input signal VIN is a voltage VSV, the NMOS transistor NM1 can transmit the voltage VSV to the gate of the NMOS transistor NM2 without loss, thereby turning on the NMOS transistor NM2, outputting the programming voltage VPP to the node Z without loss, the node Z passes through a control path NMOS transistor, and finally the programming voltage VPP is applied to one end of the antifuse without loss, and the antifuse is programmed with high voltage.

In the second path 2, the antifuse is supplied with a precharge voltage VKS. In the pre-charging process, the gate voltages of the PMOS tube PM2 and the PMOS tube PM3 are low, the substrate voltage is VSV, and the PMOS tube PM2 and the PMOS tube PM3 are in a conducting state; the gate voltage of the NMOS transistor NM4 is derived from the power-up start module, and when precharging, a high level VKS _ CTRL may be output, and the NMOS transistor NM4 is turned on. The gate voltage of the PMOS transistor PM4 is generally directly connected to the low voltage GND, the substrate is at the voltage VSV, and the PMOS transistor PM4 is turned on. The voltage VKS passes through the conducting PMOS tube PM2, PMOS tube PM3, PMOS tube PM4 and NMOS tube NM4, the voltage is output to the node Z without damage, and then is applied to the unprogrammed antifuse, and the unprogrammed antifuse is subjected to a pre-charge protection measure to prevent the unprogrammed antifuse from being programmed by mistake. In the process, a programming voltage VPP is applied to one end of the antifuse, a voltage VKS is applied to the other end of the antifuse, the voltage VKS is half of the programming voltage VPP, the voltage difference between two ends of the antifuse is 1/2 VPP, and the voltage difference cannot meet the requirement of the condition of the programming voltage difference VPP of the antifuse, so that the antifuse unit is prevented from being programmed by mistake. The 4 signals VKS 1-VKS 4 are enabling control signals for controlling the opening of the second channel, VKS1 and VKS2 are from a large number of data registers in the anti-fuse FPGA circuit, VKS3 is from a GND signal, and VKS4 is from a power-on starting circuit.

In the third circuit 3, after the antifuse FPGA circuit is programmed, and after the circuit function is solidified, when the circuit starts to operate normally, an external enable control signal turns on the charge pump circuit, the gate voltage of the NMOS transistor NM3 comes from the charge pump circuit inside the antifuse FPGA circuit to output a high level, and the NMOS transistor NM3 is turned on. The charge pump circuit is a special module in the antifuse FPGA circuit, and provides enabling signals for relevant units when the charge pump circuit starts to a normal working mode after the antifuse FPGA circuit is programmed. The gate voltage of the PMOS transistor PM1 is low, and the PMOS transistor PM1 is turned on. The working voltage VCCA is outputted to the node Z through two transistors, a PMOS transistor PM1 and an NMOS transistor NM3 without loss, and then applied to the antifuse to supply the working voltage VCCA to the cell connected to the antifuse. In fig. 1, VCC _ S1 is a control signal of PMOS transistor PM1, which is derived from an output signal of a register decoder inside the circuit, and when the circuit operates normally, the signal is at low level, and PMOS transistor PM1 is turned on; VCC _ S2 is the output signal of the charge pump circuit, when the circuit works normally, the signal is high level, the NMOS tube NM3 is turned on;

the circuit in the fourth path 4 provides a low voltage GND, which can be outputted to the node Z by turning on the NMOS transistor NM5, and when the antifuse is programmed, the low voltage is applied to the other end of the antifuse to be programmed, and finally, the programming of the antifuse is realized.

Fig. 2 is a schematic diagram of an example of obtaining data for a transport programming code stream in accordance with the principles of the present invention. When the anti-fuse FPGA circuit is programmed, a programming configuration code stream is loaded into the anti-fuse FPGA circuit through a JTAG circuit pin, data are transmitted in series through a shift register chain inside the circuit, data series-parallel conversion is carried out under the control of a TAP state machine circuit inside the anti-fuse FPGA, configuration data are stored into a rear-stage latch, a last-stage programmable structure can obtain configuration information, and then operations such as preprogramming and programming are carried out on a related anti-fuse. In the process, two D trigger units jointly act on a programmable and tested multi-voltage selection circuit structure, wherein one of the D trigger units is an enable bit, and the other D trigger unit is a data bit.

Fig. 3 is a schematic diagram of an example of an anti-fuse cell programming and pre-programming operation in accordance with the principles of the present invention. On the basis of the circuit configuration of fig. 2, the anti-fuse cell is programmed and pre-programmed. When programming an antifuse cell, the antifuse cell is addressed for programming first through the addressing register chain, and then configuration code stream fill programming is performed through the shift register chain of fig. 2. When programming, one end of the anti-fuse unit applies a programming voltage VPP, the other end of the anti-fuse unit is grounded at a low voltage GND, and the voltage difference between the two ends of the anti-fuse unit is VPP, the anti-fuse unit is burnt and broken down. In this process, it is necessary to protect the unprogrammed antifuse cell from being programmed by mistake because, as shown in the schematic diagram of fig. 3, the programming voltage VPP is applied to all antifuses in the row when the programming voltage VPP is applied to the antifuse cell, and in order to prevent other antifuse cells from being programmed by mistake, the voltage VKS is applied to the other end of the unprogrammed antifuse cell, and the voltage difference between the two ends is 1/2 VPP, so that the programming voltage condition is not reached, and the antifuse cell is protected.

Fig. 4 is a schematic diagram of an example of testing of internal wiring applied to an antifuse FPGA circuit in accordance with the principles of the present invention. On the basis of fig. 2, a read-back (Readback) functional module is added, internal wiring signals of the antifuse FPGA circuit can be acquired and read through the structure of fig. 1, the acquired internal wiring signals are read back and filled into a shift register chain, the internal wiring signals are transmitted through a JTAG port TDO of the antifuse FPAG circuit, and whether internal wiring node signals are normal or not can be directly judged through acquiring, analyzing and comparing output data. By the structure, the internal wiring nodes of the test circuit can be analyzed in real time, and a very effective method for searching problems is provided for circuit design and research.

In summary, the multilevel output control structure applied to programming and testing of the antifuse FPGA provided by the present invention enables the antifuse FPGA circuit to flexibly implement different modes such as programming, preprogramming, normal operation, testing, and the like. The invention can greatly improve the working efficiency of the antifuse FPGA.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims

1. A multi-level selection architecture for application to an antifuse FPGA, the multi-level selection architecture comprising:

a fourth path, which is used for applying a low voltage GND to the other end of the anti-fuse for programming during programming to realize the programming of the anti-fuse;

the first path comprises NMOS transistors NM1 and NM2, and an input signal VIN of the NMOS transistor NM1 is derived from a level conversion circuit at the previous stage; in the programming process, the magnitude of an input signal VIN is voltage VSV, the NMOS tube NM1 opens the NMOS tube NM2 through the voltage VSV, a programming voltage VPP is output to a node Z, and after passing through a control path NMOS transistor, the programming voltage VPP is applied to one end of an antifuse to perform high-voltage programming on the antifuse;

the second path comprises PMOS tubes PM 2-PM 4 and an NMOS tube NM 4; the gate voltages of the PMOS transistor PM2 and the PMOS transistor PM3 are low voltages, the substrate voltage is VSV, and the PMOS transistor PM2 and the PMOS transistor PM3 are in a conducting state;

2. The multi-level selection structure applied to an antifuse FPGA of claim 1, wherein the third path comprises a PMOS transistor PM1 and an NMOS transistor NM 3;

3. The multi-level selection structure applied to an antifuse FPGA of claim 2, wherein the fourth path includes an NMOS transistor NM5, the NMOS transistor NM5 is turned on to output a low voltage GND to a node Z; in the programming of the antifuse, a low voltage GND is applied to the other end of the antifuse through a node Z, and programming of the antifuse is realized.

4. The multi-level selection architecture for antifuse FPGAs as claimed in claim 1, wherein, when performing the pre-charge protection for the unprogrammed antifuse, the voltage VPP is applied to one terminal of the antifuse cell and the voltage VKS is applied to the other terminal; the voltage VKS is half of the programming voltage VPP, and the voltage difference across the antifuse is 1/2 VPP.