CN106528466B - Data exchange system and method between a kind of spaceborne computer internal processor unit and I/O-unit - Google Patents
Data exchange system and method between a kind of spaceborne computer internal processor unit and I/O-unit Download PDFInfo
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- CN106528466B CN106528466B CN201610907762.9A CN201610907762A CN106528466B CN 106528466 B CN106528466 B CN 106528466B CN 201610907762 A CN201610907762 A CN 201610907762A CN 106528466 B CN106528466 B CN 106528466B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/22—Handling requests for interconnection or transfer for access to input/output bus using successive scanning, e.g. polling
- G06F13/225—Handling requests for interconnection or transfer for access to input/output bus using successive scanning, e.g. polling with priority control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1684—Details of memory controller using multiple buses
Abstract
Data exchange system and method between a kind of spaceborne computer internal processor unit and I/O-unit, devising one has the autonomous controller for executing I O access instruction capabilities, and CPU can directly access I/O controller or realize data interaction by a high-speed memory and I/O controller.Processor can prestore the instruction for needing I/O controller to execute into high-speed memory, then memory instructions are read automatically by I/O controller and execute corresponding operating, the next step instruction of processor is waited after end of operation, significant effect of the present invention, evade influence of the IO to the processor speed of service at a slow speed, gives full play to processor performance；Customized three bus design between interiors of products veneer is eliminated, the standardized designs of veneer are conducive to；The frequent I O access operation of application software is avoided, software programming realization is conducive to.
Description
Technical field
The present invention relates between a kind of spaceborne computer internal processor unit and I/O-unit data exchange system and side
Method belongs to the Data Interchange Technology field between spaceborne computer internal processor unit and I/O-unit, is suitable for various spaceborne
High-performance calculation occasion especially needs big data quantity acquisition to need the occasion of high performance computation again.
Background technique
Processor is generallyd use inside spaceborne computer, and the data that three buses directly access I O board are controlled by data address
Exchanged form, as shown in Figure 1, CPU directly issues control (reading or writing) when CPU accesses exterior I O under customized three bus mode
Signal and corresponding address or data-signal.Above-mentioned three kinds of signals must maintain certain signal amplitude and time (to be appreciated that
For the waveform met certain condition), IO could correctly respond the read-write operation of CPU.
If IO speed is slow, CPU can be inserted into certain waiting time in read and write access, and signal sequence is made to meet IO
Requirement.But there is a upper limit in the waiting time of CPU insertion.
The dominant frequency of spaceborne computer processor is improved with fast speed at present, and I O access is limited by the rare change of peripheral hardware speed
Change.Processor processing speed is fast, and IO response speed is slow, processor again cannot the unconfined insertion waiting time, cause processor
It is difficult to directly access IO.Perhaps frequency reducing runs or waits for an I O access by once shaking hands for a long time processor.
If continuing to continue to use the structure of three buses, the performance of CPU cannot be not fully exerted.
Summary of the invention
Present invention solves the technical problem that are as follows: it overcomes the shortage of prior art, a kind of spaceborne computer internal processor is provided
Data exchange system and method between unit and I/O-unit provide and a kind of design simple, agile and all-purpose spaceborne computer
Method for interchanging data between processor unit and IO solves existing high speed processor and is difficult to directly to access IO at a slow speed to ask
Topic, gives full play to the performance of processor.
A kind of technical solution of the invention are as follows: the data between spaceborne computer internal processor unit and I/O-unit
Exchange system, it is characterised in that: including CPU, bus control unit, timing control unit, SRAM, SpaceWire controller, IO
Unit；
SpaceWire controller includes host bus interface (HOCI), SpaceWire interface and memory access interface
(COMI)；
CPU has local bus LOCAL BUS；
Interconnection of the host bus interface (HOCI) for realizing CPU and SpaceWire controller, Spacewire controller
It is articulated on the local bus LOCAL BUS of CPU by HOCI interface, CPU can directly access SpaceWire by HOCI interface
Controller；
SpaceWire controller connects I/O-unit by SpaceWire interface, and I/O-unit is for realizing SpaceWire control
The bridging functionality of device and peripheral hardware processed；
SpaceWire controller accesses local cache SRAM by COMI interface；
CPU setting COMI needs the reception initial address of reading and writing data, receives end address, send initial address, send
End address；COMI is established to need the transmission end address of reading and writing data and receive initial address, receive end address, send
Mapping relations between beginning address；CPU is existing by directly operation HOCI cause for gossip to the setting of COMI mouthfuls of above-mentioned functions；
Multiple data storage cells are set in SRAM, and an address is arranged in each storage unit, when COMI will be from SRAM
When reading data, the transmission initial address of the data storage cell that COMI is read according to needs of setting and transmission end address from
Automatic sequence reads data in SRAM；When COMI will be to data be written in SRAM, COMI is according to the received number of needs of setting
Data are written according to reception initial address and reception the end address automatic sequence into SRAM of storage unit；
CPU includes universal input/output interface GPIO, when universal input/output interface GPIO is high level, universal input
Output interface GPIO gives timing control unit high level signal, and timing control unit carries out level after receiving high level signal
It is converted to low level, exports low level signal to bus control unit, bus control unit is receiving timing control unit
When the low level signal of transmission, the bus communication between CPU and SRAM can be connected, CPU is able to access that SRAM, i.e., to SRAM write
Enter data, and data there are the transmission initial address of the COMI data storage cell for needing to be written and are sent between end address
Data storage cell in, and forbid SpaceWire controller access SRAM；The data that CPU write enters are divided into two types, pass through
Write command and reading instruction are divided into the instruction having before data, and the data after write command are sent to outside, reading instruction by write command
Data are read back from outside；
When universal input/output interface GPIO is set to low level, universal input/output interface GPIO is to timing control unit
Low level signal, timing control unit carry out level conversion and obtain high level, give bus marco list after receiving low level signal
Member output high level signal, bus control unit can be disconnected when receiving the high level signal of timing control unit transmission
Bus communication between CPU and SRAM, while SpaceWire controller being allowed to access SRAM；
Then it is low level by universal input/output interface GPIO, the transmission end address of COMI is set, according to COMI need
The transmission end address of reading and writing data is wanted, SpaceWire controller can be automatically from the data of the transmission initial address in SRAM
Storage unit starts to read data, terminates reading data to end address is sent, and the data of reading are connect by SapceWire
Mouth is sent to I/O-unit, completes data and sends；When input/output interface GPIO is low level, SpaceWire controller passes through
The data that SpaceWire interface receives are stored into SRAM from initial address is received to the corresponding data storage in reception end address
In unit, data receiver is completed；
After completing data transmission and data output, SpaceWire controller exports a negative arteries and veins to timing control unit
Signal is rushed, timing control unit is sent after the undersuing for receiving the transmission of SpaceWire controller to bus control unit
Low level signal, bus control unit receive timing control unit transmission low level signal when, can be connected CPU with
Bus communication between SRAM, while SpaceWire controller being forbidden to access SRAM；
CPU completes data when SpaceWire controller and sends out every the state of set time inquiry SpaceWire controller
It send and data receiver, universal input/output interface GPIO is set to high level, data CPU is from initial address is received to receiving end
Data are sequentially read in the corresponding data storage cell in location；
SpaceWire controller is sent to by I/O-unit by the data with write command that SpaceWire link is sent
Peripheral hardware；
SpaceWire controller sends reading instruction to I/O-unit, and after I/O-unit receives reading instruction, external data is read
Enter, SpaceWire controller is recycled to by SpaceWire link.
I/O interface receives the data that SpaceWire controller is sent, and is converted into the local bus (LOCAL of IO
BUS), corresponding read-write operation is carried out.
IO is received the data with write command and is sent to outside by I/O interface；
I/O interface is received with reading instruction, and external data is read in, and is recycled to by SpaceWire link
SpaceWire controller.
The advantages of the present invention over the prior art are that:
(1) present invention evades influence of the IO to the processor speed of service at a slow speed, gives full play to processor performance；
(2) present invention eliminates customized three bus design between interiors of products veneer, be conducive to the standardization of veneer
Design；
(3) present invention avoids the frequent I O access operation of application software, is conducive to software programming realization.
Detailed description of the invention
Fig. 1 is to generally use processor inside current spaceborne computer directly to access IO by three buses of data address control
The system diagram of the data exchange ways of plate；
Fig. 2 is whole functional block diagram of the invention；
Fig. 3 is the further explanation of dotted box portion in Fig. 2；
The processor of the present invention and I/O data interaction figure, (a) of Fig. 4 is write for processor, (b) sends for SpaceWire, (c)
For data loopback.
Specific embodiment
A kind of basic ideas of the invention are as follows: the data exchange between spaceborne computer internal processor unit and I/O-unit
System and method, devising one has the autonomous controller for executing I O access instruction capabilities, and CPU can directly access IO control
Device can also realize data interaction by a high-speed memory and I/O controller.Processor can will need I/O controller to execute
Instruction is prestored into high-speed memory, is then read memory instructions automatically by I/O controller and is executed corresponding operating, has operated
The next step instruction of processor is waited after finishing, significant effect of the present invention has evaded influence of the IO to the processor speed of service at a slow speed,
Give full play to processor performance；Customized three bus design between interiors of products veneer is eliminated, the standard of veneer is conducive to
Change design；The frequent I O access operation of application software is avoided, software programming realization is conducive to.
The invention will be described in further detail in the following with reference to the drawings and specific embodiments,
As shown in figure 3, arbitrary high speed processor can be selected in CPU, the present invention selects Atmel company to produce AT697F.
SpaceWire controller selects BM4802, and BM4802 is selected to be based on from the aspect of two: first is that itself supporting to specify to send starting
Address sends the block data-transformation facility after termination address, can be using external large capacity SRAM as data storage cell；Second is that
BM4802 can not limit the speed of service of processor by the access of high speed processor.
Bus control unit and timing control unit are built using discrete device, main one GPIO mouthful using CPU with
Transmission mark COCI and COCO of BM4802 etc. are realized, by foregoing circuit, BM4802 and CPU can be shared using a piece of SRAM,
Realize data exchange between the two.
BM4802 externally passes through the exportable three roads SpaceWire of LVDS interface chip, every one IO of road SpaceWire connection
Unit, i.e. whole system can connect three I/O-units.As shown in Fig. 2, the letter that I/O-unit can will be sent by SpaceWire
Breath is converted into the local bus inside I/O-unit, and IO local bus herein can match the I/O peripheral of access at a slow speed.The present invention
I/O-unit is realized using FPGA (ACTEL company A54SX72A), and intelligent processing unit realization can also be used in practical application.
With processor from I O read data instance, following three step can be divided into:
A) processor issues instruction
B) I/O-unit, which executes instruction, adopts number and removes number
C) processor reads data
Shown in the information flow respectively walked such as Fig. 4 (a), Fig. 4 (b), Fig. 4 (c).
In actual use, a plurality of instruction or pending data can be pre-stored among " cache " by processor, then
Notice I/O controller starts to execute in batches instruction, and after instruction execution, processor reads data from cache again.IO
The process executed instruction is intervened without processor, other tasks can be performed in processor at this time.
Assuming that the working frequency of processor is f, the I O access response time is t1, and processor need to continuously acquire N word from IO
Joint number evidence, but access can only obtain 1 byte every time.If f and t1 are not matched that, such as preferred f=100MHz, t1=1us, processor
IO can not be directly accessed, unless processor reduces working frequency and is inserted into the sufficient amount of waiting time simultaneously, obtains N byte at this time
Total time-consuming be T1=N*t1.
After design of the invention, the processor single reference time is solely dependent upon I/O controller and cache.This
Invention require I/O controller and cache that can directly be accessed by high speed processor, it is assumed that the response time be t2 (should have t2 < <
t1).It is about T2=N*t2+ Δ t that processor, which obtains the total time-consuming of N byte, at this time, and Δ t is that processor issues the instruction time.
The efficiency that processor improves in I O access is
Due to t1 > > t2, Δ t is usually smaller to be influenced can be neglected in big data quantity access, and processor is in I O access
When efficiency can greatly improve.Such as t1=1us, t2=100ns, it is 90% that I O access, which improves efficiency,.
Claims (2)
1. the data exchange system between a kind of spaceborne computer internal processor unit and I/O-unit, it is characterised in that: including
CPU, bus control unit, timing control unit, SRAM, SpaceWire controller, I/O-unit；
SpaceWire controller includes host bus interface (HOCI), SpaceWire interface and memory access interface
(COMI)；
CPU has local bus LOCAL BUS；
For realizing the interconnection of CPU and SpaceWire controller, Spacewire controller passes through host bus interface HOCI
HOCI interface is articulated on the local bus LOCAL BUS of CPU, and CPU can directly access SpaceWire control by HOCI interface
Device processed；
SpaceWire controller connects I/O-unit by SpaceWire interface, and I/O-unit is for realizing SpaceWire controller
With the bridging functionality of peripheral hardware；
SpaceWire controller accesses local cache SRAM by COMI interface；
CPU setting COMI needs the reception initial address of reading and writing data, reception end address, transmission initial address, transmission to terminate
Address；COMI is established to need the transmission end address of reading and writing data and receive initial address, receive end address, send starting point
Mapping relations between location；CPU is existing by directly operation HOCI cause for gossip to the setting of COMI；
Multiple data storage cells are set in SRAM, and an address is arranged in each storage unit, when COMI will be read from SRAM
When data, the transmission initial address for the data storage cell that COMI is read according to the needs of setting and end address is sent from SRAM
Middle automatic sequence reads data；When COMI will be to data be written in SRAM, COMI is deposited according to the received data of needs of setting
Data are written in reception initial address and reception the end address automatic sequence into SRAM of storage unit；
CPU includes universal input/output interface GPIO, when universal input/output interface GPIO is high level, universal input output
Interface GPIO gives timing control unit high level signal, and timing control unit carries out level conversion after receiving high level signal
Low level is obtained, exports low level signal to bus control unit, bus control unit is receiving timing control unit transmission
Low level signal when, the bus communication between CPU and SRAM can be connected, CPU is able to access that SRAM, i.e., enters number to SRAM write
According to, and data there are the transmission initial address of the COMI data storage cell for needing to be written and are sent into the number between end address
According in storage unit, and SpaceWire controller is forbidden to access SRAM；The data that CPU write enters are divided into two types, pass through data
Write command and reading instruction are divided into the preceding instruction having, and the data after write command are sent to outside by write command, and reading instruction will count
It reads back according to from outside；
When universal input/output interface GPIO is set to low level, universal input/output interface GPIO gives timing control unit low electricity
Ordinary mail number, timing control unit carries out level conversion and obtains high level after receiving low level signal, defeated to bus control unit
High level signal out, bus control unit receive timing control unit transmission high level signal when, can disconnect CPU with
Bus communication between SRAM, while SpaceWire controller being allowed to access SRAM；
Then universal input/output interface GPIO is set to low level, the transmission end address of COMI is set, according to COMI needs
The transmission end address of reading and writing data, SpaceWire controller can be deposited from the data of the transmission initial address in SRAM automatically
Storage unit starts to read data, terminates reading data to end address is sent, and the data of reading are passed through SpaceWire interface
It is sent to I/O-unit, data is completed and sends；When input/output interface GPIO is low level, SpaceWire controller passes through
The data that SpaceWire interface receives are stored into SRAM from initial address is received to the corresponding data storage in reception end address
In unit, data receiver is completed；
After completing data transmission and data output, SpaceWire controller exports a negative pulse letter to timing control unit
Number, timing control unit sends low electricity after the undersuing for receiving the transmission of SpaceWire controller, to bus control unit
Ordinary mail number, bus control unit when receiving the low level signal of timing control unit transmission, can be connected CPU and SRAM it
Between bus communication, while forbid SpaceWire controller access SRAM；
CPU every the set time inquiry SpaceWire controller state, when SpaceWire controller complete data send and
Data receiver, universal input/output interface GPIO are set to high level, and CPU is corresponding to end address is received from initial address is received
Data are sequentially read in data storage cell；
I/O-unit receives the data that SpaceWire controller is sent by SpaceWire link, the number including having write command
Accordingly and reading instruction；
SpaceWire controller is sent to peripheral hardware by the data with write command that SpaceWire link is sent by I/O-unit；
SpaceWire controller sends reading instruction to I/O-unit, and after I/O-unit receives reading instruction, external data is read in, and leads to
It crosses SpaceWire link and is recycled to SpaceWire controller.
2. the method for interchanging data between a kind of spaceborne computer internal processor unit and I/O-unit, it is characterised in that step is such as
Under:
(1) it is initialized, i.e., SpaceWire controller includes memory access interface COMI, and CPU setting COMI needs data
The reception initial address of read-write receives end address, sends initial address, sends end address；Establishing COMI needs data to read
That writes sends end address and reception initial address, receives end address, sends the mapping relations between initial address；
(2) when setting high level for universal input/output interface GPIO, universal input/output interface GPIO gives timing control list
First high level signal, timing control unit carry out level conversion and obtain low level, give bus marco after receiving high level signal
Unit exports low level signal, and bus control unit can be led when receiving the low level signal of timing control unit transmission
Data can be written in bus communication between logical CPU and SRAM, CPU into SRAM, and data are divided into two types, before data
Write command and reading instruction are divided into the instruction having, and the data after write command are sent to outside by write command, and reading instruction is by data
It reads back from outside；
(3) after step (2) complete data write-in, when universal input/output interface GPIO is set to low level, universal input output
Interface GPIO gives timing control unit low level signal, and timing control unit carries out level conversion after receiving low level signal
High level is obtained, exports high level signal to bus control unit, bus control unit can disconnect total between CPU and SRAM
Line communication, while SpaceWire controller being allowed to access SRAM；
(4) then the transmission end address of COMI is set, the transmission end address of reading and writing data is needed according to COMI,
SpaceWire controller can read data since the data storage cell of the transmission initial address in SRAM automatically, to hair
It send end address to terminate reading data, and these data of reading is sent to I/O interface, complete data and send, carry out step
(5) and step (6)；
(5) I/O-unit receives the data that send of SpaceWire controller, when I/O-unit receives the data with write command,
Outside is sent by the data with write command；When I/O-unit is received with reading instruction, external data is read in, is passed through
SpaceWire link is recycled to SpaceWire controller, and SpaceWire controller stores the data received into SRAM
From initial address is received to receiving in the corresponding data storage cell in end address, data receiver is completed；
(6) CPU inquires the state of SpaceWire controller within the set time of setting, when inquiring SpaceWire controller
Complete that data are sent and the received state of data, universal input/output interface GPIO are set to high level, CPU is from receiving initial address
Data are sequentially read to receiving in the corresponding data storage cell in end address；It is completed when not inquiring SpaceWire controller
Data are sent and the received state of data, carry out step (7)；
(7) after completing data receiver, SpaceWire controller exports a undersuing, timing to timing control unit
Control unit sends low level signal after the undersuing for receiving the transmission of SpaceWire controller, to bus control unit,
Bus control unit can be connected total between CPU and SRAM when receiving the low level signal of timing control unit transmission
Line communication, while SpaceWire controller being forbidden to access SRAM.
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| CN201610907762.9A CN106528466B (en) | 2016-10-18 | 2016-10-18 | Data exchange system and method between a kind of spaceborne computer internal processor unit and I/O-unit |
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| CN103140830A (en) * | 2010-10-01 | 2013-06-05 | 华为技术有限公司 | System and method for controlling the input/output of a virtualized network |
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|---|---|---|---|---|
| EP2541851A1 (en) * | 2011-06-30 | 2013-01-02 | Astrium Limited | Apparatus and method for use in a spacewire-based network |
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|---|---|---|---|---|
| CN1540665A (en) * | 2003-04-21 | 2004-10-27 | ���ش�洢����ʽ���� | Memory modular and memory system |
| CN103140830A (en) * | 2010-10-01 | 2013-06-05 | 华为技术有限公司 | System and method for controlling the input/output of a virtualized network |
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| Title |
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| 计算机原理学习（2）--存储器和I/O设备和总线;cc_net;《CSDN》;20130829;全文 |
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