CN106486429A - Semiconductor chip package and its method for packing - Google Patents
Semiconductor chip package and its method for packing Download PDFInfo
- Publication number
- CN106486429A CN106486429A CN201510536960.4A CN201510536960A CN106486429A CN 106486429 A CN106486429 A CN 106486429A CN 201510536960 A CN201510536960 A CN 201510536960A CN 106486429 A CN106486429 A CN 106486429A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 238000000034 method Methods 0.000 title claims description 25
- 238000012856 packing Methods 0.000 title 1
- 238000007789 sealing Methods 0.000 claims abstract description 14
- 239000011248 coating agent Substances 0.000 claims abstract description 4
- 238000000576 coating method Methods 0.000 claims abstract description 4
- 239000002184 metal Substances 0.000 claims description 67
- 229910052751 metal Inorganic materials 0.000 claims description 67
- 239000000758 substrate Substances 0.000 claims description 62
- 238000004806 packaging method and process Methods 0.000 claims description 18
- 150000001875 compounds Chemical class 0.000 claims description 15
- 239000008393 encapsulating agent Substances 0.000 claims description 14
- 239000000084 colloidal system Substances 0.000 claims description 11
- 238000003466 welding Methods 0.000 claims description 11
- 238000001746 injection moulding Methods 0.000 claims description 10
- 239000012778 molding material Substances 0.000 claims description 6
- 238000005538 encapsulation Methods 0.000 claims description 5
- 239000011148 porous material Substances 0.000 claims description 4
- 239000007769 metal material Substances 0.000 claims description 3
- 239000002861 polymer material Substances 0.000 claims description 3
- 239000000853 adhesive Substances 0.000 abstract description 5
- 230000001070 adhesive effect Effects 0.000 abstract description 5
- 239000004020 conductor Substances 0.000 abstract 4
- 238000000338 in vitro Methods 0.000 abstract 1
- 238000000465 moulding Methods 0.000 description 16
- 229920005989 resin Polymers 0.000 description 14
- 239000011347 resin Substances 0.000 description 14
- 239000012790 adhesive layer Substances 0.000 description 12
- 239000010410 layer Substances 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 11
- 239000000463 material Substances 0.000 description 9
- 238000002347 injection Methods 0.000 description 8
- 239000007924 injection Substances 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 8
- 238000010438 heat treatment Methods 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 4
- 239000003292 glue Substances 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 238000012858 packaging process Methods 0.000 description 3
- 229910001020 Au alloy Inorganic materials 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 239000012812 sealant material Substances 0.000 description 2
- 230000002860 competitive effect Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
A kind of encapsulating structure of semiconductor chip, including:Chip, its active surface is configured with multiple pads；A plurality of plain conductor, its one end is electrically connected with pad；Lid, is formed by the top at multiple edges and closed edge, in order to coating chip and plain conductor；Adhesive body, is formed in lid, coating chip and plain conductor, and is exposed to the bottom of lid；Multiple metallic contacts, are exposed to sealing in vitro, and each metallic contact are integral with the other end electric connection of a plurality of plain conductor；Wherein, some edges of lid are configured with hole.
Description
Technical Field
The present invention relates to a semiconductor chip package structure, and more particularly, to a semiconductor chip package structure and a method for packaging the same, which can complete a packaging process without using a mold.
Background
Generally, after functional manufacturing of a semiconductor component is completed in a wafer factory, the semiconductor component needs to be cut into chips, and then the chips are electrically connected with a circuit board; then, putting the chip and the circuit board which are electrically connected into a mould, and injecting resin into the mould to completely coat the chip and the circuit board; and then, baking to cure the resin, thereby completing the packaging of the semiconductor assembly.
In the packaging process, the mold is a consumable material and needs to be manufactured individually according to different chip sizes; because the cost of manufacturing the mold by opening the mold is very high, the problem of cost increase is often caused in the competitive process of product manufacturing. In addition, each chip must be electrically connected to a circuit board, so that the circuit board is also one of the manufacturing costs.
In order to further reduce the packaging cost of the semiconductor chip, a simple packaging structure is required.
Disclosure of Invention
In view of the above, the present invention provides a semiconductor chip package structure, which includes a chip having an active surface provided with a plurality of bonding pads; one end of each metal wire is electrically connected with the welding point; the cover body is formed by a plurality of edges and the top of the closed edge and used for coating the chip and the metal wires; the sealing colloid is formed in the cover body, covers the chip and the metal wires and is exposed at the bottom of the cover body; a plurality of metal contacts exposed out of the surface of the encapsulation body, each metal contact being electrically connected with the other ends of the plurality of metal wires into a whole; wherein, some edges of the cover body are provided with pores.
According to the above object, the package structure of the present invention does not need to be processed by a mold, so as to effectively reduce the manufacturing cost. In addition, the packaging structure does not need to use a substrate, so that the manufacturing cost can be further reduced, and the height of the packaging structure can be reduced.
The present invention also provides a method for packaging a semiconductor chip, which comprises providing a substrate having a plurality of regions, each of the regions having a plurality of identification marks; providing chips in sequence, wherein a plurality of welding pads are arranged on the active surface of each chip, the bottom of the opposite active surface is fixedly connected to each area of the substrate and is arranged between the identification marks of each area; performing routing, namely electrically connecting one end of each metal wire with each welding pad in sequence, and electrically connecting the other end of each metal wire with each identification mark to form a metal contact; providing a cover body, forming a plurality of accommodating spaces with openings on one side, wherein each accommodating space of the cover body covers a chip and a metal wire and is fixedly connected with a substrate, and holes are arranged on the edges of the cover body; performing injection molding, namely injecting a molding material into each accommodating space in the cover body through the pores on the edge of the cover body to form sealing colloid, wherein each sealing colloid covers the chip and the metal wires; and stripping to separate the substrate from the sealing colloid and the cover body to expose the metal contact.
According to the above object, the packaging method of the present invention does not need to go through the process of mold, so as to effectively reduce the manufacturing cost. In addition, the packaging structure does not need to use a substrate, so that the manufacturing cost can be further reduced, and the height of the packaging structure can be reduced.
Drawings
FIG. 1A is a schematic top view of a substrate according to the present invention;
FIG. 1B is a schematic cross-sectional view of a substrate of the present invention;
FIG. 2 is a schematic top view of the substrate and chip combination of the present invention;
FIG. 3 is a schematic cross-sectional view of the chip of the present invention after wire bonding;
FIG. 4 is a bottom view of the cover of the present invention;
FIG. 5 is a schematic cross-sectional view of a cover covering a chip according to the present invention;
FIGS. 6A-6C are schematic cross-sectional views of an injection molding process of the present invention;
FIG. 7 is a bottom view of the present invention after stripping has been completed;
FIG. 8A is a bottom view of the completed package structure after dicing; and
fig. 8B is a schematic cross-sectional view of the completed package structure after dicing.
Detailed Description
To make the objects, features and advantages of the present invention more comprehensible and practical for a person skilled in the relevant art, the present invention is described in detail in the following description together with the accompanying drawings, and further illustrates preferred embodiments, which are not intended to limit the present invention and are shown in the figures referred to below.
First, please refer to fig. 1A and fig. 1B, wherein fig. 1A is a schematic top view of a substrate according to the present invention, and fig. 1B is a schematic cross-sectional view of the substrate according to the present invention. As shown in FIG. 1A, the substrate 10 of the present invention is made of a polymer material, such as a resin or AB glue. The substrate 10 can be divided into a plurality of die regions 14 for placing semiconductor devices, each die region 14 being divided by a dotted line. In addition, the substrate 10 of the present invention may have a certain hardness, or the substrate 10 may be baked to make the substrate 10 have a certain hardness. Then, a plurality of identification symbols 12 are formed at the peripheral position of the die region 14, each identification symbol 12 is a geometric shape, such as a cross symbol, and the material of each identification symbol 12 is a metal, such as gold or copper alloy. Each identifier 12 may be formed by metal deposition, electroplating or screen printing in a semiconductor process, as shown in FIG. 1B, but the invention is not limited thereto. In addition, the size of each identification symbol is 12 inches, which can be adjusted according to the number of pads 22 of the semiconductor device 20 to be packaged, and the invention is not limited thereto.
Next, please refer to fig. 2, which is a top view of the substrate and the chip of the present invention. As shown in fig. 2, the cut semiconductor devices 20 (e.g., DRAM or Flash memory) are placed one by one on the die area 14 of the substrate 10 by a pick and place mechanism (Handler), and the semiconductor devices 20 are disposed between each of the identifiers 12. In addition, the die region 14 of the substrate 10 on which the semiconductor device 20 is mounted can be fixed by using a resin (resin), especially a B-Stage resin or a resin with thermal conductivity, as the adhesion layer between the semiconductor device 20 and the substrate 10.
Referring to fig. 3, a top view of the substrate and the chip of the present invention is shown. As shown in fig. 3, a wire bonding machine (wire bonding machine) is used to connect the bonding pad 22 on each semiconductor device 20 to the identifier 12 of the substrate 10 by a metal wire 30 to form an electrical connection. In the preferred embodiment, when the wire bonder is used in a reverse wire bonding manner, the metal ball 32 is formed on the identification mark 12, and then the gold wire 30 is connected to the bonding pad 22 on the semiconductor device 20; in addition, in another embodiment of the invention, the wire bonding can also select to connect the gold wire 30 with the bonding pad 22 on the semiconductor device 20, then connect the metal wire 30 to the identification symbol 12, and form the metal ball 32 on the identification symbol 12; the metal ball 32 of the present invention is formed by connecting a metal material and the identification mark 12 on each substrate 10 into a whole by a wire bonder, and the diameter of each metal ball 32 can be 0.01 mm-0.5 mm. In addition, in the preferred embodiment of the present invention, an adhesive layer 50 can be formed on the die region 14, so as to fix the semiconductor device 20 by the adhesive layer 50; the adhesive layer 50 can be a curing adhesive, such as B-Stage curing adhesive; in addition, the adhesive layer 50 may also be a high thermal conductive resin, such as a thermal conductive adhesive formed by using epoxy resin as a main material.
Next, please refer to fig. 4A and fig. 4B, which are schematic diagrams of the bottom surface and the cross section of the cover body according to the present invention. As shown in fig. 4A, the cover 40 may be formed by injection molding to form a plurality of cover regions 42 having receiving spaces, wherein each cover region 42 is formed by a plurality of edges and a top portion closing the edges. The cover 40 may be precisely designed so that the receiving space of each cover region 42 can enclose the semiconductor devices 20 arranged at intervals and electrically connected to the substrate 10; the material of the cover 40 may be plastic or resin. In addition, in the design of the injection molded cover 40, the width of the four peripheries can be designed to be 0.5-1 mm, and in the embodiment of the present invention, the width of the four peripheries of the cover 40 is selected to be 0.5 mm; under the condition that the cutting line width needs about 1.2mm, the widths of other middle frames except the four peripheries are selected to be 2.2 mm; wherein the dashed lines in fig. 4A represent the positions of the cut lines 44. In addition, the cover body 40 of the present invention further forms a gap 46 in the middle area of each frame or the bottom of the frame, the width of which can be selected to be 1-5 mm, and the gap can be used as an inlet and an outlet of a subsequent injection mold. In this embodiment, the width of the aperture 46 is selected to be 2.5mm, as shown in FIG. 4B.
Next, please refer to fig. 5, which is a cross-sectional view illustrating a chip covered by a cover according to the present invention. As shown in FIG. 5, an adhesive layer (not shown) can be optionally formed on the bottom frame of the cover 40, and then the adhesive layer 50 is fixed to the substrate 10. Therefore, after the injection-molded cover regions 42 with the accommodating spaces are aligned, the semiconductor devices 20 arranged at intervals can be sealed, as shown in fig. 5.
Next, please refer to fig. 6A, fig. 6B and fig. 6C, which are schematic cross-sectional views illustrating an injection molding process according to the present invention. As shown in fig. 6A, after each of the cap regions 42 having a receiving space encloses the semiconductor device 20 on each of the substrates 10 and is fixed to the substrate 10 by the adhesive layer 50, a molding process of injection molding (molding) may be performed, wherein the molding material injected into the cap region 42 may be Epoxy resin (Epoxy) or low temperature glue. When the injected molding compound is injected into the accommodating space of the cover region 42 through the at least one aperture 46 of the injection molded cover 40, the injection port injects the molding compound as shown by the arrow in fig. 6A; with proper applied pressure, the injected sealant material can be completely filled into the accommodating space of the cap region 42; when the injected molding compound overflows from the aperture 46 on the other side of the cover 40, it means that the molding compound has completely filled into each cover region 42; finally, after a proper heating and baking, the encapsulating material can be cured, as shown in fig. 6B. According to the design of the cover body of the present invention, no mold is needed to be used in the packaging process of the semiconductor device 20, and the cover body is used instead, so that the cost for manufacturing the mold can be saved.
Next, referring to fig. 6C, a cross-sectional view of the substrate stripped package of the present invention is shown. As shown in fig. 6C, after the molding compound is completely filled into each cap region 42 and is subjected to a proper heating and baking, the molding compound is cured to form a molding compound for encapsulating the semiconductor device 20 in each cap region 42. Next, the substrate 10, the encapsulant and the cover edge are peeled off, so that the bottom of the encapsulant and the metal balls 32 are exposed, as shown in fig. 6C. In the preferred embodiment, after the molding compound is processed, the molding compound is first subjected to a low temperature thermal process to soften the substrate 10 and facilitate the peeling of the substrate 10 from the molding compound. In this embodiment, the low temperature thermal process can be selected to be 30-60 degrees. It is obvious that the package structure of the present invention does not need to use the substrate 10, which can further reduce the manufacturing cost and the height of the package structure.
Please refer to fig. 7, which is a bottom view of the peeled-off substrate of the present invention. As shown in fig. 7, when the substrate 10 and the encapsulant are peeled off, the bottom of the encapsulant and the metal balls 32 are exposed, and the bottom of the encapsulant and the metal balls 32 are on the same plane. In the preferred embodiment of the present invention, the metal layer 60 may be formed on the die region 14 in a manner that is performed simultaneously with the formation of the identifier 12. Thereafter, an adhesive layer 50 is formed on the metal layer 60 so as to be fixed to the semiconductor element 20 by the adhesive layer 50, wherein the adhesive layer 50 may be a high thermal conductive resin, such as a thermal conductive adhesive formed by using epoxy resin as a main material. When the substrate 10 and the encapsulant are peeled off, the metal layer 60 is exposed, as shown in FIG. 7. By the design of the metal layer 60, it can be used as the heat dissipation path of the semiconductor device 20; at this time, the bottom of the molding compound and the plurality of metal balls 32, i.e., the metal layer 60, are on the same plane.
Please refer to fig. 8A and 8B, which are a bottom view and a cross-sectional view of the package structure after the dicing process is completed. As shown in fig. 8A, after the substrate 10 and the encapsulant are peeled off, the bottom of the encapsulant, the metal balls 32 and the metal layer 60 are exposed; then, after forming Solder Paste (Solder Paste) on each metal Ball 32 exposed in the whole package structure, a Solder Ball (Solder Ball)16 is formed on each metal Ball 32 after a thermal process, so that the Solder Ball 16 protrudes out of the bottom of the package body.
Finally, after the dicing along the dicing lines by the laser, the packaging of the semiconductor device 20 can be completed, as shown in fig. 8B. Obviously, the injection molded cover body is used as a mold, so that the mold required by the traditional injection molding can be saved, and the manufacturing cost can be further reduced.
The present invention next provides a method for packaging a semiconductor chip, comprising:
providing a substrate 10, and forming a plurality of regions on the substrate 10, wherein each region is configured with a plurality of identification marks 12, wherein the substrate 10 is formed by a polymer material, such as AB glue; in addition, the substrate 10 can be divided into a plurality of die regions 14 for placing semiconductor devices. A plurality of identification symbols 12 are formed at the periphery of the die region 14, each identification symbol 12 is a geometric shape, such as a cross symbol, and the material of each identification symbol 12 is a metal, such as gold or copper alloy. Each identifier 12 may be formed by metal deposition, electroplating or screen printing in a semiconductor process, as shown in FIG. 1B, but the invention is not limited thereto.
And step two, providing the chips 20 in sequence, wherein the active surface of each chip 20 is provided with a plurality of welding pads 22, the bottom of the opposite active surface is fixedly connected to each grain region 14 of the substrate and is arranged between the identification marks 12 of each region. In addition, the die region 14 of the semiconductor device 20 placed on the substrate 10 can be fixed by using a resin (resin), especially a B-Stage resin, as the adhesion layer between the semiconductor device 20 and the substrate 10. In a preferred embodiment, the metal layer 60 is formed on the die region 14 in a manner that is substantially simultaneous with the formation of the identifier 12. Thereafter, an adhesive layer 50 is formed on the metal layer 60 so as to be fixed to the semiconductor element 20 by this adhesive layer 50.
Performing routing, namely electrically connecting one end of each metal wire 30 with each welding pad 22 in sequence, and electrically connecting the other end of each metal wire 30 with each identification mark 12 to form a metal ball 32; the metal ball 32 of the present invention is formed by connecting a metal material and the identification mark 12 on each substrate 10 into a whole by a wire bonder, and the diameter of each metal ball 32 can be between 1mm and 10 mm.
Step four, providing a cover body, wherein the cover body 40 can form a plurality of cover body areas 42 with accommodating spaces by using an injection molding mode, wherein each cover body area 42 is formed by a plurality of edges and the top of the closed edge. The cover 40 may be precisely designed so that the receiving space of each cover region 42 can enclose the semiconductor devices 20 arranged at intervals and electrically connected to the substrate 10; the material of the cover 40 may be plastic or resin. In addition, the cover 40 of the present invention is further provided with apertures 46 on some edges to serve as injection ports and exit ports for mold flow.
Step five, performing injection molding, namely injecting a molding material into each accommodating space 42 in the cover body 40 through at least one aperture 46 on the edge of the cover body 40, wherein the molding material injected into the cover body area 42 can be Epoxy resin (Epoxy) or low-temperature glue, etc. When the injected molding compound is injected into the accommodating space of the cap region 42 through the at least one aperture 46 on the injection molded cap 40, the injection opening is indicated by an arrow in fig. 6A; with proper applied pressure, the injected sealant material can be completely filled into the accommodating space of the cap region 42; when the injected molding compound overflows from the aperture 46 on the other side of the cap 40, it means that the molding compound has completely filled into each cap region 42. At this time, the encapsulant is formed to cover the chip and the metal wires.
Step six, heating is carried out, the sealing colloid can be subjected to a low-temperature thermal process firstly, so that the substrate 10 can be softened, and the substrate 10 and the sealing colloid can be conveniently stripped. In the embodiment, the low temperature thermal process can be selected to be 30-60 degrees. It should be noted that the heating step is a selection step, and whether to perform the heating step is determined according to the material of the substrate 10.
And step six, stripping is carried out, namely the substrate is separated from the sealing colloid and the cover body. When the substrate 10 and the encapsulant are peeled off, the bottom of the encapsulant and the metal balls 32 are exposed. When the metal layer 60 is disposed on the die region 14, the metal layer 60 is exposed after the substrate 10 and the encapsulant are stripped.
And step seven, forming Solder balls, namely forming Solder Paste (Solder Paste) on each metal Ball 32 exposed in the whole packaging structure, and forming the Solder balls (Solder Ball) on each metal Ball 32 after a thermal process so that the Solder balls 16 protrude out of the bottom of the sealing colloid. It should be noted that the step of forming solder balls is a selection step, and whether to execute the step may be determined according to whether the used package structure is a Land Grid Array (LGA) package or a Ball Grid Array (BGA) package; wherein, when the package structure is to form a BGA package structure, the step is performed.
Step eight, performing dicing along the dicing lines 44 by laser, and then packaging the semiconductor device 20, as shown in fig. 8A or fig. 8B.
Although the present invention has been described with reference to the above preferred embodiments, it is not intended to limit the present invention, and any person skilled in the art, for example, the semiconductor device 20 is not limited to a memory, as long as the die is formed by a semiconductor process, which is the object of the present invention; therefore, it is understood that various changes and modifications can be made without departing from the spirit and scope of the invention, and therefore, the scope of the invention should be determined by the appended claims.
Claims (10)
1. A semiconductor chip package comprising:
a chip, wherein a plurality of welding points are arranged on an active surface of the chip;
one end of each metal wire is electrically connected with the welding point;
the cover body is formed by a plurality of edges and a top part for sealing the edges and is used for coating the chip and the metal wires;
the sealing colloid is formed in the cover body, covers the chip and the metal wire and is exposed at the bottom of the cover body; and
a plurality of metal contacts exposed outside the sealing compound, wherein each metal contact is electrically connected with the other ends of the plurality of metal wires into a whole; wherein,
apertures are provided on some edges of the cover.
2. The package structure of a semiconductor chip according to claim 1, wherein the cover has a rectangular configuration.
3. The package structure of a semiconductor chip as claimed in claim 1, wherein the metal wires are formed by reverse wire bonding.
4. The package structure of claim 1, wherein the metal contacts exposed outside the encapsulant are Land Grid Array (LGA) structures.
5. The semiconductor chip package structure of claim 1, wherein the metal contacts exposed outside the encapsulant are Ball Grid Array (BGA) structures.
6. The package structure of claim 1, wherein the cover is made of a polymer material.
7. A method of packaging a semiconductor chip, comprising:
providing a substrate, wherein a plurality of identification marks are formed on the substrate;
providing a chip, wherein a plurality of welding points are arranged on an active surface of the chip, the bottom of the chip opposite to the active surface is fixedly connected to the substrate, and the chip is arranged between the identification marks;
performing routing, namely electrically connecting one end of each metal wire with the welding point, electrically connecting the other end of each metal wire with each identification mark and forming a metal contact;
providing a cover body, wherein an opening is formed in one side edge of the cover body to form an accommodating space, the chip and the metal wire are covered by the accommodating space and are fixedly connected with the substrate, and holes are arranged on some edges of the cover body;
performing injection molding, namely injecting a molding material into the cover body through the pores on the edge of the cover body to form an encapsulation body, wherein the encapsulation body covers the chip and the metal wires; and
and stripping is carried out, namely the substrate is separated from the sealing colloid and the cover body, so as to expose the metal contact.
8. A method of packaging a semiconductor chip, comprising:
providing a substrate, wherein a plurality of areas are formed on the substrate, and a plurality of identification marks are arranged on each area;
providing chips in sequence, wherein a plurality of welding points are arranged on the active surface of each chip, the bottom of each chip opposite to the active surface is fixedly connected to each area of the substrate and arranged between the identification marks of each area;
performing routing, namely electrically connecting one end of each metal wire with the welding point in sequence, and electrically connecting the other end of each metal wire with each identification mark to form a metal contact;
providing a cover body, forming a plurality of accommodating spaces with openings on one side edge, wherein each accommodating space of the cover body covers the chip and the metal wires and is fixedly connected with the substrate, and holes are arranged on some edges of the cover body;
performing injection molding, namely injecting a molding material into each accommodating space in the cover body through the pores on the edge of the cover body to form an encapsulation body, wherein each encapsulation body covers the chip and the metal wires; and
and stripping is carried out, namely the substrate is separated from the sealing colloid and the cover body, so as to expose the metal contact.
9. The method of claim 7 or 8, wherein the mark on the substrate is a metal material.
10. The method of claim 7 or 8, further comprising performing a baking process before the stripping process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510536960.4A CN106486429A (en) | 2015-08-27 | 2015-08-27 | Semiconductor chip package and its method for packing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510536960.4A CN106486429A (en) | 2015-08-27 | 2015-08-27 | Semiconductor chip package and its method for packing |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106486429A true CN106486429A (en) | 2017-03-08 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510536960.4A Pending CN106486429A (en) | 2015-08-27 | 2015-08-27 | Semiconductor chip package and its method for packing |
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Citations (4)
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| US20050224949A1 (en) * | 2001-09-28 | 2005-10-13 | Renesas Technology Corp. | Semiconductor device and method of fabricating the same |
| US20080136001A1 (en) * | 2006-03-20 | 2008-06-12 | Micron Technology, Inc. | Carrierless chip package for integrated circuit devices, and methods of making same |
| CN101421833A (en) * | 2003-12-09 | 2009-04-29 | 飞思卡尔半导体公司 | Land grid array packaged device and method of forming same |
| CN104779221A (en) * | 2015-04-08 | 2015-07-15 | 南昌欧菲生物识别技术有限公司 | Fingerprint identification module packaging structure, method for preparing fingerprint identification module packaging structure as well as electronic equipment |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050224949A1 (en) * | 2001-09-28 | 2005-10-13 | Renesas Technology Corp. | Semiconductor device and method of fabricating the same |
| CN101421833A (en) * | 2003-12-09 | 2009-04-29 | 飞思卡尔半导体公司 | Land grid array packaged device and method of forming same |
| US20080136001A1 (en) * | 2006-03-20 | 2008-06-12 | Micron Technology, Inc. | Carrierless chip package for integrated circuit devices, and methods of making same |
| CN104779221A (en) * | 2015-04-08 | 2015-07-15 | 南昌欧菲生物识别技术有限公司 | Fingerprint identification module packaging structure, method for preparing fingerprint identification module packaging structure as well as electronic equipment |
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